JPS63234721A - Inverter circuit - Google Patents

Abstract

PURPOSE:To simultaneously obtain a high load driving capacity and a high speed by composing the titled circuit of a switching step and a push-pull type outputting step, and using a coupling capacitor for a level shift. CONSTITUTION:When VH=5V is inputted as an input, the gate potential of a MESFET3 is clamped to about 0.5V. At such a time, FET3 is turned on. At the same time, MESFET7 comes to be turned on. Therefore, the gate electric potential of a MESFET6 comes to be VL=1V and an FET6 comes to be turned off. At such a time, an output comes to be VL=1V. Next, when the input comes to be VL=1V, in accordance with the change of this input, a charge distribution is generated between the gate capacities of FET 3 and 7 and the coupling capacitor, the gate electric potential of the FET3 and 7 come to be about -2V and the FET3 and 7 come to be turned off. At such a time, the gate potential of th FET6 comes to be about VH=5V and the FET6 comes to be turned on. Therefore, the output comes to VH=5V.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an inverter circuit that can be used for high frequency oscillator 1 frequency dividers, optical communications, and the like.

BACKGROUND OF THE INVENTION In general, depletion-type MESFETs have advantages over enhancement-type MESFETs, such as high speed, high current drive capability, and ease of manufacture.

Furthermore, a capacitively coupled logic circuit (Capacitor-Coupled logic circuit) is constructed using a method called capacitor coupling.
Logic (CCL)) enables level shifting with low power consumption and can operate with one power supply.

Hereinafter, a conventional capacitively coupled logic circuit as described above will be explained with reference to the drawings.

FIG. 2 shows a conventional capacitively coupled logic circuit (CCL). In FIG. 2, 10 and 11 are both depletion type MESFETs, 9 is a coupling capacitor for level shifting, 5 is a single power supply (5V) terminal, and 1 and 8 are an input terminal and an output terminal, respectively.

The operation of the capacitively coupled logic circuit configured as described above will be described below.

First, when V)l=5V is input, MESFET lo
The gate potential of MESFETIO is clamped to about 0.5V by the gate-source forward diode of MESFETIO.

At this time, MESFETIO is on.

Next, when the input becomes VL=IV, charge distribution occurs between the gate capacitance of MESFETIO and the coupling capacitor 9 according to this input change, the gate potential of MESFETIO becomes negative, and MESFETIO is turned off. That is, a power supply voltage of 5V (VH) is obtained as an output.

Once the coupling capacitor 9 is charged in this way, (
This circuit operates as an inverter (provided the input frequency is fast enough to sustain this charge).

Problems to be Solved by the Invention However, the above configuration is a radio circuit. That is, the switching transistor 10
If the size of the load transistor 11 is made larger than the size of the load transistor 11, the switching speed becomes faster, but there is a drawback that the load driving capability output logic amplitude becomes smaller.

In view of the above drawbacks, the present invention provides a single power supply inverter circuit that simultaneously has high load driving capability and high speed performance regardless of the ratio of switching transistors to load transistors.

Means for Solving the Problems In order to solve the above problems, the inverter circuit of the present invention is comprised of a switching stage and a bush-pull type output stage.

Effect: Due to this configuration, the present circuit does not become a radio circuit; high-speed switching is possible by increasing the size of the switching transistor, and high-load driving capability can be achieved by increasing the size of the transistor in the output section.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of an inverter circuit in an embodiment of the present invention. In Figure 1, 3.4.6,7
．． are depletion type MESFETs, 3 serves as a switching purpose, 4 serves as a load, and 6 and 7 serve as an output purpose. 2 is a coupling capacitor for level shifting, 5 is a terminal of a single power supply Voo (5V), and 1 and 8 are an input terminal and an output terminal, respectively.

The operation of the inverter circuit configured as described above will be explained.

First, when VH=5V is input, the MESFET
The gate potential of MESFET 3 is clamped to approximately 0.5V by the gate-source forward diode of MESFET 3. At this time, MESFET3 is on. At the same time M
ESFET7 is also turned on. Therefore, MESFE
The gate potential of T6 becomes approximately VL=IV, and the MESFET
6 is off. At this time, the output becomes VL=IV. Next, when the input becomes VL=IV, charge distribution occurs between the gate capacitance of MESFET 3.7 and the coupling capacitor 2 according to this input change, and the gate potential of MESFET 3.7 becomes about 12V, turning MESFET 3.7 off. becomes. At this time, the gate potential It of MESFET6
VH=approximately 5 V and MESFET 6 is turned on. Therefore, the output becomes VH=5V.

As described above, according to this embodiment, since the coupling capacitor 2 is used for level shifting, the normally-on type MES
It has the feature that a single power supply inverter can be constructed using only FETs. Furthermore, since the output section and the switching stage are separated, the device does not become a ratio circuit, and has the feature of being able to simultaneously achieve high switching speed and high load driving capability.

Effects of the Invention As described above, the present invention uses a coupling capacitor for level shifting to create a single power supply inverter circuit consisting only of depletion type MESFETs that is easy to manufacture and has high speed and high load driving ability. Furthermore, by separating the output section and the switching section, high-speed, high-load driving capability can be obtained regardless of circuit parameters, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an inverter circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional inverter circuit. 1...Input terminal, 2...Coupling capacitor, 3゜4.6.7...MESFET, 5...
...Power terminal (5V), 8...Output terminal. Agent's name Patent attorney Toshio Nakao One idiot l --- Manpower Q'! r z9-m-coupling content J, 4.6.710.II --- Schottky Kenito's G kidneys

Claims (2)

[Claims] (1) Consisting of a switching section in which a first transistor and a second transistor are connected in series, and an output section in which a third transistor and a fourth transistor are connected in series; Source terminals of the first and third transistors are both grounded, a drain of the first transistor is connected to a source of the second transistor, and a gate of the first transistor is connected to an input terminal via a capacitor. , a connection point between the drain of the third transistor and the source of the fourth transistor is connected to an output terminal, the drains of the second transistor and the fourth transistor are each connected to a power supply, and the second The gate of the transistor and the gate of the fourth transistor are commonly connected to the source terminal of the second transistor, and the gate of the first transistor and the gate of the third transistor are connected. Characteristic inverter circuit. (2) The inverter circuit according to claim 1, wherein the transistor is a normally-on type MESFET or a normally-on type J-FET.