JP2539908B2 - Semiconductor logic circuit - Google Patents

Description

The present invention relates to a semiconductor logic circuit, and more particularly to a semiconductor logic circuit using a Schottky gate field effect transistor (MESFET).

[Conventional technology]

Along with the development of the information-oriented society, there is an increasing demand for a device that performs higher-speed information processing, and a semiconductor device that constitutes the device is also required to operate at a higher speed. The gallium arsenide integrated circuit (GaAs IC) is expected to contribute to these fields due to the characteristics of GaAs itself such as high electron mobility and semi-insulating substrate.

Figure 3 shows SCFL (Source Cou
pled FET Logic) shows the inverter circuit. In the figure, reference numerals 21 and 22 are load elements and reference numeral 2
Reference numerals 25 and 27 are source follower transistors, reference numerals 26 and 28 are level shift elements, reference numerals 29, 30, and 31 are constant current sources, reference numerals 32 and 33 are power supply terminals, and reference numeral 34. , 35 are input terminals, and reference numerals 36 to 39 are output terminals. The input signal is supplied to the input terminals 34 and 35 complementarily, and the basic output signal can be obtained from the output terminals 36 and 37.

In the SCFL circuit, the depletion type is generally used for the transistor, and it is necessary to make the potential of the output signal lower than the drain terminal of the driving transistor because of the compatibility with the logic circuit in the next stage. 40
Is added. In this circuit, the signal level is shifted by the gate-source voltage of the source follower transistors 25 and 27.

By the way, the SCFL circuit has a feature that logic gates can be vertically stacked. The circuit shown in FIG. 4 is an SCFL circuit in which logic gates are vertically stacked, and realizes a 3-input NAND (NAND) circuit. However, in this circuit, the level shift sof follower circuit for setting the output level to a desired level is omitted. This circuit includes a pair of load elements 41, 42 and a driving transistor 43-
48 and a constant current source 49, and V _DD and V _SS are applied to power supply terminals 50 and 51, respectively. Driving transistor
A complementary input signal A is applied to the gates of 43 and 44,
However, a complementary input signal B is applied to the gates of the driving transistors 45 and 46, and
A complementary input signal C is given to the gates of 7 and 48, a logical operation process is performed by each driving transistor pair, and a complementary output signal Q appears at the output terminals 58 and 59.

[Problems to be Solved by the Invention]

By the way, the structure of the MESFET used in the above-mentioned SCFL circuit tends to have a shorter gate. The reason why the gate length of the MESFET is shortened is to reduce the capacitance of the FET itself and improve the transconductance g _m to improve the performance of the IC. However, it is known that as the gate length is shortened, a negative phenomenon called a short gate effect occurs. Ie MESF
The drain current of the ET originally shows a characteristic as a constant current current without depending on the drain-source voltage. However, if the gate length is extremely short, the constant current characteristic is destroyed due to the change in the drain voltage. This phenomenon is particularly remarkable in FETs having a gate length of 1 μm or less.

Now, consider the case where such a short gate MESFET is used as the driving transistors 43 to 48 of the vertically stacked SCFL circuit of FIG. Since the drain terminals of the driving transistors 43 and 44 are both directly connected to the load elements 41 and 42, the symmetry with respect to the drain voltage is maintained. However, regarding the pair of driving transistors 45 and 46, the drain of the driving transistor 45 is connected to the load element 41 via the driving transistor 43 that handles a higher level signal, whereas The drain is directly connected to the load element 42. Therefore, the driving transistor 46
Has a higher drain terminal voltage than the drain terminal voltage of the driving transistor 45. Then, the characteristics of the driving transistors 45 and 46 become different due to the short gate effect, which hinders the operation of the logic circuit. The driving transistors 47 and 48 have a larger difference in drain voltage.

[Means for solving the problem]

In order to solve the above-mentioned problems, the semiconductor logic circuit of the present invention relates to at least one driving transistor pair in a vertically stacked SCFL circuit, and handles another high-level signal connected in series with a load element. The voltage compensating transistor is connected in series to the drain of the driving transistor having the smaller number of stages of the driving transistor.

[Action]

When the voltage compensating transistor is added to one of the paired driving transistors, the operating drain terminal voltages of the two driving transistors become substantially equal. Therefore, even if the MESFETs having a short gate length, in which the constant current characteristics are somewhat impaired due to the short gate effect, are used as the driving transistors, they operate in the same operating region. Therefore, the current switching operation by the driving transistor pair is stable.

〔Example〕

FIG. 1 is a circuit diagram showing a 3-input NAND circuit according to an embodiment of the present invention. The circuit of this embodiment is different from the 3-input NAND circuit of the conventional SCFL circuit shown in FIG. 4 in that voltage compensating transistors 60 and 61 are added.

The voltage compensating transistor 60 is connected to the drain of the driving transistor 46 connected to the load element 42 side of the driving transistors 45 and 46 in order to equalize the operating drain terminal voltages of the driving transistors 45 and 46 in the middle stage. Has been done. The gate of the voltage compensating transistor 60 is a high-level driving transistor of the driving transistor 46, and a signal given to the gate of the driving transistor 44 connected to the load element 42 side similarly to the driving transistor 46. The same number, that is, the input signal is given.

The voltage compensating transistor 61 is placed to equalize the drain terminal voltages of the lower-stage driving transistors 47 and 48, and the gate thereof is that of the driving transistor 46 connected to the load element 42 side of the driving transistors 45 and 46. It is connected to the gate and receives the input signal.

Since the present embodiment is configured in this way, the number of transistors interposed between the respective drains of the pair of driving transistors and the load element is equal in each stage. Therefore, the operating drain terminal voltage of the driving transistor is uniform for each driving transistor pair.

FIG. 2 shows another embodiment of the present invention, in which a voltage compensating transistor 61 is added only to a pair of lower driving transistors 47 and 48 in a 3-input NAND circuit. Also in this embodiment, for example, when the input signal becomes high level, the driving transistor 47 is connected to the load element 42 via the higher level driving transistor 46, and the driving transistor 48 becomes the voltage compensating transistor.
It is also connected to the load element 42 via 61. Therefore, the operating drain terminal voltages of the driving transistors 47 and 48 become substantially equal.

As described above, in each of the embodiments, the same signal as the signal given to the driving transistor of the higher level is given to the gate of the voltage compensating transistor, but a fixed voltage may be given.

In this embodiment, the level-following source follower circuit for converting the output signal level to a desired level is omitted. However, if this circuit is added, for example, the input signal A and the output signal Q, The levels of can be matched.

Further, both of the above-mentioned two embodiments are three-input NAND circuits, but various logic circuits can be assembled by changing the number of stages or the connection of the driving transistor pair.

〔The invention's effect〕

As described above, according to the semiconductor logic circuit of the present invention, the operating drain terminal voltage points of the pair of driving transistors forming the differential logic gate can be aligned.
Therefore, even if a MESFET having a short gate length, in which the constant current characteristic is somewhat impaired due to the short gate effect, is used as a driving transistor, the paired driving transistors operate in the same operating region. Therefore, the current switching operation by the driving transistor pair is stable.
In other words, according to the semiconductor logic circuit of the present invention, an IC can be manufactured with a high yield even with a short gate effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, FIG. 3 is a circuit diagram showing an inverter using a conventional SCFL circuit, and FIG. It is a circuit diagram which shows the 3 input NAND circuit by the conventional SCFL circuit. 41, 42 ... load element, 43 to 48 ... drive transistor,
49 …… constant current source, 50, 51 …… power supply terminal, 52 to 57 …… input terminal, 58, 59 …… output terminal, 60, 61 …… voltage compensation transistor.

Claims (1)

(57) [Claims] 1. A pair of load elements, a plurality of pairs of driving field effect transistors whose sources are connected to each other, and a constant current source, wherein each driving field effect transistor pair includes a driving field effect transistor pair. A semiconductor logic in which the drain is connected to the source of the driving field effect transistor pair that handles an upper level signal or the load element, and the source of the driving field effect transistor pair that handles the lowest level signal is connected to a constant current source. In the circuit, regarding at least one driving field effect transistor pair, a driving field effect transistor having a smaller number of stages of other driving field effect transistors for handling high-level signals connected in series with the load element A field-effect transistor for voltage compensation is connected in series to the drain, and the gate of this field-effect transistor for compensation is connected. Semiconductor logic circuit connected to the gate of the other driving field effect transistor for handling the signal of the higher level.