JPH0444422A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To make a logic operation due to current switching stable by adding a voltage compensation transistor(TR) to one of driving TRs in pairs. CONSTITUTION:A voltage compensation TR 60 is connected to the drain of a drive TR 46 connected to a load element 42 in driving TRs 45, 46 so as to make the operating drain terminal voltage of the intermediate-stage drive TRs 45, 46 equal to each other. The gate of the voltage compensation TR 60 is connected to the common source terminal of driving TRs 43, 44 located at a higher level than the level of the gate driving TR 46. A voltage compensation TR 61 is provided to make the drain terminal voltages of the lower-stage drive TRs 47, 48 equal and the gate of the TR 61 is connected to the common source of the intermediate-stage driving TRs 45, 46.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor logic circuits, and particularly to semiconductor logic circuits using Schottky gate field effect transistors (MESFETs).

[Conventional technology]

2. Description of the Related Art With the development of an information society, the demand for devices that process information at higher speeds has increased, and the semiconductor devices that make up these devices are also required to operate at higher speeds. Gallium arsenide integrated circuit (GaAs IC) is 1. Ga
Due to the characteristics of As itself, such as its high electron mobility and semi-insulating substrate, it is expected to contribute to these fields.

Figure 3 shows SCF L, which is often used for GaAs1C.
(Source Coupled FET Logic
) circuit. In the figure, 21.22 is a load element, 23.24 is a driving transistor, 25.27 is a source follower transistor, 26.28 is a level shift element, and 29.30.31 is a constant current. 32 and 33 are power supply terminals, 34 and 35 are input terminals, and 36 to 39 are output terminals, respectively. The input signals are provided complementary to the input terminals 34.35, and the fundamental output signal can be obtained from the output terminals 36.37.

The 5CFL circuit operates by distributing current through two paired FETs, so if the characteristics of the two FETs are the same, the center value of the characteristics does not have a big effect on the operation. . Therefore, there is a wide range of selection for the threshold value of the FET, and when operation with low current consumption is desired, an FET with a shallow threshold value that can obtain a relatively large value is used. Here, the K value refers to a constant in the following equation.

I = K (VG - VT) 5at IDsat' Drain saturation current ■G: Gate voltage V T: L threshold voltage Note that the 5CFL circuit when an enhancement type FET with a large K value is used is especially LSCF L (Lo
w-power 5source Coupled FE
It is sometimes called a T Logic circuit.

By the way, the 5CFL circuit has the feature that logic gates can be vertically stacked. The circuit shown in FIG. 4 is a 5CFL circuit in which logic gates are vertically stacked, and realizes a three-manpower NAND (NAND) circuit. However, this circuit does not include a level shift source follower circuit for adjusting the output level to a desired level.

This circuit is composed of a pair of load elements 41, 42, driving transistors 43 to 48, and a constant current source 49, and DD SS is applied to power supply terminals 50 and 51, respectively. Complementary input signals A, A are applied to the respective gates of the driving transistors 43 and 44, and
The gates of the driving transistors 45, 46 are supplied with complementary input signals B, B, or in addition, the driving transistors 47.4.
Complementary input signals C and C are applied to the gates of 8, and logical operation processing is performed by each pair of driving transistors.
Complementary output signals Q, Q appear at output terminals 58,59.

[Problem to be solved by the invention]

By the way, the MESF used in the 5CFL circuit mentioned above
ET structures tend to have shorter gates.

The purpose of shortening the gate length of a MESFET is to reduce the capacitance of the FET itself and drain conductance g.

This is to improve the performance of the IC.

However, it is known that as the gate length is shortened, a negative phenomenon called the short gate effect occurs.

In other words, the drain current of a MESFET does not originally depend on the drain-source voltage and exhibits characteristics as a constant current source, or if the gate length is extremely short, the constant current characteristics will be lost due to changes in the drain voltage. . This phenomenon is particularly noticeable in FETs with gate lengths of 1 μm or less.

Here, the M E S F E T of such a short gate
The driving transistor 4 of the vertically stacked 5CFL circuit in Fig. 4
Let's consider the case where it is used for 3 to 48. The drain terminals of drive transistors 43 and 44 are both connected to load elements 41 and 42.
Symmetry is maintained with respect to the drain voltage as it is directly connected to the drain voltage. However, the driving transistor 45.4
Regarding pair No. 6, the drain of the driving transistor 45 is connected to the load element 41 via the driving transistor 43 that handles upper level signals, whereas the drain of the driving transistor 46 is connected directly to the load element 42. It is connected. Therefore, the drain terminal voltage of the driving transistor 46 is higher than the drain terminal voltage of the driving transistor 45. Then, the characteristics of the driving transistors 45 and 46 become different due to the short gate effect, which impedes the operation of the logic circuit. For drive transistors 47 and 48, an even larger difference in drain voltage occurs.

[Means to solve the problem]

In order to solve the above problems, the semiconductor logic circuit of the present invention relates to at least one pair of driving transistors in a vertically stacked 5CFL circuit, and other transistors that handle higher level signals connected in series with a load element. A voltage compensation transistor is connected in series to the drain of the drive transistor with fewer stages of drive transistors, and the gate of the voltage compensation transistor is connected to the drive transistor pair in a common state. connected to the source. Furthermore, the threshold voltage of the voltage compensation transistor is on the negative side than that of the driving transistor.

[Effect]

By adding a voltage compensation transistor to one of the pair of driving transistors, the drain terminal voltages of the two driving transistors become approximately equal. Therefore, even if a drive transistor with a gate length so short as to cause a short channel effect is used, the two drive transistors have the same characteristics, and the logic operation can be stabilized by the current switching operation.

Note that even if an E-FET is used as a driving transistor to reduce current consumption, a transistor whose threshold voltage is on the negative side than that of the driving transistor is used as a voltage compensation transistor. Because
The voltage drop between the gate and the source is small, and the drain voltage of the driving transistor compensated by the voltage compensating transistor does not drop too much.

〔Example〕

FIG. 1 is a circuit diagram showing a three-person NAND circuit which is an embodiment of the present invention. The circuit of this embodiment differs from the conventional three-man NAND circuit using a 5CFL circuit shown in FIG. 4 in that voltage compensation transistors 60 and 61 are added.

The voltage compensation transistor 60 is connected to the load element 4 of the drive transistors 45 and 46 in order to equalize the operating drain terminal voltages of the drive transistors 45 and 46 in the middle stage.
It is connected to the drain of the driving transistor 46 connected to the second side.

The gate of the voltage compensation transistor 60 is connected to the driving transistors 43 and 44 at the upper level of the driving transistor 46.
connected to the common source terminal of the

The voltage compensation transistor 61 is placed to equalize the drain terminal voltages of the lower drive transistors 47 and 48, and its gate is connected to the middle drive transistors 45 and 46.
connected to the common source terminal of the

As already mentioned, as a driving transistor,
E-FETs with large K values are increasingly being used, but as voltage compensation transistors
When a -FET is used, a voltage drop occurs between the gate and source of the FET, and the voltage at the drain terminal of the driving transistor to which the voltage compensation transistor is connected becomes lower than necessary. However, in this embodiment, since a D-FET is used as the voltage compensation transistor, a voltage drop is not generated between the gate and source of the D-FET. Terminal voltages become equal.

Since this embodiment is constructed in this manner, the drain terminal voltages of the pair of driving transformers and stars can be made equal in each stage.

FIG. 2 shows another embodiment of the present invention, in which a voltage compensation transistor 61 is added only to the pair of drive transistors 47 and 48 in the lower stage, where voltage compensation has a large effect in a three-man NAND circuit. It is.

Note that in both of the above two embodiments, the present invention is applied to a three-person NAND circuit, but the present invention is not limited to this, and the number of stages and connections of driving transistor pairs can be changed. It can be applied to various logic circuits that can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor logic circuit of the present invention, the operating drain terminal voltage points of a pair of driving transistors constituting a differential logic gate can be aligned. Therefore, even if a MESFET with a short gate length whose constant current characteristics are somewhat impaired due to the short gate effect is used as a driving transistor, the paired driving transistors operate in the same operating range. Therefore,
The current switching operation by the driving transistor pair is stable. In other words, according to the semiconductor logic circuit of the present invention, ICs can be manufactured with high yield even against short gate effects.

4 are circuit diagrams showing a three-person canant circuit using a conventional 5CFL circuit.

41.42... Load element, 43-48... Drive transistor, 49... Constant current source, 50.51... Power supply terminal, 52-57... Input terminal, 58.59... Output Terminal, 60.61... Voltage compensation transistor.

Claims (1)

[Claims] 1. A pair of load elements, a plurality of pairs of driving field-effect transistors whose sources are connected to each other, and a constant current source, and each pair of driving field-effect transistors has a driving electric field. The drain of the effect transistor is connected to the source of a driving field-effect transistor pair that handles an upper-level signal or to the load element, and the source of the driving field-effect transistor pair that handles a lowest-level signal is connected to a constant current source. In a semiconductor logic circuit, with respect to at least one pair of driving field effect transistors, the driving electric field of the other driving field effect transistor connected in series with the load element and handling a higher level signal has a smaller number of stages. A voltage-compensating field-effect transistor is connected in series to the drain of the effect transistor, and the voltage-compensating field-effect transistor has a gate terminal common to the driving field-effect transistors whose gate terminal is located above the pair of driving field-effect transistors. A semiconductor logic circuit connected to a source terminal, the threshold voltage of which is on the negative side of that of a driving field effect transistor. 2. The semiconductor logic circuit according to claim 1, wherein the driving field effect transistor is an enhancement type, and the voltage compensation field effect transistor is a debleation type.