JPH02241115A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by stacking plural logic circuits compris ing a current changeover circuit longitudinally to a constant current source. CONSTITUTION:A lower-stage logic circuit 125 and an upper stage logic circuit 126 are formed, sources of drive transistors(TRs) 101, 102 of the lower stage logic circuit 125 are connected together and connected to a power terminal 127 of a voltage VSS via a constant current source 113 and a drain of a signal level adjustment TR 105 connects to one load element 111 of the upper stage logic circuit 126. Then the signal of the lower stage logic circuit 126 is sent to the upper stage logic circuit 126 whose logic signal level differs not through a level shift means. That is, when a complementary input signal is given to gates of a couple of drive TR of the current switching circuit of each stage, a level in response to an input signal supplied to the driving TR of the stage and the drive TR of the current switching circuit placed lower than the stage appears at the load element terminal of the current switching circuit of each stage as the output signal of the stage. Thus, the circuit is operated with low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor logic circuits, and particularly to semiconductor logic circuits using Schottky gate field effect transistors (MESFETs).

[Conventional technology]

2. Description of the Related Art With the development of an information society, the demand for devices that process information at higher speeds has increased, and the semiconductor devices that make up these devices are also required to operate at higher speeds. Gallium power product circuits (GaAslC) are expected to contribute to these fields due to the characteristics of GaAs itself, such as its high electron mobility and semi-insulating substrate.

Figure 2 shows SCF L, which is often used for GaAs1C.
(Source Coupled PET Logic
) circuit. In the figure, 21.22 is a load element, 23.24 is a driving transistor, 25.27 is a source follower transistor, 26.28 is a level shift element, and 29.30.31 is a constant current. 32 and 33 are power supply terminals, 34 and 35 are input terminals, and 36 to 39 are output terminals, respectively. The input signals are provided complementary to the input terminals 34.35, and the fundamental output signal can be obtained from the output terminals 36.37.

In a 5CFL circuit, a depletion type transistor is generally used for the transistor, and for consistency with the next stage logic circuit, the potential of the output signal needs to be lower than the drain terminal of the driving transistor, so a source follower circuit is used. 4
0 is added.

In this circuit, the signal level is shifted by the voltage between the gate and source of the source follower transistors 25 and 27.

[Problem to be solved by the invention]

By the way, GaAs used in the 5CFL circuit
Since the MESFET is a monopolar device, it is free from the minority carrier accumulation effect that occurs in silicon (Si) bipolar transistors and can operate at low voltages. However, with emphasis on compatibility with conventional logic circuit systems, GaA s M E S F E
It is often operated at a high power supply voltage that is more than sufficient for T. Therefore, the original characteristic of low power consumption could not be fully utilized.

An object of the present invention is to solve these problems, and to provide a semiconductor logic circuit that can operate with substantially low power consumption when applied to a system that operates at a high power supply voltage. It is in.

[Means to solve the problem]

In order to solve the above problems, a semiconductor logic circuit of the present invention includes a pair of load elements, the sources of which are connected to each other, the drain of one of which is directly or indirectly connected to one of the load elements, and the drain of the other connected to the load element. n (n is any natural number of 2 or more) current switching circuits each having one or more driving field-effect transistor pairs connected directly or indirectly to the other side of the element are connected to one constant current source. If the bottom stage is the first stage and the top stage is the nth stage, then the two load elements of the current switching circuit of any 9th stage (1≦ρ≦n-1) are separately connected to the source or load element of any pair of drive field effect transistors in the (N+1)th stage via signal level adjustment field effect transistors.

[Effect]

When complementary input signals are applied to the gates of a pair of driving transistors in each stage of current switching circuit, the load element terminals of the current switching circuit in each stage are connected to the driving transistor in that stage and the driving transistor in the stage below. A potential corresponding to the input signal applied to the driving transistor of the current switching circuit located there appears as an output signal of the relevant stage.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which two logic circuits and a constant current source are stacked vertically with respect to a power supply. That is, a lower stage logic circuit 125 and an upper stage logic circuit 126 are formed with the dashed-dotted line in the figure as a boundary.

Driving transistor 101.10 of lower logic circuit 125
2 are connected to each other, and a constant current source 113
It is connected to the power supply terminal 127 of voltage v88 via. Load elements 103 and 104 are connected to the drains of the drive transistors 101 and 102, respectively, and the other ends of the load elements 103 and 104 are connected to the sources of signal level adjustment transistors 105 and 106, respectively.

The gates of the signal level adjustment transistors 105 and 106 are both connected to a terminal 116 to which a fixed potential vLS is applied. Each gate of the driving transistors 101 and 102 is connected to an input terminal 114 and 115 of the input signal A1A, respectively.

At the drain of the signal level adjustment transistor 105,
It is connected to one load element 111 of the upper logic circuit 126. The sources of the first set of driving transistors 107 and 108 of the upper logic circuit 126 are commonly connected to the drain of the signal level adjustment transistor 106.

The load element 1 is connected to the drain of the driving transistor 107.
11 is connected to the drive transistor 108, and the sources of the second set of drive transistors 109 and 110 of the upper logic circuit 126 are commonly connected to the drain of the drive transistor 108. Each drain of the second set of drive transistors 109.110 is connected to a load element 111.112, and the other end of the load element 111.112 is connected to a power supply voltage v8. are commonly connected to a power supply terminal 128 to which is applied. Each gate of the first set of driving transistors 107 and 108 is
The input terminals 117 and 118 for the input signals B and B are connected, and the gates of the second set of drive transistors 109 and 110 are connected to the input terminals 119 and 120 for the input signals C and C, respectively.

The lower logic circuit 125 of the logic circuit of this embodiment configured as described above is an inverter. In addition, the upper logic circuit 12
6 is a two-person Kanoa (NOR) circuit, but as will be described later, it is logically connected to the lower logic circuit 125 via a current, so that it essentially constitutes a three-person Kanoa circuit.

The signal level of the lower logic circuit 125 is determined by the value of the voltage L8 applied to the gates of the signal level adjusting transistors 105 and 106, and the voltage V is selected to be, for example, an intermediate type S between the power supply voltages vDD and v88. Therefore, the average logic signal level of lower logic circuit 125 is lower than voltage vLs. Further, the average signal level of the output signals Q1 and Ql is higher than the average signal level of the input signals A and A.

Note that the gate width of the signal level adjustment transistors 105 and 106 is the same as that of the driving transistors 101 and 106.
A gate width larger than the gate width of 2 is used, thereby stabilizing its source potential.

The logic signal level of the upper logic circuit 126 is determined by the voltage vL applied to the gate of the signal level adjustment transistor 105.
A value higher than 8 is selected and the input signal C1
The average signal level of C is selected to be higher than the average signal level of input signals B and B. Output signal Q2
, Q2 is higher than the average signal level of input signals C and C.

The upper logic circuit 126 itself is a two-person circuit with input signals B and C, but since the current switching state of the lower logic circuit 125 affects the output, three of the input signals ASBSC are sent to the output terminals 124 and 125. An output signal appears as a human circuit. In other words, output signal Q2 is at high level (Q2
becomes low level). In this way, the lower logic circuit 12
The signals of 5 are connected to the upper logic circuit 12 with different logic signal levels.
6 without going through any level shift means.

Note that in this embodiment, the input signal level and the output signal level do not match, but in order to adjust the logic signal level,
A source follower circuit for level shifting may be added.

Further, in this embodiment, the lower stage logic circuit is an inverter and the upper stage logic circuit is a two-person Kanoa circuit, but the logic configuration of each stage is not limited to this embodiment, and various conventional circuit configurations can be used. You can build logic circuits. Also,
The number of stages is not limited to two, upper and lower, but may be three or more as long as the power supply voltage allows.

〔Effect of the invention〕

As explained above, according to the semiconductor logic circuit of the present invention, a plurality of logic circuits each consisting of a current switching circuit are vertically stacked for one constant current source, so that each independent logic circuit Power consumption can be significantly reduced compared to conventional semiconductor logic circuits having constant current sources. Moreover,
In each stage of the logic circuit of the present invention, an output signal from a logic circuit located at a stage lower than itself is transmitted as a current switching state. In other words, even if you want to transmit the output of a lower logic circuit to an upper logic circuit with a different logic level,
Level shifting means with large current consumption is not required.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an inverter using a conventional 5CFL circuit. 101.102.107.108.109.110...
・Drive transistor, 103.104.111.11
2... Load element, 113... Constant current source, 105.1
06...Signal level adjustment transistor, 125...
・Lower logic circuit, 126...Upper logic circuit, 127・
...Power supply V terminal, 128...Power supply VDD terminal. S Patent applicant Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] A pair of load elements, the sources of which are connected to each other, the drain of one of which is connected directly or indirectly to one of the load elements, and the drain of the other connected directly or indirectly to the other of the load elements. n (n is any natural number of 2 or more) current switching circuits each having one or more driving field effect transistor pairs (n is any natural number greater than or equal to 2) are stacked vertically with respect to one constant current source. Assuming that the first stage is the first stage and the top stage is the nth stage, the two load elements of the current switching circuit of the arbitrary first stage (1≦l≦n-1) each have a field effect transistor for signal level adjustment. A semiconductor logic circuit that is separately connected to the source or load element of any pair of driving field effect transistors in the (l+1)th stage through the semiconductor logic circuit.