JPH02182026A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To constitute a gate logic circuit stacked longitudinally and withstanding the dispersion in the component by employing an enhancement type MESFET for a driving transistor(TR), connecting an input terminal to its gate and connecting an output terminal to its drain. CONSTITUTION:Driving TRs 1, 2 are enhancement type MESFETs. Load elements 3, 4 are connected respectively to each drain of the driving TRs, the gate connects to input terminals 34, 35 and its drain connects to output terminals 36, 37 respectively. When a complementary input signal is given to the input terminals 34, 35, a current flows to either the TR 1 or the TR 2. When the input signal is switched, the current is also switched. When the input signal is inverted, the current is also switched and the output is also inverted. Since the enhancement type MESFET is employed for the driving TRs 1, 2, the output level is made coincident with the input signal level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor logic circuit, and particularly to a semiconductor logic circuit using a Schottky gate field effect transistor (MESFET).

[Conventional technology]

2. Description of the Related Art With the development of an information society, there is an increasing demand for devices that process information at higher speeds, and the semiconductor devices that make up these devices are also required to operate at higher speeds. GaAs
ICs are expected to contribute to these fields due to the characteristics of GaAs itself, such as high electron mobility and semi-insulating substrates.

Figure 4 shows SCF L, which is often used in GaAs ICs.
(Source Coupled FET Logi
c) shows an inverter circuit according to the circuit. In the same figure, 21.22 is a load element, and 23.24 is a load element.
is a driving transistor, 25.27 is a source follower transistor, 26.28 is a level shift element,
29, 30, 31 are current sources, 32, 33 are power supply terminals, 34, 35 are input terminals, and 36 to 39 are output terminals, respectively.

The human power signal is given to the input terminals 34.35 in a complementary manner,
The basic output signals are available at output terminals 36,37.

In a 5CFL circuit, a deregion type transistor is generally used for the transistor, and for consistency with the next stage logic circuit, the potential of the output signal needs to be lower than the drain terminal of the driving transistor, so a source follower circuit is used. 40 is always added. In the circuit shown in FIG. 3, the signal level is shifted by the voltage between the gate and source of the source follower transistors 25 and 27.

FIG. 5 shows a reset set flip-flop circuit (R5
-FF circuit).

This R5-FF circuit has transistors 41, 42, 43, and 44 added to the inverter shown in FIG.
．． Complementary locks C1C are applied to 46, respectively. FIG. 6 shows this R5-FF circuit as a symbol, and terminals D, QSQ, C, and C correspond to terminals 34, 35, 36, 37, 45, and 46 in FIG. 4, respectively. In this R3-FF circuit, when the clock C is at the 71 level, complementary human input signals applied to the terminals 34 and 35 are respectively inverted by the driving transistors 23 and 24 and level-shifted by the source follower transistors 25 and 27. is applied to the gates of driving transistors 41 and 42. When the clock C becomes low level from this state, the transistor 43 is turned off and the transistor 44 is turned on, so that the inverted signal of the signal applied to the driving transistor 41.42 is transferred to the source follower transistor 27.25.
This state is maintained while the clock C is at a low level.

Since the 5CFL circuit is a current switching type, it is resistant to variations in elements and has the advantage of being able to form a vertically stacked gate logic.

[Problem to be solved by the invention]

However, as described above, the 5CFL circuit always needs to include a source follower circuit, so it has the drawback of high power consumption due to the current in this part. Therefore, it was particularly unsuitable for large-scale circuits.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, a semiconductor logic circuit of the present invention includes a pair of driving transistors whose sources are connected in common, a pair of load resistors connected to each drain of these driving transistors, and a driving transistor. The drive transistor is an enhancement-type MESFET, and has an input terminal connected to its gate and an output terminal connected to its drain.

[Effect]

By applying a complementary input signal to each gate of each driving transistor, a current selectively flows to one of the driving transistors, so that the voltage as an output signal at the drain of each driving transistor is complementary. appears in Then, by switching the input signal, the current flowing through the drive transistor is switched, and the drain potential (output signal) of each drive transistor is inverted. Since an enhancement type MESFET is used as the driving transistor, the input signal level and the output signal level can be matched.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention, which constitutes an inverter. The driving transistor 1.2 is
It is an enhancement type MESFET. The respective sources of the driving transistors 1.2 are connected to each other, and are connected to a power supply terminal 33 at a voltage V88 via a constant current source 5. A load element 3.4 is connected to each drain of the driving transistor, and the other end of the load element 3.4 is connected to a power supply terminal 32 of voltage VDo. The gates of drive transistors 1 and 2 are connected to input terminal 3, respectively.
4.35, and the drains are connected to output terminals 36 and 36 respectively.
．． It is connected to 37.

When complementary input signals are applied to the input terminals 34, 35 of this circuit, a current flows through either driving transistor 1 or 2. Then, when the input signal is switched, the current is switched. For example, when a high level is applied to the gate of the driving transistor 1 and a low level is applied to the gate of the driving transistor 2, the driving transistor 1 is turned on and the output of the output terminal 36 is low level, and the driving transistor 1 is turned on and the output of the output terminal 36 is at a low level. The transistor 2 is turned off and the output of the output terminal 37 becomes high level. When the input signal is reversed, the current is also switched and the output is also reversed. Since the driving transistors 1.2 are enhancement-type MESFETs, the output level can be made to match the input signal level.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, in which R5
-Constitutes an FF circuit. In this circuit, an inverter consisting of a driving transistor 6.7 which commonly uses the load element 3.4 is added to the inverter shown in FIG.
Driving transistors 8 and 9 that are turned on and off are connected in series. And a driving transistor 6.
Transistors 7.6 with each drain on the opposite side of the transistor 7.
The inverter in the latter stage serves as a circuit for holding information. As can be seen from this circuit diagram, the output of the inverter at the front stage is given to the inverter at the rear stage for holding information without passing through the source follower circuit. The reason why a source follower circuit is not necessary is because an enhancement type drive transistor is used, and the input and output levels of each inverter are the same. However, the input/output level and the clock level do not match.

In this R5-FF circuit, when complementary human input signals and D bar are applied to the terminals 35 and 34, when the clock C is at a high level, the information is transferred to the driving transistor 1.
．． When the clock C becomes low level, that is, the clock C becomes high level, the information is held in the information holding inverter at the subsequent stage.

Figure 3 shows a mask and slave toggle flip-flop (MS-T) constructed by connecting two stages of R3-FF circuits.
F F ) circuit is shown. R5-F on the mask side
The QSQ output of the F circuit 10 is supplied to the DSD circuit of the R3-FF circuit 11 on the slave side, and the R5-FF circuit on the slave side
The QSQ output of the circuit 11 is applied to the mask side and is applied to the D input. In this manner, in the ~l5-TFF circuit, signal transmission is performed from the mask side to the slave side or between Q, Q, D, and D whose signal levels match, so the connection is easy.

〔Effect of the invention〕

As explained above, according to the semiconductor logic circuit of the present invention, since it is driven by current switching like the conventional 5CFL circuit, it is resistant to variations in elements and allows vertically stacked gate logic. Since there is no need for a source follower for level shifting, which is always necessary in the 5CFL circuit, power consumption is low and the number of active elements is small. Therefore, by using the circuit of the present invention, it becomes easy to further increase the scale of the integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an inverter which is one embodiment of the present invention, and FIG. 2 is a circuit diagram showing an RS-FF which is another embodiment of the present invention.
3 is a block diagram of an MS-TFF circuit configured using two stages of R3-FF circuits, FIG. 4 is a circuit diagram showing an inverter using a conventional 5CFL circuit, and FIG. 5 is a circuit diagram showing the circuit. is a circuit diagram showing an R5-FF circuit based on a conventional 5CFL circuit, and FIG. 6 is a diagram showing this R8-FF circuit in symbols. 112.6.7.8.9...Enhancement type FE
Driving transistor by T, 3.4...Load cord,
5... Current source, 32.33... ffi source terminal, 34
．． 35.36.37.45.46...Signal terminal. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Salt 1) Tatsuya Hibakata Seda J aru Ishino ＂゛-ri diagram MS-Ding Chinyouki diagram Meishinban I, R, 5-M gate return diagram ss choice ice, 3CFLff'' ``PF5-+= Innomarts Diagram

Claims (1)

[Claims] 1. A pair of driving transistors whose sources are connected in common, a pair of load resistors each connected to each drain of these driving transistors, and a current source connected to the source of the driving transistor, A semiconductor logic circuit in which the driving transistor is an enhancement type MESFET, an input terminal is connected to its gate, and an output terminal is connected to its drain.