JPH0271612A - Semiconductor logic circuit with improved active current source - Google Patents

Abstract

PURPOSE:To surely perform a push-pull operation, to heighten driving capacity, and to realize a stable logic operation by keeping the sum of the currents of a pair of current sources constant and varying the distribution ratio of the current. CONSTITUTION:When a signal of (H) is inputted to input IN1 and a signal of (L) to input IN2 after inverting their phases mutually, a transistor Q1 is turned on, a Q2 is turned off. Thereby, a Q4 is turned off, and a Q5 is turned on, and the gate of a Q7 is set at (L) during charging a capacitor C2, and the Q7 is turned off, and the source potential of the Q5 is shifted by the potential drop of a Schottky barrier diode comprising a level shift element 22, then, a signal of (H) is outputted to output OUT2. Also, a Q6 is turned on, then, out OUT1 goes to (L). As a result, it is possible to vary the distribution ratio of each current that flows on the Q6 and the Q7 by the push-pull operation as keeping the sum of the currents that flow on the Q6 and Q7 constant.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor circuits, particularly semiconductor circuits using Schottky gate field effect transistors (MESFETs), and more particularly to semiconductor logic circuits using Schottky gate field effect transistors (MESFETs). The present invention relates to an active current source circuit for a source follower in the output stage of the circuit.

Conventional technology Integrated circuits using compound semiconductors such as gallium arsenide (GaAs) have attracted attention in recent years due to their high speed, high frequency operation, and low power consumption, and their application to digital circuits is being actively promoted. There is. In compound semiconductor circuits such as GaAs, transistors are made of M
It is often composed of ESFET. As for logic gates, which are extremely important circuit elements of digital integrated circuits, various circuits using MESFETs are known.

Figure 2 shows SCF L (Source Couple), which is one of the typical conventional circuits using MESFET.
edFET Logic) circuit is shown.

The illustrated logic circuit is composed of a logic stage 10 and an output stage/level shift stage 12.

Logic stage 10 includes a pair of switching MESFETs Q1.
and Q2. The drains of the transistors Q1 and Q2 are connected to load resistors R1 and R2, respectively, and the load resistors R1 and R2 are further connected to the first power supply terminal 14 via a load resistor R3. Also, the gates of transistors Q1 and Q2 are connected to the input INI
and IN2, and receive input logic signals that are complementary to each other.

Furthermore, the sources of transistors Ql and Q2 are commonly connected and connected to the drain of MESFET Q3. The source of the transistor Q3 is connected to the second power supply terminal 16 via a current setting resistor R4.

This second power supply terminal 16 has a negative relationship with respect to the first power supply terminal 14. Further, the gate of the transistor Q3 is connected to the bias fixed voltage terminal 18 via a bias resistor R5. Therefore, transistor Q3
and resistors R4 and R5 constitute an active current source.

The drains of the transistors Q1 and Q2 are connected to the gates of a pair of MESFETs Q4 and Q5 of the output stage/level shift stage 12. Those transistors Q4 and Q
The drain of 5 is connected to the first power supply terminal 14. Further, the sources of transistors Q4 and Q5 are connected to level shifting elements 20 and 22 (for example, resistors, M
It is connected to the drains of a pair of MESFETs Q6 and Q7 via an ESFET, a Schottky barrier diode, etc.). The gates and sources of these transistors Q6 and Q7 are connected to the second power supply terminal 16. Transistors Q6 and Q7 thus constitute an active current source.

Respective nodes between the cathodes of level shifting elements 20 and 22 and the drain terminals of transistors Q6 and Q7 are connected to outputs 0UT1 and 0IJT2. Transistors Q4 and Q5 thus constitute a source follower.

A circuit with such a differential configuration can be expected to have a high operating yield because it can operate even if the characteristics of individual elements deviate from the designed values to some extent as long as there are no variations in characteristics within the chip. However, as the circuit scale increases, the normal source follower circuit shown in FIG. 2 lacks load driving ability, and high-speed operation cannot be expected.

Therefore, in order to increase the load driving capability of the source follower circuit, as shown in FIG. A method of control was devised.

In FIG. 3, the same elements as those of the circuit shown in FIG. 2 are given the same reference numerals and symbols, and explanations of the same elements will be omitted.

As is clear from the comparison with FIGS. 2 and 3, in the circuit of FIG. 3, the current 71FETQ for the source follower
The gate of No. 6 is connected to the drain terminal of the switching FET Q2 on the opposite side to the switching FET QI of the logic stage 10 to which the source follower FET Q4 is connected.
1 and is also connected to the bias fixed voltage terminal 18 via a bias resistor R6. Similarly, the gate of current source FET Q7 is connected to the switching FE of logic stage 10 to which its source follower FET Q5 is connected.
It is connected to the drain terminal of the switching FET QI on the opposite side to TQ2 via a capacitor C2, and is also connected to the bias fixed voltage terminal 18 via a bias resistor R7. Thus, the source follower circuit portion performs a push-pull operation.

By the way, in a 5CFL circuit, all FETs operate in the saturation region for high-speed operation and are designed to have a small logic amplitude, so the threshold voltage Vth
is selected from -0.1V to -0.4V. However, if a current source is configured by connecting the gate and source of an FET having such a shallow Vth, the current value of the current source changes drastically due to deviation from the designed value of Vih. For example, if the design value of the current source is 1 when the design value of Vth is -0.2V, a variation of ±0.1V in Vth will cause the current source to vary by 9 times from 0.25 to 2.25. It turns out.

Therefore, as shown in FIG. 4, the source terminals of FETQ6 and Q7 and the second
Generally, a current source is configured by connecting resistors R8 and R9 between the power supply terminals of the gate terminal and applying a fixed potential to the gate terminal from the bias fixed voltage terminal 18 via resistors R6 and R7. It is being done. In FIG. 4, the same elements as those of the circuit shown in FIG. 2 are given the same reference numerals and symbols, and explanations of the same elements will be omitted.

According to this configuration, the connected resistor acts as a negative feedback element, and as long as the fixed potential is stable, the dependence of the current on variations in Vth is reduced compared to a current source whose gate and source are simply shorted. can do.

Problems to be Solved by the Invention However, it is difficult to convert this configuration into a bushing with a source follower circuit.
If you try to apply it to a pull circuit, the source potential will change in response to changes in the gate potential of the current source FET, and as a result, the current value of the current source will be kept constant, so the bush-pull effect will be lost. I'll get lost.

Therefore, the present invention solves the above problems, and provides a semiconductor logic circuit that can realize stable logic operation by suppressing variations in drive capability due to variations in the threshold values of current source FETs for source followers of semiconductor logic circuits. This is what we intend to provide.

Means for Solving the Problems According to the present invention, a pair of switching FETs,
A source follower having a logic stage having an input and a pair of outputs capable of taking a pair of complementary output potentials, and a pair of source follower FETs each having a gate connected to the pair of outputs of the logic stage. and an active current source having a pair of current source FETs connected to respective source terminals of the pair of source follower FETs,
The gate of each of the pair of current source FETs is connected to a fixed bias voltage terminal via a resistor, and the gate of the source follower FET to which the current source FET is connected is connected to the logic stage to which the gate of the source follower FET is not connected. In the semiconductor logic circuit connected to the output of the current source FET via a capacitor, the source terminals of the current source FETs are commonly connected to each other, and the commonly connected source terminals connect the resistance element to the power supply terminal.

As described above, in the semiconductor circuit of the present invention, complementary signals are applied from the logic stage via the capacitor to the gate terminals of the pair of current source FETs for the source followers that constitute the output stage of the semiconductor logic circuit. In addition, the source terminals of the pair of current source FETs are connected in common and are also connected to a power supply terminal via a resistor.

With this configuration, it is possible to change the current distribution ratio for the bush-pull operation while keeping the sum of the currents of both types of current sources constant. Therefore, the bush-pull operation can be performed reliably, and a circuit with a large driving capacity can be realized.

Embodiments Hereinafter, embodiments of a semiconductor logic circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor logic circuit according to the present invention. The semiconductor logic circuit of this embodiment is an inverter circuit similar to the conventional semiconductor logic circuit shown in FIGS. 2 to 4, and the circuit of the conventional semiconductor logic circuit shown in FIGS. Identical circuit elements have the same reference numbers or symbols.

The semiconductor logic circuit according to the present invention shown in FIG.
0 and an output stage/level shift stage 12.

Logic stage 10 includes a pair of switching MESFETs Q1 and C2. The drains of the transistors Q1 and C2 are connected to load resistors R1 and R2, respectively, and the load resistors R1 and R2 are further connected to the first power supply terminal 14 via a load resistor R3. Furthermore, the gates of transistors Q1 and C2 are connected to inputs INI and IN2, respectively, and receive input logic signals that are complementary to each other.

Furthermore, the sources of transistors Q1 and C2 are commonly connected and connected to the drain of MESFET Q3. The source of the transistor Q3 is connected to the second power supply terminal 16 via a current setting resistor R4.

This second power supply terminal 16 has a negative relationship with respect to the first power supply terminal 14. Further, the gate of the transistor Q3 is connected to the bias fixed voltage terminal 18 via the bias resistor R5, and the transistor Q3 and the resistors R4 and R5 constitute an active current source.

The drains of the transistors Q1 and C2 are connected to the gates of a pair of MESFETs Q4 and C5 of the output stage/level shift stage 12. Those transistors Q4 and C
The drain of 5 is connected to the first power supply terminal 14. Further, the sources of the transistors Q4 and C5 are level shift elements 20 and 22, respectively, which are constructed by connecting three Schottky barrier diodes (SBD) in series.
is connected to the drains of a pair of MESFETs Q6 and C7. The gates of these transistors Q6 and C7 are connected via capacitors C1 and C2, respectively.
It is connected to the drains of the transistors Q2 and Ql, and further connected to the bias fixed voltage terminal 18 via resistors R6 and R7, respectively. The sources of transistors Q6 and C7 are connected in common and resistor RI
It is connected to the second power supply terminal 16 via O. Furthermore, level shifting elements 20 and 22 and transistor Q6
and C7, respectively, are connected to outputs 0UTI and 0UT2. Transistors Q4 and C5 thus constitute a source follower and transistors Q6 and C7 constitute a current source.

A concrete example of the components of the circuit described above is as follows.

The gate width of MESFETQI to C7 is 20 μm.

GaAsME SFET with Vth=0.3V
.

Level shift elements 20 and 22 are composed of three SBDs connected in series, load resistors R1, R2 and R3 are 5 ohms, bias resistors R4, R6 and R7 are 3 ohms, and current setting resistance R
5 is Ω, capacitors C1 and C2 are about 40 fF, resistor RIO
is 2.5Ω, the voltage VDD of the first power supply terminal is OV1, the voltage VSS of the V2O3 source terminal is -5V, and the fixed potential of the bias fixed voltage terminal 18 for current stabilization is -4,
4V.

The semiconductor inverter circuit described above operates as follows. A high level signal is input to the input INI, and the input IN
A low level signal is input to input INI and I
When signals having mutually inverted phases are input to N2, the transistor Q1 is turned on and the transistor Q2 is turned off. Therefore, the drain of transistor Q1 becomes low level, the gate of transistor Q4 becomes low level, and transistor Q4 is turned off. On the other hand, the drain of transistor Q2 becomes high level,
The gate of transistor Q5 becomes high level, and transistor Q5 is turned on.

Furthermore, one end of the capacitor C2 is connected to the gate of the transistor Q7, and the other end of the capacitor C2 is connected to the drain of the transistor Q1, so it becomes low level, and therefore,
The gate of transistor Q7 is pulled low while capacitor C2 is being charged, so that transistor Q7 is placed in an off state. Therefore, the source potential of the transistor Q5 is shifted by the potential drop of SBD constituting the level shift element 22, and the output is 0UT.
2 is output as a high level signal. On the other hand, the other end of the capacitor C1, whose one end is connected to the gate of the transistor Q6, is connected to the drain of the transistor Q2, so it becomes high level, and the gate of the transistor Q6 becomes high level, and as a result, the transistor Q6 is placed in the on state. Therefore, the output 0UT1
is dropped to a low level via the transistor Q6 and the resistor RIO, and is output as a low level signal from the output 0UTI.

When the signals input to inputs INI and IN2 are reversed from the above operation, the high level in the above operation becomes low level, and the low level becomes high level. Except that
Works similarly.

Transistor Q that constitutes the active current source of the source follower
Since the source terminals of transistors Q6 and Ql are commonly connected, the distribution ratio of the currents flowing through transistors Q6 and Ql can be changed by push-pull operation while keeping the sum of the currents flowing through transistors Q6 and Ql constant. can.

Although the embodiment of the present invention described above is a gate circuit having an inverter function, the scope of application of the present invention is not limited to this. It is obvious that the present invention can be applied to gate circuits, NOR gate circuits, AND gate circuits, NAND gate circuits, latch circuits, and other circuits.

Effects of the invention A circuit with increased driving capacity compared to the conventional 5CFL circuit is
Variations in current consumption and drive capacity due to variations in ET Vth can be suppressed, and manufacturing can be performed with high yield.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor logic circuit according to the present invention, FIG. 2 is a circuit diagram showing a conventional 5CFL circuit, and FIG.・Circuit diagram of a conventional circuit that enables pull operation. FIG. 4 is a circuit diagram showing an example of a conventional 5CFL circuit that suppresses variations in current consumption and drive capacity. [Main reference numbers] 10... Logic stage 12... Output pre-dead level shift stage 14
...First power terminal 16...Second power terminal 18...
Bias fixed voltage terminal 20.22...Level shift element Ql-Ql...MESFET R1~RIO...Resistor 01~C2...Capacitor

Claims (3)

[Claims] (1) A logic stage having a pair of switching FETs, an input, and a pair of outputs capable of taking a pair of complementary output potentials, and a gate connected to each of the pair of outputs of the logic stage. a source follower circuit having a pair of source follower FETs, and a source follower circuit having a pair of source follower FETs;
an active current source having a pair of current source FETs connected to respective source terminals of the ET, the gate of each of the pair of current source FETs being connected to a fixed bias voltage terminal via a resistor; , in a semiconductor logic circuit in which the current source FET is connected to the output of the logic stage to which the gate of the source follower FET is not connected via a capacitor, the source terminals of the current source FETs are connected to each other. A semiconductor logic circuit characterized in that the commonly connected source terminals are connected to a power supply terminal via a resistive element. (2) The switching FET, the source follower FET, and the current source FET are GaAs MESFETs.
The semiconductor logic circuit according to claim 1, characterized in that: (3) The pair of current source FETs are connected to respective source terminals of the pair of source follower FETs via a level shift element.
) or the semiconductor logic circuit according to 2.