JPS63232524A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines by making any of a data signal line, a clock signal line and a strobe signal line common. CONSTITUTION:The data signal line 23 and the clock signal line 25 are made common in a first frequency synthesizer and a second frequency synthesizer 3. A data signal is inputted in shift registers 19a and 19b and when a strobe signal STB1 becomes ON in the first synthesizer 1 the contents of the register 19a is transmitted to a latch circuit 21a and the number of division of a variable divider 17a is altered so as to set the frequency of the first synthesizer 1. In this case, the data signal is also transmitted to the shift register 19b, but the number of division of the variable divider 17b is not altered as far as the strobe signal STB2 does not become ON. Thus, the number of signal lines can be reduced since the data signal line 23 and the clock signal line 25 are made common.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a frequency synthesizer.

(Prior Art) There is a conventional frequency synthesizer (for example, as shown in FIG. 3). This frequency synthesizer has a first frequency synthesizer 1 and a second frequency synthesizer 3 connected in parallel. .

The first frequency synthesizer 1 includes a reference oscillator 59 and a frequency divider 7.
a. Phase comparator (PD) 98. loop filter 11a,
Voltage controlled tlI optical oscillator (VCO) 13a.

It consists of variable frequency dividers 15a and 17a, a shift register 19a, and a latch circuit 21a.

A reference oscillator 5 generates a reference signal. A frequency divider 7aG divides the frequency of the reference signal. The phase comparator 9a compares the phases of the output signal of the frequency divider 7a and the output signal of the variable frequency divider M17a. V
The CO 13a changes the oscillation frequency according to the output signal of the loop filter 11a.

The variable frequency divider 15a divides the frequency of the output signal of the VCO 13a. This frequency division number can be set arbitrarily. The variable frequency divider 17a further divides the output signal of the variable frequency divider 15a, and the frequency division number is set by the data signal sent to the shift register 19a. The shift register 19a inputs a data signal (DATA) in synchronization with a clock signal (CK). The latch circuit 21a is a shift register 19a.
The output signal is temporarily stored in response to the input of the strobe signal (STB) and sent to the variable frequency divider 17a.

The second frequency synthesizer 3 has a configuration similar to that of the first frequency synthesizer 1, and the corresponding elements are denoted by b.
This is a change. Note that the first frequency synthesizer 1 and the second
The frequency synthesizers 3 have M single oscillators 5 in common.

In such a frequency synthesizer, the frequency to be output can be set by inputting a predetermined data signal to the shift registers 19a, 19b and appropriately setting the frequency division numbers of the variable frequency dividers 17a, 17b.

(Problems to be Solved by the Invention) 'However, in such a frequency synthesizer, three types of control lines, a data signal line, a clock signal line, and a strobe signal line, are required for each frequency synthesizer, so the number of signal lines is large. There was a problem with that.

The present invention has been made in view of these problems, and its purpose is to provide a frequency synthesizer with a small number of signal lines.

(Structure of the Invention) (Means for Solving the Problems) In order to achieve the above object, the present invention provides a frequency synthesizer in which a plurality of frequency synthesizers are connected in parallel,
It is characterized in that any one of the data signal, clock signal, and strobe signal is output in common.

(Function) By using one of the data signal line, clock signal line, and strobe signal line in common, the number of signal lines can be reduced.

(Example) Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram of a frequency synthesizer according to a first embodiment of the present invention. In this embodiment, elements that perform the same functions as those in the conventional example shown in FIG. 3 are given the same numbers, and explanations from a Φ perspective are avoided. The feature of this embodiment is that the data signal line 23 and the clock bus line 25 are connected to each other in the first frequency synthesizer 1 and the second frequency synthesizer 113.

In this embodiment, data signals are input to shift registers 19a and 19b in synchronization with a clock signal. Then, in the first frequency synthesizer 1, the strobe signal <
5TB1> is turned on, the contents of the shift register 19a are sent to the latch circuit 21a, the frequency divider of the variable frequency divider 17a is changed, and the frequency of the first frequency synthesizer 1 is set.

In this case, the data signal is also sent to the shift register 19b, but the frequency division number of the variable frequency divider 17b is not changed unless the strobe signal (STB2> is turned on).The frequency of the second frequency synthesizer 3 is set. In this case, when the strobe signal (STB2) is turned on, the frequency division number of the variable frequency divider 17b is changed and the frequency is set.

As described above, in this embodiment, the number of signal lines can be reduced by using the data signal line 23 and the clock signal line 25 in common.

FIG. 2 is a block diagram of a frequency synthesizer according to a second embodiment of the present invention, and the feature of this embodiment is that a clock signal line 25 and a strobe signal line 27 are used in common.

Different data signals (DATA1, DATA2) are sent to the shift registers 19a, 19b, respectively, and these data signals are connected to the shift registers 19a, 19b in synchronization with a clock signal (CK). Strobe signal ST
When B is turned on, the contents of the shift registers 19a, 194) are sent to the latch circuits 21a, 21b, respectively, and the frequency division numbers of the variable frequency dividers 17a, 17b are changed, and the contents of the shift registers 19a, 194) are changed to the first frequency synthesizer 1 and the second frequency synthesizer 3. The frequency is set.

In this embodiment, the clock signal 1125 and the clock signal line 2
7 in common, the number of trust wires can be reduced.

(Effects of the Invention) As described in detail above, according to the present invention, it is possible to provide a frequency synthesizer with fewer signal lines.

[Brief explanation of the drawing]

FIG. 1, FIG. 2, and FIG. 3 are block diagrams of frequency synthesizers according to the first embodiment of Bonmei, the second embodiment of the present invention, and the conventional example, respectively. 1.3...Frequency synthesizer, 5... groups? V oscillator, 7a, 7b--1=frequency divider, 9a, 9b--phase comparator, 11a, 11b--loop filter, 13a. 13 b VCo, 15 a, 15 b-- Frequency divider, 17a, 17b--. Variable frequency divider, 19a, 19b
...shift register, 21a, 21b as latch circuit, 2
3...Data signal @ line, 25...Clock signal line, 2
7... Strobe signal line Figure 1. Figure 2 Figure 3

Claims (1)

[Claims] A reference oscillator that generates a reference signal; a phase comparator that compares the phase of the reference signal and the output signal of the variable frequency divider; a loop filter connected to the phase comparator; a voltage controlled oscillator that changes the oscillation frequency according to the output signal of the filter; a variable frequency divider that divides the output signal of the voltage controlled oscillator and inputs it to the phase comparator; and a data signal that is synchronized with the clock signal. A frequency synthesizer in which a plurality of frequency synthesizers are connected in parallel, each of which includes a shift register for input, a latch circuit that temporarily stores the output of the shift register according to the input of a strobe signal, and outputs this data to the variable frequency divider. A frequency synthesizer according to the present invention, wherein one of the data signal, the clock signal, and the strobe signal uses a common signal line.