JPH09289446A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the precise PLL circuit by using an inexpensive phase comparator. SOLUTION: A delay circuit 10 delays a reference signal 1 by a specific delay time T to generate a delayed reference signal 11, and a delay phase comparator 12 compares the phase of the delayed reference signal 11 with that a frequency-divided signal and outputs the comparison output as delay voltage pulses 13. An adding integration circuit 14 adds and integrates the output of the delay phase comparator 12 and the output of the phase comparator 2. The delay time T is so set that the dead zones of the delay phase comparator 12 and phase comparator 2 do not overlap with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional PLL circuit.

In the figure, 1 is a reference signal supplied from the outside to an input terminal IN, 2 is a phase comparator, 3 is an integrating circuit, 4
Is a voltage controlled oscillator (VCO), 5 is a frequency divider having a frequency division ratio N,
Reference numeral 6 is a frequency-divided signal output from the frequency divider 5, 7 is a voltage pulse signal output from the phase comparator, 8 is an oscillation voltage serving as a control input of the VCO 4, and 9 is an oscillation frequency signal.

Next, the operation of the conventional PLL circuit will be described.

FIG. 5 is a timing diagram showing the output voltage of a conventional phase comparator.

The reference signal 1 from the input terminal IN and the divided signal 6 fed back via the divider 5 are input to the phase comparator 2. The phase comparator 2 compares the two phases, and if the phase of the frequency-divided signal 6 advances from the reference signal 1, as shown in FIG. 5B, a positive voltage pulse signal having a pulse width corresponding to the phase difference. 7 is output and, conversely, if the phase is delayed, (f) in FIG.
As described above, the negative voltage pulse signal 7 having a pulse width corresponding to the phase difference is output.

The integrating circuit 3 integrates the voltage pulse signal 7 and outputs an oscillation control voltage 8. The VCO 4 outputs an oscillation frequency signal 9 which oscillates at an oscillation frequency according to the oscillation control voltage 8. The frequency divider 5 frequency-divides the oscillation frequency signal 9 and outputs the frequency-divided signal 6 to the phase comparator 2.

If the entire feedback system is moved in a stable direction, that is, if the frequency-divided signal 6 lags behind the reference signal 1, the feedback is advanced, and if it is advanced, the feedback is delayed, as shown in FIG. The oscillation frequency signal 9 stabilizes at a position where the voltage pulse signal 7 does not appear. The oscillation frequency signal 9 has a frequency N times as high as that of the reference signal 1 and has a phase matched with that of the reference signal 1, and is output from the output terminal OUT.

[0009]

In the conventional PLL circuit as shown in FIG. 4, the phase at which the positive pulse and the negative pulse of the phase comparator 2 are switched, that is, as shown in (c) and (e) of FIG. The pulse signal 7 is not output when the phase of the divided signal 6 approaches the phase of the reference signal 1, that is, in the dead zone. Therefore, since the reference signal 1 and the frequency-divided signal 6 cannot be compared in phase in such a dead zone, the phases of the oscillation frequency signal 9 and the reference signal 1 cannot be adjusted more precisely.

On the other hand, the phase comparator having a narrow dead zone is expensive, and if the PLL is used to construct the PLL, there is a problem that the cost of the PLL increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly accurate PLL circuit using an inexpensive phase comparator having a wide dead zone. Is.

[0012]

A PLL circuit according to the present invention includes first phase comparison means for comparing the phases of a divided signal and a reference signal and outputting a first voltage pulse according to the phase difference. A second phase comparison means for delaying one of the frequency-divided signal and the first reference signal, comparing the phases of these signals, and outputting a second voltage pulse according to the phase difference; Addition and integration means for adding and integrating the first and second voltage pulses to generate a voltage signal, voltage controlled oscillation means for outputting an oscillation frequency signal according to the voltage signal, and frequency division of the oscillation frequency signal. And a frequency dividing means for generating the frequency divided signal.

The first and second phase comparison means of the PLL circuit according to the present invention generate a positive or negative voltage pulse depending on whether the phase difference is positive or negative. .

The PLL circuit according to the present invention is the first
And the second voltage pulse has a pulse width corresponding to the phase difference.

Further, the second phase comparison means of the PLL circuit according to the present invention has a comparator and a delay means, and the delay means comprises the first phase comparison means and the second phase comparison means. The comparator has a delay time so that the dead zones of the comparators do not overlap each other.

The PLL circuit according to the present invention has a second configuration.
2 or more of the phase comparing means, and the two or more second phase comparing means have different delay times.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described.

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the figure, reference numerals 1 to 9 are the same as the conventional one (FIG. 4). Reference numeral 10 is a delay circuit that forms a delayed reference signal 11 by delaying the reference signal 1 by a predetermined delay time T. Reference numeral 12 compares the phases of the delayed reference signal 11 and the frequency-divided signal 6, and the comparison result shows the delayed voltage pulse 13 Is a delay phase comparator, and 14 is an adding and integrating circuit. Here, the delay phase comparator 12 is the phase comparator 2
It has a dead zone similar to that of both, and both dead zones DZ1 and D
The delay time T is set so that Z2 does not overlap.

Next, the operation of the PLL circuit having the above configuration will be described.

2A to 2F are timing charts showing the outputs of the phase comparator 2 and the delay phase comparator 12 in the PLL circuit of FIG. In the figure (a),
Reference signal 1, delayed reference signal 11 delayed by delay time T,
The dead zones DZ1 and DZ2 of the phase comparators 2 and 12 are shown.

The reference signal 1 and the frequency-divided signal 6 supplied from the outside to the input terminal IN are input to the phase comparator 2. The phase comparator 2 outputs a positive pulse having a pulse width corresponding to the phase difference when the phase of the divided signal 6 advances from the reference signal 1, and outputs a negative pulse having a pulse width corresponding to the phase difference when delayed. 2B and 2F show the voltage pulse signal 7 when the phase of the frequency-divided signal 6 is advanced and delayed.

The reference signal 1 is output from the delay circuit 10 as a delay reference signal 11 having a delay time T, and the delay reference signal 11 and the divided signal 6 are input to the delay phase comparator 12. The delay phase comparator 12 outputs a positive pulse having a pulse width corresponding to the phase difference when the phase of the divided signal 6 advances from the delay reference signal 11, and outputs a negative pulse having a pulse width corresponding to the phase difference when delayed. Similarly, FIGS. 2B and 2F show the delayed voltage pulse signal 13 when the phase of the divided signal 6 is advanced and delayed.

The addition and integration circuit 14 adds the voltage pulse signal 7 and the delayed voltage pulse signal 13 to each other, and then outputs an integrated flat oscillation control voltage 8.
The VCO 4 outputs an oscillation frequency signal 9 that oscillates at an oscillation frequency according to the magnitude of the oscillation control voltage 8. The frequency divider 5 divides the oscillation frequency signal 9 into 1 / N and outputs a divided signal 6. This entire feedback system makes it possible to obtain an oscillation frequency signal 9 having a frequency N times that of the reference signal 1 and in phase with the reference signal 1.

Since the PLL circuit of this embodiment is constructed and operates as described above, the phases of the reference signal 1 and the divided signal 6 are greatly separated as shown in FIGS. 2B and 2F. If so, the oscillation output of the VCO 4 can be controlled in the direction in which the phases are matched, as in the conventional PLL circuit.

As a result, as shown in FIG. 2 (c), when the phase of the divided signal 6 approaches the reference signal 1 and the voltage pulse signal 7 enters the dead zone DZ1 of the phase comparator 2, the voltage The pulse signal 7 is not output, and one input of the adding and integrating circuit 14 is in the high impedance state. However, since the frequency-divided signal 6 is out of the dead zone of the delay phase comparator 12, a positive pulse is output as the delay voltage pulse signal 13. Therefore, since the delayed voltage pulse signal 13 is integrated by the addition integration circuit 14 and input to the VCO 4 as the oscillation control voltage 8, the delayed voltage pulse signal 13 acts in the direction of further delaying the phase of the divided signal 6 (rightward in FIG. 2).

Further, when the phase of the divided signal 6 lags the phase of the reference signal and leads the phase of the delayed reference signal 11, a negative pulse is generated as the voltage pulse signal 7 as shown in (d) of FIG. When a positive pulse is output as the delay voltage pulse signal 13, the oscillation control voltage 8 is kept in balance and a predetermined value is obtained from the reference signal at the point that the value obtained by adding them by the adding and integrating circuit 14 and then integrating them becomes 0. A stable oscillation output can be obtained with the phase difference of, that is, with the intermediate phase between the reference signal 1 and the delayed reference signal 11.

As shown in FIG. 2E, when the phase of the divided signal 6 approaches the delayed reference signal 11, the delayed voltage pulse signal 13 enters the range of the dead zone DZ2 of the delayed phase comparator 12, so that the voltage is reduced. The pulse signal 13 is not output, and the other input of the adding and integrating circuit 14 is in a high impedance state. However, the voltage pulse signal 7 output from the phase comparator 2 is output as a negative pulse because it is outside the dead zone DZ1. Therefore, this voltage pulse signal 7
And the addition control circuit 14 controls the oscillation control voltage 8 to VC
If input to O4, it acts in the direction of advancing the phase of the divided signal 6 (leftward in FIG. 2).

As described above, in the PLL circuit including the delay circuit 10, the two phase comparators 2 and 12, and the adding and integrating circuit 14, what value is the phase difference of the divided signal 6 with respect to the reference signal 1. However, since the pulse output from either of the phase comparators 2 and 12 is output, it is possible to inexpensively configure a highly accurate PLL circuit without a dead zone as a whole.

Embodiment 2 FIG. In the first embodiment, the delay circuit 10 creates the delayed reference signal 11 from the reference signal 1 and uses it as the reference signal of the delay phase comparator 11. However, even if the delay circuit 10 is provided between the frequency divider 5 and the delay phase comparator 11 to delay the frequency-divided signal 6 and compare the phase with the reference signal 1, the same effect as in the first embodiment is obtained. Can be obtained.

Embodiment 3 In the first embodiment, the two phase comparing means of the phase comparator 2 and the delay phase comparator 12 are used, but the delay circuits of two or more different delay times and the dead zone DZ1 of the phase comparator 2 are mutually connected. By providing two or more phase comparators having different dead zones DZN (N is 2, 3, ...), the balance of the oscillation control voltage is maintained at the phase where the addition integral value of the addition integral means becomes zero. .

FIG. 3 is a diagram showing a specific configuration of the adding and integrating circuit 14. Three or more phase comparators 2, 12a, 12
When using b, the resistances R1, R2, R3 are respectively
By connecting to the capacitor C via, it is possible to shorten the time until the phases match. That is, when the phase of the oscillation frequency signal deviates greatly from the phase of the reference signal, positive or simultaneous negative pulses from the phase comparators 2, 12a, 12b are composed of the resistors R1, R2, R3 and the capacitor C. This is because the charging / discharging time in the capacitor C can be shortened because it is output to the adding and integrating circuit 14.

Further, for example, when the delay circuit is used to generate two or more delay reference signals having different delay times, the average value of the phases of the reference signal and all the delay reference signals and the phase of the divided signal. The balance of the oscillation control voltage is maintained in a state where and are matched. By using three or more phase comparators in this way, it becomes possible to match the phases with higher accuracy.

Embodiment 4 Although the delay circuit is used to delay the phase of the second reference signal in the first embodiment, the same effect can be obtained even when the impedance of the delay line or the line is used as the delay means.

In the first embodiment, the adding and integrating means uses the adding and integrating circuit 14 that adds a plurality of voltage pulses and then integrates them. Such an addition and integration circuit 1
4, the circuit configuration is easy in some cases, but in some cases, it may be preferable to first integrate each voltage pulse and then add the voltage pulses, and the present invention is based on the above-described embodiment. It is not limited.

[0036]

Since the PLL circuit of the present invention is constructed as described above, even if it is a phase comparator having a wide dead zone, a plurality of phase comparators can be used to stabilize the phase based on the reference signal. There is an effect that the divided signal of is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an output voltage of the phase comparator in FIG.

FIG. 3 is a diagram showing a specific configuration of an addition and integration circuit 14.

FIG. 4 is a block diagram showing a configuration example of a conventional PLL circuit.

FIG. 5 is a timing diagram showing an output voltage of a conventional phase comparator.

[Explanation of symbols]

1 reference signal, 2 phase comparator, 3 integrating circuit,
4 VCO, 5 frequency divider, 6 frequency division signal, 7 voltage pulse signal, 8 oscillation voltage, 9 oscillation frequency signal, 10 delay circuit, 11 delay reference signal, 12
Delayed phase comparator, 13 Delayed voltage pulse, 14
Adding and integrating circuit.

Claims (5)

[Claims] 1. Comparing the phases of the divided signal and the reference signal,
The first phase comparison means for outputting a first voltage pulse according to the phase difference and either one of the frequency-divided signal and the first reference signal are delayed, and then the phases are compared to obtain the phase difference. Second phase comparing means for outputting a second voltage pulse according to the above, an adding and integrating means for adding and integrating the first and second voltage pulses to generate a voltage signal, and an oscillation according to the voltage signal. A PLL circuit comprising: a voltage controlled oscillating means for outputting a frequency signal; and a frequency dividing means for dividing the oscillation frequency signal to generate the divided signal. 2. The first and second phase comparison means generate positive or negative voltage pulses depending on whether the phase difference is positive or negative, respectively. Item 2. The PLL circuit according to item 1. 3. The PLL circuit according to claim 2, wherein each of the first voltage pulse and the second voltage pulse has a pulse width corresponding to the phase difference. 4. The second phase comparison means has a comparator and a delay means, and the delay means has a dead zone of the comparators of the first phase comparison means and the second phase comparison means. The PLL circuit according to any one of claims 1 to 3, wherein the PLL circuits have delay times so that they do not overlap each other. 5. The method according to claim 1, further comprising two or more second phase comparison means, and the two or more second phase comparison means having delay times different from each other. The PLL circuit described in 1.