JPS63232452A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63232452A JPS63232452A JP62066145A JP6614587A JPS63232452A JP S63232452 A JPS63232452 A JP S63232452A JP 62066145 A JP62066145 A JP 62066145A JP 6614587 A JP6614587 A JP 6614587A JP S63232452 A JPS63232452 A JP S63232452A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- island
- sealing
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 73
- 239000011347 resin Substances 0.000 claims abstract description 73
- 238000007789 sealing Methods 0.000 claims abstract description 29
- 238000000576 coating method Methods 0.000 abstract description 16
- 239000011248 coating agent Substances 0.000 abstract description 15
- 238000000465 moulding Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 21
- 238000000034 method Methods 0.000 description 7
- 206010040844 Skin exfoliation Diseases 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920002050 silicone resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 241001178076 Zaga Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にリードフレームの半導
体チップ搭載面の裏面が露出するように開口部を設けた
樹脂封止型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device in which an opening is provided so that the back surface of a semiconductor chip mounting surface of a lead frame is exposed.
従来、この種の半導体装置は、第７図に一例の断面図を
示すように、半導体チップ１がリードフレーム２の半導
体素子搭載面（以下、アイランドと称す）３にろう材で
固着され、半導体チップ１の電極パッドとリードフレー
ム２のリード４とを金属ワイヤ５で接続していた。リー
ドフレーム２に固着した半導体チップ１は封止金型を用
いて周囲を封止樹脂で封止して成型樹脂７．を形成して
いるが、封止金型の下金型にある突起によってアイラン
ド３の裏面の一部を露出する開口部６．が形成されてい
た。この場合、下金型の突起はアイランド３の裏面に接
するようになっていた。Conventionally, in this type of semiconductor device, as shown in an example cross-sectional view in FIG. The electrode pads of the chip 1 and the leads 4 of the lead frame 2 were connected with metal wires 5. The semiconductor chip 1 fixed to the lead frame 2 is sealed with a sealing resin using a sealing mold, and molded with resin 7. However, an opening 6. which exposes a part of the back surface of the island 3 is formed by a protrusion on the lower mold of the sealing mold. was formed. In this case, the protrusion of the lower mold was in contact with the back surface of the island 3.
上述した従来の半導体装置は、アイランドの裏面に対す
る封止樹脂の廻り込み量が少くないので、樹脂封止時、
封止金型からの離型時、リードフレームの加工、めっき
処理、プリント基板への実装時において熱、水分１機械
的外力、処理薬品などの影響により、第８図に示すよう
に、開口部６３の縁端から発する剥れ８を引起す場合が
あった。又、第９図に示すように、開口部６．の最深部
の面がアイランド３の裏面に接しないなめ封止樹脂が入
込んで薄い膜を形成した場合にも、上記した状況におい
て、内部クラック９を発生するという不具合があった。In the conventional semiconductor device described above, the amount of sealing resin that wraps around the back surface of the island is not small, so when encapsulating with resin,
When releasing the mold from the sealing mold, processing the lead frame, plating it, and mounting it on the printed circuit board, due to the effects of heat, moisture, mechanical external force, processing chemicals, etc., the openings may be damaged as shown in Figure 8. There was a case where peeling 8 occurred from the edge of 63. Further, as shown in FIG. 9, the opening 6. Even when the sealing resin whose deepest surface does not contact the back surface of the island 3 penetrates to form a thin film, there is a problem in that internal cracks 9 occur in the above-described situation.
これらの剥れや内部クラックは、半導体チップを外包す
る成型樹脂の封止性を損うものであり、外部からの水分
の浸入や塵埃等の付着を許し、半導体装置の信頼性を著
しく劣化させるという欠点がある。These peelings and internal cracks impair the sealing properties of the molded resin that encases the semiconductor chip, and allow moisture to enter from the outside and dust to adhere, significantly deteriorating the reliability of semiconductor devices. There is a drawback.
本発明の目的は、成型樹脂の剥れ、内部クラックの発生
を防止して信頼性の高い半導体装置を提供することにあ
る。An object of the present invention is to provide a highly reliable semiconductor device by preventing peeling of molded resin and occurrence of internal cracks.
本発明の半導体装置は、リードフレームの半導体チップ
搭載面の裏面側が露出するように樹脂封止して形成した
開口部を有する半導体装置において、樹脂封止前に少く
とも前記裏面を覆って形成された樹脂膜を有している。The semiconductor device of the present invention is a semiconductor device having an opening formed by resin sealing so that the back side of a semiconductor chip mounting surface of a lead frame is exposed, and the semiconductor device is formed so as to cover at least the back side before resin sealing. It has a resin film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
第１図に示すように、半導体チップ１はリードフレーム
２のアイランド３の表面上にろう材で固着され、半導体
チップ１の電極パッドとリードフレーム２のリード４と
が金属ワイヤ５で電気的接続がとられた後、アイランド
３の裏面にコーティング樹脂を後述する方法で塗布し熱
硬化させて樹脂膜１１を形成する。その後、封止金型に
半導体チップを取付は封止樹脂を注入し硬化させて開口
部６を有する成型樹脂７を形成する０次に、封止した樹
脂の外に出たり−ド４のめっき処理、リード切断及び曲
げの工程を経て半導体装置が作られる。As shown in FIG. 1, the semiconductor chip 1 is fixed on the surface of the island 3 of the lead frame 2 with a brazing material, and the electrode pads of the semiconductor chip 1 and the leads 4 of the lead frame 2 are electrically connected by metal wires 5. After the coating resin is removed, a coating resin is applied to the back surface of the island 3 by a method described later and is thermally cured to form a resin film 11. After that, the semiconductor chip is attached to the sealing mold, and a sealing resin is injected and hardened to form a molding resin 7 having an opening 6.Next, the molding resin 7 that comes out of the sealed resin and the plate 4 A semiconductor device is manufactured through processing, lead cutting, and bending steps.
第２図はコーティング樹脂の塗布工程を説明するための
コーティング装置の断面図である。FIG. 2 is a sectional view of the coating apparatus for explaining the coating resin coating process.
第２図に示すように、金属ワイヤ５のボンデイン゛グ工
程が終了した半導体チップ１を裏返して支持台１３の上
に置き、シリンジ１４からゼラチン状のコーティング樹
脂１５を滴下（ボッティング）し、アイランド３の裏面
に盛上げる０次に、加熱してコーティング樹脂１５を硬
化させ第１図に示す樹脂膜１１を形成する。コーティン
グ樹脂１５としてはゼラチン状のシリコン樹脂が用いら
れる。As shown in FIG. 2, the semiconductor chip 1 after the bonding process of the metal wires 5 is turned over and placed on the support stand 13, and a gelatinous coating resin 15 is dripped (botted) from the syringe 14. Next, the coating resin 15 is heated and hardened to form a resin film 11 shown in FIG. 1. As the coating resin 15, gelatinous silicone resin is used.
第３図は樹脂封止の工程を説明するための封止金型の断
面図である。FIG. 3 is a sectional view of a sealing mold for explaining the resin sealing process.
第３図に示すように、樹脂膜１１をアイランド３の裏面
に形成した半導体チップ１は、リードフレームを下側に
して封止金型の上金型２１と下金型２２との間の所定位
置に挟み込まれる。As shown in FIG. 3, the semiconductor chip 1 with the resin film 11 formed on the back surface of the island 3 is placed between the upper mold 21 and the lower mold 22 of the sealing mold with the lead frame facing downward. Caught in position.
下金型２２のアイランド３に対向する面には突起２３が
設けられていて、突起２３の上面とアイランド３の裏面
の樹脂膜１１との間は所定の間隔になるよう設定される
。A protrusion 23 is provided on the surface of the lower mold 22 facing the island 3, and a predetermined distance is set between the upper surface of the protrusion 23 and the resin film 11 on the back surface of the island 3.
次に、第４図（ａ）〜（Ｃ）は樹脂膜がないときの封止
樹脂の充填状態を工程順に示す第３図のＡ−Ａ’線線断
断面図第５図（ａ）〜（Ｃ）は樹脂膜があるときの封止
樹脂の充填状態を工程順に示す第３図のＡ−Ａ’線線断
断面図ある。Next, FIGS. 4(a) to 4(C) are cross-sectional views taken along the line A-A' in FIG. (C) is a sectional view taken along the line AA' in FIG. 3 showing the filling state of the sealing resin in the process order when there is a resin film.
ここで、第４図及び第５図において、第３図の突起２３
の上面とアイランド３の裏面との間隔は同じに設定しで
あるものとする。Here, in FIGS. 4 and 5, the protrusion 23 in FIG.
It is assumed that the distance between the top surface of the island 3 and the back surface of the island 3 is set to be the same.
第３図のアイランド３に樹脂膜１１のない場合は、第４
図（ａ）に示すように、ゲート部３１を通って封止樹脂
１０の注入が開始され、内部にあった空気はエアーベン
ト部３２から排気される。続いて、第４図（ｂ）、（ｃ
）の順で封止樹脂１０が充填される段階で突起２３の位
置を通過するものは、わずかに粘性抵抗を受け、第４図
（ｂ）に示すように、他の部分よりやや遅れるが、第４
図（Ｃ）に示すように、突起２３とアイランド３との間
にも封止樹脂１０が充填された後、充填が終了する。If the island 3 in FIG. 3 does not have the resin film 11, the fourth
As shown in FIG. 3A, injection of the sealing resin 10 is started through the gate part 31, and the air inside is exhausted from the air vent part 32. Subsequently, Fig. 4(b) and (c
) When the sealing resin 10 is filled in the order shown in FIG. Fourth
As shown in Figure (C), after the sealing resin 10 is also filled between the protrusion 23 and the island 3, the filling is completed.
一方、第３図のアイランド３に樹脂膜１１がある第１の
実施例では、第５図（ａ）に示すように、充填の初期で
は上述した第４図（ａ）の場合と同様であるが、第５図
（ｂ）に示す充填の中間過程では、突起２３の位置付近
でアイランドの裏面の樹脂膜と突起２３により封止樹脂
１０が強い抵抗を受け、充填の流れが妨げられる。この
ため、突起２３の上部の空気は取り残され、第５図（Ｃ
）に示すように、樹脂膜と突起２３の上部との間は封止
樹脂１０が充填されない状態で成型される。On the other hand, in the first embodiment in which the island 3 in FIG. 3 has a resin film 11, as shown in FIG. 5(a), the initial stage of filling is similar to the case in FIG. 4(a) described above. However, in the intermediate process of filling shown in FIG. 5(b), the sealing resin 10 is subjected to strong resistance near the position of the protrusion 23 by the resin film on the back surface of the island and the protrusion 23, and the flow of the filling is obstructed. Therefore, the air above the protrusion 23 is left behind, and as shown in FIG.
), the sealing resin 10 is not filled between the resin film and the upper part of the protrusion 23 during molding.
従って、アイランドに樹脂膜が形成されていれば突起２
３と樹脂膜との間が離れていても、第１図に示すように
、成型樹脂７の開口部６が確保できることになる。Therefore, if a resin film is formed on the island, the protrusion 2
Even if there is a distance between 3 and the resin film, the opening 6 of the molded resin 7 can be secured as shown in FIG.
なお、コーティング樹脂としてはシリコン樹脂でなくエ
ポキシ系、ポリイミド系等の有機材料、あるいは複合材
料等も使用できる。As the coating resin, instead of silicone resin, organic materials such as epoxy or polyimide, or composite materials can also be used.
第６図は本発明の第２の実施例の断面図である。FIG. 6 is a sectional view of a second embodiment of the invention.
第６図に示すように、第２の実施例は上述した第１の実
施例のようにアイランド３の裏面側に樹脂膜を形成する
だけでなく、半導体チップ１の全面を覆って樹脂コーテ
ィングした樹脂膜１２を形成している。As shown in FIG. 6, the second embodiment not only forms a resin film on the back side of the island 3 as in the first embodiment described above, but also covers the entire surface of the semiconductor chip 1 with a resin coating. A resin film 12 is formed.
この場合は、前述した第２図に示す樹脂コーティングを
行う際に、半導体チップ１を裏返して樹脂コーティング
の工程・を追加すればよい。In this case, when performing the resin coating shown in FIG. 2 described above, the semiconductor chip 1 may be turned over and the resin coating step may be added.
第２の実施例では、樹脂膜１２が半導体チップ１の全面
を覆っているため、より完全な成型樹脂７ｂによる樹脂
封止と内部応力の緩和ができる利点がある。In the second embodiment, since the resin film 12 covers the entire surface of the semiconductor chip 1, there is an advantage that more complete resin sealing with the molded resin 7b and relaxation of internal stress can be achieved.
以上説明したように本発明の半導体装置は、アイランド
の裏面に成型樹脂の開口部をもつ半導体装置においてア
イランドの裏面に樹脂膜を形成することにより、樹脂膜
による界面密着と内部応力の吸収が達成できるので成型
樹脂の開口部の剥れや内部クラックを防止できるという
効果がある。As explained above, the semiconductor device of the present invention achieves interfacial adhesion and internal stress absorption by the resin film by forming a resin film on the back surface of the island in a semiconductor device having a molded resin opening on the back surface of the island. This has the effect of preventing peeling of the opening of the molded resin and internal cracks.
又、樹脂膜を形成することにより、樹脂封止時に下金型
の突起の上面と樹脂膜との間を離しても開口部が形成で
きるので、アイランドが変形したり汚染、傷をうけるこ
とを防止できるという効果がある。Furthermore, by forming a resin film, an opening can be formed even if the upper surface of the protrusion of the lower mold is separated from the resin film during resin sealing, so the island is prevented from being deformed, contaminated, or damaged. It has the effect of preventing
第１図は本発明の第１の実施例の断面図、第２図はコー
ティング樹脂の塗布工程を説明するためのコーティング
装置の断面図、第３図は樹脂封止の工程を説明するため
の封止金型の断面図、第４図（ａ）〜（ｃ）は樹脂膜が
ないときの封止樹脂の充填状態を工程順に示す第３図の
Ａ−Ａ’線線断断面図第５図（ａ）〜＜ｃ＞は樹脂膜が
あるときの封止樹脂の充填状態を工程順に示す第３図の
Ａ−Ａ’線線断断面図第６図は本発明の第２の実施例の
゛断面図、第７図は従来の半導体装置の一例の断面図、
第８図及び第９図はそれぞれ第７図の半導体装置の問題
点を説明するための半導体装置の断面図である。
１・・・半導体チップ、２・・・リードフレーム、３・
・・アイランド、４・・・リード、５・・・金属ワイヤ
、６゜６−．６ｂ’・・開口部、７，７．．７ｂ・・・
成型樹脂、８・・・剥れ、９・・・内部クラック、１０
・・・封止樹脂、１１．１２・・・樹脂膜、１３・・・
支持台、１４・・・シリンジ、１５・・・コーティング
樹脂、２１・・・上金型、２２・・・下金型、２３・・
・突起、３１・・・ゲート部、３２・・・エアーベント
部。
へ′坐拶聞旨 ｌ￥臂１肩※升／フ。
第２図
第２図
条Ｊ閃FIG. 1 is a cross-sectional view of the first embodiment of the present invention, FIG. 2 is a cross-sectional view of a coating device for explaining the process of applying coating resin, and FIG. Cross-sectional views of the sealing mold, FIGS. 4(a) to (c) are cross-sectional views taken along the line AA' in FIG. Figures (a) to <c> are cross-sectional views taken along the line AA' in Figure 3, showing the filling state of the sealing resin in the process order when there is a resin film. Figure 6 is a second embodiment of the present invention. 7 is a sectional view of an example of a conventional semiconductor device,
8 and 9 are cross-sectional views of the semiconductor device for explaining the problems of the semiconductor device of FIG. 7, respectively. 1... Semiconductor chip, 2... Lead frame, 3...
...Island, 4...Lead, 5...Metal wire, 6°6-. 6b'... opening, 7, 7. ．． 7b...
Molded resin, 8...Peeling, 9...Internal crack, 10
...Sealing resin, 11.12...Resin film, 13...
Support stand, 14... Syringe, 15... Coating resin, 21... Upper mold, 22... Lower mold, 23...
-Protrusion, 31...Gate part, 32...Air vent part. He' zaga monji l￥ﾂ1 shoulder *sho/fu. Figure 2 Figure 2 Article J Sen
Claims (1)
するように樹脂封止して形成した開口部を有する半導体
装置において、樹脂封止前に少くとも前記裏面を覆って
形成された樹脂膜を有することを特徴とする半導体装置
。In a semiconductor device having an opening formed by resin sealing so that the back side of the semiconductor chip mounting surface of a lead frame is exposed, it is preferable to have a resin film formed to cover at least the back side before resin sealing. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066145A JPS63232452A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066145A JPS63232452A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232452A true JPS63232452A (en) | 1988-09-28 |
Family
ID=13307402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62066145A Pending JPS63232452A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232452A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314842A (en) * | 1988-09-30 | 1994-05-24 | Kabushiki Kaisha Toshiba | Resin-sealed type semiconductor device and method for manufacturing the same |
-
1987
- 1987-03-20 JP JP62066145A patent/JPS63232452A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314842A (en) * | 1988-09-30 | 1994-05-24 | Kabushiki Kaisha Toshiba | Resin-sealed type semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2843464B2 (en) | Solid-state imaging device | |
| US6482675B2 (en) | Substrate strip for use in packaging semiconductor chips and method for making the substrate strip | |
| JPH07321139A (en) | Semiconductor device and manufacture thereof | |
| JPH0831988A (en) | Sealing structure of tape carrier package | |
| JPH05267555A (en) | Semiconductor device and its manufacture, and lead frame used for it and its manufacture | |
| JP3606078B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6372553B1 (en) | Disposable mold runner gate for substrate based electronic packages | |
| JP4591362B2 (en) | Manufacturing method of electronic device | |
| JPS63232452A (en) | Semiconductor device | |
| WO1999049512A1 (en) | Semiconductor device and method of manufacturing the same | |
| JP2002270627A (en) | Semiconductor device manufacturing method | |
| JPH0936155A (en) | Manufacture of semiconductor device | |
| JPS634945B2 (en) | ||
| CN108831839B (en) | Method for removing burrs generated in semiconductor plastic packaging process | |
| JP2000124401A (en) | Semiconductor device | |
| JPH11297750A (en) | Semiconductor device, manufacture thereof, and mounting of the semiconductor device | |
| JPH08288324A (en) | Resin sealed semiconductor device and manufacture thereof | |
| JP4308698B2 (en) | Semiconductor device | |
| JPH01205454A (en) | Lead frame | |
| JPH07161909A (en) | Resin-sealed type semiconductor device | |
| JPH0722559A (en) | Lead frame | |
| JPH1084055A (en) | Semiconductor device and its manufacturing method | |
| JP2000124237A (en) | Board for mounting semiconductor elements, resin-sealed semiconductor device using the same and manufacture of the substrate | |
| JPH04252041A (en) | Manufacture of hybrid integrated circuit | |
| JPH04280459A (en) | Semiconductor device sealed with resin |