JPS63231667A - Microcomputer - Google Patents

Abstract

PURPOSE:To suppress the increase of areas of a bus line and a semiconductor chip due to the extension of the width of the bus line and the increase of the number of ports by providing a control circuit, plural output port circuits, and plural input port circuits and transmitting output values and input values of plural ports in serial. CONSTITUTION:Since set bits outputted from a CPU 31 are converted to serial bits by a control circuit 36 and are transmitted in serial in plural output port circuits 421-42n, the number of signal lines among the control circuit 36 and plural output port circuits 421-42n is reduced. Since bits read by plural input port circuits 431-43m are transmitted in serial in plural input port circuits 431-43m and are converted to parallel bits by the control circuit 36 and are supplied to the CPU 31, the number of signal lines among plural input ports 431-43m and the control circuit 36 is reduced. Thus, the length of a bus line 37 is shortened to suppress the increase of areas of the bus line and the semiconductor chip.

Description

[Detailed Description of the Invention] [Summary] The present invention is a microcomputer, which is provided with a υJti1 circuit, a plurality of output port circuits, and a plurality of input port circuits, and has a υJti1 circuit, a plurality of output port circuits, and a plurality of input port circuits. By serially transmitting the data, it is possible to suppress an increase in the area of the bus line and the semiconductor chip due to an increase in the width of the bus line and the number of ports.

[Industrial application field]

The present invention relates to a microcomputer, and a central processing unit (
The present invention relates to a microcomputer that sets output values of a plurality of output ports and reads input values of a plurality of input ports using a rcPUJ (hereinafter referred to as rcPUJ).

In a single-chip microcomputer, a CPU, various peripheral circuits, and a plurality of ports are provided within a semiconductor chip, and these are connected by a bus line.

It is desired that semiconductor chips for such microcomputers have a small area.

[Conventional technology]

FIG. 5 shows a configuration diagram of an example of a conventional microcomputer. In the figure, in addition to a CPU 11, a semiconductor deep 10 has a ROM 12. RAMI 3. Timer 14. A/D converter 15. Peripheral circuits such as interface circuits 16 to 19 are provided, and these CPU 11 and peripheral circuits (12 to 19) are interconnected by a bus line 20. Further, a plurality of ports 21 for input/output are provided at the periphery of the semiconductor chip 10, and the ports 21 are connected to the interface circuits 16-19.

[Problem that the invention seeks to solve]

In conventional microcomputers, when the CPU 11 sets the output value of the port 21 for outputting data, addresses, etc., and when reading the input value of the port 21 and inputting addresses, data, etc., the CPU 11 uses the bus line 20 and the interface circuit. 16 to 1 was conducted.

Therefore, the number of bits for data, addresses, etc. increases from 16 bits to 32 bits, and the width of the bus line 20 increases.
As the number of bauds increases from several tens to about 100, the area of the bus line 20 increases, causing the problem that the area of the semiconductor chip 10 increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a microcomputer that suppresses an increase in the area of a semiconductor chip even when the width of a bus line and the number of ports increase.

Means for Solving Problem C] The microcomputer of the present invention converts setting bits supplied in parallel from a CPU (31) via a bus line (37) into serial bits and outputs the serial bits. A control circuit (36) that converts the serial bits to parallel bits and supplies them to the CPU (31) from the bus line (37), and a control circuit (36) that is connected to each other and is provided corresponding to each of the plurality of output ports (401 to 40T+). connected, and the control circuit (3
6) Port circuits for multiple outputs (421~42n> that shift the serial bits from 401~40η) to set the output values of the ports for multiple outputs (401~40η); 41T11) are provided correspondingly to each other and are cascade-connected to each other, and shift the input values of the plurality of input ports (411 to 41m) and supply them as serial bits to the control circuit (36). port circuits (43I to 43Tn).

[Effect]

In the present invention, the setting bits output from the CPU (31) are converted into serial bits by the control circuit (36) and transmitted serially through the plurality of output port circuits (421 to 42n), so the control circuit The number of signal lines between (36) and the plurality of output port circuits (421 to 42η) can be reduced. Also, multiple input port circuits (431 to 4
The bits read and taken by the control circuit (36) are serially transmitted through the port circuits (431 to 43T11) for multiple inputs, and converted into parallel bits by the control circuit (36).
1), so multiple input port circuits (43
1 to 43 m) and the control circuit (36). Therefore, the length of the bus line (37) can be shortened.

〔Example〕

FIG. 1 shows a configuration diagram of an embodiment of a microcomputer according to the present invention. In the figure, 30G is a semiconductor depth, and the central part of the semiconductor chip 30 has a CPU 31, a ROM 32, and so on. R
AM33. Timer 34. A/D converter 15. Peripheral circuits such as a port control circuit 36 are provided. These CPU3i and peripheral circuits (32 to 36) are connected to bus line 3.
7 and are interconnected.

Further, ports 401 to 4 are provided at the peripheral edge of the semiconductor chip 30.
0i to 4On and /11+ to 41m are provided. Ports 401 to 401 to 401 are connected to port circuits 421 to 401, respectively.
42i to 42η are connected to the port control circuit 36, and the ports 41+ to 41tn are connected to the port circuits 43I, .
. . , are connected to the port control circuit 36 via 43tn.

The port control circuit 36 has a 474 configuration shown in FIG.

In FIG. 2, a register 50 is connected to the bus line 37 via a terminal 51, and stores port information supplied from the CPU 31. The port information includes a signal that instructs input or output, the value of the end position of the input or output port, the number of ports, and the address.

Setting bits and degrees of data etc.

For example, when setting the output from ports 40n to 40i (directly), the port control circuit 36
The value n indicating 0η is the end position value, and the port control circuit 36
The value 1 indicating the port 40i closest to is the value of the starting position, and the number of ports is expressed as n-i. Further, the same applies when reading input values from ports 411 to 41Tn, for example, and the port 41 which is farthest from the port control circuit 36
The value m indicating m is the value of the end position.

When the port information indicates output, the value of the end position of baud 1~ and the number of ports are set in the counter circuit 53.

At the same time, the setting bits stored in the register 50 are supplied in parallel to the shift register 54 and loaded therein. The shift register 54 shifts the parallel setting bit using the clock <HS supplied from the clock generator 55, and supplies the serial bit SS to the port circuit 421 from the terminal 56.

After setting the end position value, the counter 53 counts the clock signal and generates a position control signal until the count value reaches the number of ports, and supplies it to the position signal generation circuit 57. When this happens, an a-do control signal is generated and supplied to the load signal generation circuit 58.

The position signal generation circuit 57 sets the value of the position signal ST to 717 only while the position control signal is being supplied, and then sets the value of the position signal ST to vOv and outputs the value from the terminal 59 to the port circuit 42.
Supply to 1.

The load signal generation circuit 58 generates a load signal @LD with a value of 717 by supplying the load control signal and outputs it from the terminal 60. Also, the clock signal C from the clock generator 55
LK is output from terminal 61.

When the port information instructs input, a signal instructing input stored in the register 50 is supplied to the save signal generation circuit 65, and the save signal generation circuit 65 operates for a predetermined period *'
A save signal Sv of i' is generated and supplied from the terminal 66 to the port circuits 41+ to 41m.

Thereafter, the end position value is set in the counter circuit 53. The counter circuit 53 counts the clock signal and
When the count value reaches the end position value, an output control signal is generated and supplied to the shift register 63.

The serial bit SS is input to the terminal 62 from the port circuit 431.
is input and supplied to the shift register 63. The shift register 63 shifts serial pins 1 to SB in response to a clock signal supplied from the clock generator 55. The shift register 63 is connected to the bus line 37 via a terminal 64, and when an output control signal is supplied from the counter circuit 53, the shift register 63 outputs the shifted bits from the terminal 64 to the bus line 37 in parallel. .

The port circuits 421 to 42i to 42n are output circuits and are cascade-connected to each other, and have a circuit configuration not shown in FIG. 3. In FIG. 3, a clock signal CLK is commonly input to the terminal 70 from the port control circuit 36, and the D-type flip 7a knob 7
1.72 clock input terminals. terminal 7
3 receives the position signal ST output from the port control circuit 36 or the port circuit at the previous stage and is supplied to the data input terminal of the flip-flop 71.
The position signal 5”3ST output from the terminal is output from the AND circuit 74.
It is also supplied to the next stage port circuit from the terminal 75.

end? The serial bit SB output from the port control circuit 3G or the previous stage port circuit enters -76 and is supplied to the data input terminal of the flip-flop 72, and the serial bit SS output from the Q terminal of the flip-flop 72
is supplied to the data terminal of the D-type flip 70 tube 78, and is also supplied from the terminal 77 to the next stage port circuit.

That is, the flip-flops 71 of each of the port circuits 421-42i-42n constitute a shift register for shifting the position signal ST, and the respective 7-lip flops 72 constitute a shift register for shifting the serial bit SB.

A load signal LD is commonly supplied to the seven terminals from the port control circuit 36 and is supplied to the AND circuit 74. The AND circuit 74 receives a position signal from the Q terminal output of the flip-flop 71.
The load signal LD is supplied to the clock input terminal of the flip-flop 78 only when the value S is 717. The flip-flop 78 to which the load signal LD is supplied takes in the serial bit SB of the Q terminal output of the flip-flop 72.
ν is supplied to the pad 80 from its Q terminal. band 80
correspond to the pads 401 to 40i to 401 shown in the first diagram.

As a result, the serial bit SB and position signal 8 signals [1 signal CLK] are output from the port control circuit 36.
The port circuits 421 to 42i to 42η are sequentially shifted by. For example, when the position signal ST with the value 717 is set in the flip-flops 71 of the port circuits 42i to 42++, the serial bit SS for output is set in the flip-flops 72 of the port circuits 42i to 42n, and the value of the load signal LD is Togi port circuit 42 becomes 717
The serial bit SB for output is set in the flip-flops 78 of ports 401 to 40n.
The output values of are set at the same time.

The port circuits 431 to 43m are input circuits and are cascade-connected to each other, and have the circuit configuration shown in FIG. 3. In FIG. 3, pads 90 correspond to pads 411 to 41T11, respectively. Band 90 is connected through an N-channel field effect transistor (FET) 91 to a data input terminal of a D-type flip-flop 92.

The serial bit SB output from the previous stage port circuit is input to the terminal 93, and this terminal 93 is connected to the P-channel FET 9.
4 to the data input terminal of the flip-flop 92.

The terminal 95 has a common save (3
No. S■ comes in and is supplied to the gates of FETs 91 and 94, respectively. In addition, clock signals CL and K are commonly input from the port control circuit 36 to the terminal 96, and the flip-flop 9
2 clock input terminal. Also, the serial bit SB output from the QE terminal of the flip-flop 92 is connected to the next stage port circuit or port control circuit 36 from the terminal 97.
supplied to

Here, when the value of the save signal SV is 717, the FET91
becomes conductive, FET 94 is cut off, and the input value of pad 90 is taken into flip 70 knob 92 as serial bit SB.

When the value of the save signal S becomes W Q V, FET91
The port circuit 43+ is cut off and the FET 94 becomes conductive.
~43Tn flip-flop 92 is port circuit 431
constitutes a shift register with C as the final stage, and the serial bits SB captured in these are clock signals C1,
The signal is sequentially shifted through the port circuits 43m to 431 by K, and is supplied from the port circuit 431 to the shift register 63 of the port 1 control circuit 36. After this, shift register 63
As described above, the parallel pit is output from the bus line 37 to the bus line 37.

In this way, the port control circuit 36 and the port circuit 42+
~42i~42n and 43+~43m are connected only by a few signal lines that transmit the serial bit 8B, clock signal CLK, etc., so the port control circuit 36 and the port circuits 42+~42n, 43t
Only a few signal lines run between ~43 m, and even if the number of ports increases, the area of the semiconductor chip 30 does not increase. Furthermore, the length of the bus line 37 is shorter than that of the conventional device, and even if the width of the bus line 37 increases, the area of the semiconductor deep 30 does not increase so much, and an increase in the area of the semiconductor chip 30 can be suppressed.

Note that, for example, port circuits 421 and 43 are connected to port 40n.
It is also possible to connect Tn and use the port t-40n as an input/output bidirectional port.

〔Effect of the invention〕

As mentioned above, according to the microphone [1 computer of the present invention], even if the width of the bus line and the number of ports increase, the increase in the area of the bus line and the area of the semiconductor chip can be suppressed, which is extremely useful in practice. It is.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of a microcomputer according to the present invention; Figure 2 is a block diagram of an embodiment of a port control circuit; Figures 3 and 4 are circuit diagrams of each embodiment of a port circuit. FIG. 5 is a configuration diagram of an example of a conventional microcomputer. In the figure, 30 is a semiconductor chip, 31 is a central processing unit V! 1 (CPU), 36 is a port control circuit, 401 to 40n, 41+ to 41m are ports, 42
1 to 42T1.431 to 43m are port circuits, 50 is a register, 53 is a counter circuit, 54.63 is a shift register, 55 is a clock generator, 57 is a position signal generation circuit, 58 is a load signal generation circuit, 65 is In the save signal generation circuit, 71, 72, 78, and 92 are flip-flops, 74 is an AND circuit, and 92.94 is an FET. Agent Patent Attorney Tei Iji Ipponmawari'FIF4's My Two Copies - 12's 1p (Picture Book (Figure Po Y Control Circuit Blog 2 Demon Diagram @ 2 Figure Bo 18 Omitted/) Blind T & Eye Week Figure 3) Circuit rotation diagram

Claims (1)

[Claims] The central processing unit (31) provides a plurality of output ports (4
In a microcomputer that sets output values of ports (0_1 to 40_n) and reads input values of a plurality of input ports (41_1 to 41_m), the central processing unit (31)
The configuration bits supplied in parallel via the bus line (37) are converted into serial bits and outputted, and the incoming serial bits are converted into parallel bits and sent via the bus line (37) to the central processing unit. (31) and a plurality of output ports (40_1 to 40_n), which are connected in cascade to each other, and shift serial bits from the control circuit (36). a plurality of output port circuits (42_1 to 42_n) that set the output values of the plurality of output ports (40_1 to 40_n), and a plurality of input ports (41_1 to 41_m), respectively. A plurality of input port circuits (43_1 to 43_m) are provided and cascade-connected to each other, and shift the input values of the plurality of input ports (41_1 to 41_m) and supply them as serial bits to the control circuit (36). 43_m).