JP2590410B2 - Count data output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a circuit for outputting the value of a counting circuit incorporated in a digital circuit to the outside, and an output circuit in which a large number of bits simultaneously invert the polarity when carrying the counting circuit. A counter circuit, a polarity circuit for inverting the polarity of a bit string of an output of the counter circuit every other bit, and a circuit for preventing the sudden load force fluctuation from adversely affecting other circuits. And an output circuit for outputting the output of the polarity conversion circuit to the outside.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of outputting a value of a counting circuit incorporated in, for example, an LSI or the like. The present invention relates to a circuit configuration that does not cause any problem.

[Prior Art] In a multi-bit binary counting circuit (hereinafter, the following counting circuit is also referred to as counting), when the lower bits of the value are continuous “1”, the next counting up is performed. The carry is generated in the upper bits, and the polarity of the lower bits is inverted at the same time.

For example, in an 8-bit counter, the binary number “011111
When the value of "11" is reached, the value is "1000000" in the next step.
That is, in this case, the polarity of all 8 bits is inverted, and the polarity of the lower 7 bits is simultaneously changed in the same direction.

When outputting the value of such a counter to the outside, the output circuit drives a power amplifier called a driver provided for each bit and transmits the output.

[Problems to be Solved by the Invention] The fact that the polarities of most bits of the counter value simultaneously change in the same direction as described above itself is a particular problem for the counter or its peripheral circuits with low power consumption. It will not happen.

However, such an operation is not preferable when the value of the counter is output to the outside through a driver for each bit.

That is, the output circuit is a group of power amplifiers for each bit for outputting a signal to the outside and handles a large power that cannot be compared with a normal logic circuit. Alternatively, when "0" changes to "1", a considerable amount of current flows into or cuts off the circuit.

Therefore, when a change in the polarity of bits in the same direction occurs at the same time in a counter having a large bit width, a change in the current of each driver is added, and a sudden inflow or disconnection of a large current occurs.

This is unfavorable for a logic circuit that handles very fine pulse signals.

This is because, when a large current changes rapidly, a transient phenomenon causes pulse noise in the power supply circuit and fluctuations in the power supply voltage.

This can cause a malfunction of the related logic circuit.

The present invention has been made in view of such a conventional problem, and when a value of a counter having a large bit width is output to the outside through a driver, even when most bits of the counter simultaneously change the polarity in the same direction. It is another object of the present invention to provide an output circuit system which does not cause a large change in current of a power supply to an output circuit.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims.

That is, the present invention includes a counting circuit, a polarity conversion circuit for inverting the polarity of a bit string of the output of the counting circuit every other bit, and an output circuit for outputting the output of the polarity conversion circuit to the outside. This is a count data output circuit.

[Operation] FIG. 1 is a diagram showing the principle of the present invention, wherein 1 is a counting circuit, 2 is a polarity conversion circuit, and 3 is an output circuit.

In FIG. 1, the polarity conversion circuit 2 inverts the bit string of the count output of the counting circuit 1 every other bit and outputs the inverted bit string.
For example, “7F” as a hexadecimal number is “01111111” in a binary number, but this is inverted every other bit to obtain “00101010”.
Output as “or“ 11010101 ”.

The hexadecimal number “7F” is converted into a hexadecimal number “80” when stepped by a counting circuit, which is “10000000” in binary, all bits of the preceding “7F” are inverted, and the lower 7 bits are simultaneously the same. Direction, but on the output side of the polarity inversion circuit 2,
It becomes “11010101” or “00101010”.

When these are tabulated, it becomes as shown in Table 1, and it can be seen that only the upper two bits change in the same direction at the same time and the others are offset.

Note that the inverted pattern 1 in Table 1 refers to a case where the polarity is inverted every other bit, such as non-inverted → inverted → non-inverted from the upper bit, and the inverted pattern 2 is inverted from the upper bit similarly. The case where the polarity is inverted every other bit, such as → non-inversion → inversion...

In the present invention, as described in the above example, no matter how the value of the counting circuit 1 changes, conversion is performed by the conversion circuit so that the polarity of a large number of bits in the same direction does not change at the same time. , No large current change in the output circuit 3 occurs.

FIG. 2 is a block diagram of an embodiment of the present invention.
Reference numerals 4 and 5 denote LSIs, 6 denotes a counting circuit, 7
Denotes a polarity conversion circuit, 8 denotes an output circuit, 9 denotes an input circuit, 10 denotes a polarity conversion circuit, and 11 denotes an internal circuit.

In the figure, the output of the counting circuit 6 of the LSI 4 is inverted every other bit by the polarity conversion circuit 7 and is output from the output circuit 8 to the outside.

When the input circuit 9 of the LSI 5 receives this, the polarity circuit 10 inverts it again every other bit, restores the original data, and inputs it to the internal circuit 11.

In this embodiment, the case where the polarity conversion circuit and the input / output circuit are provided separately is described. However, the output circuit itself or the input circuit itself can be configured as the polarity conversion circuit.

FIG. 3 is a diagram showing an example of an input / output circuit in such a case, where 12 is an LSI count data output circuit,
Is a transmission line, 14 is a data input circuit of another LSI, 15 is a driver, 16 is a driver for inverting the signal polarity and sending out, 17 is a receiver, and 18 is a receiver for inverting the signal polarity and receiving. I have.

In the figure, the count data of the LSI is inverted every other bit by the output circuit 12 and received by the input circuit 14 via the transmission line 13. At this time, the count data is inverted again every other bit so that the original count data is obtained. Restored to data.

If the original data is not necessarily required on the input side (for example, when used as a local memory address), the data receiving side can use the data as it is without inverting the bits. It is possible.

[Effects of the Invention] As described above, according to the present invention, when a value of a binary counter circuit (counter) having a large bit width is output to the outside, most of the bits are simultaneously transmitted due to a carry of an upper bit. Even when the polarity is changed in the same direction, a sudden change in large current does not occur in the output circuit. It is possible to prevent malfunction of the circuit, and there is an advantage that stable operation of the circuit can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a diagram showing an example of an input / output circuit. 1, 6, a counting circuit, 2, a polarity conversion circuit, 3, an output circuit, 4, 5, LSI, 7, 10, a polarity conversion circuit, 8, 1
2 ... output circuit, 9, 14 ... input circuit, 11 ... internal circuit, 13 ... transmission line, 15 ... driver, 16 ... driver for inverting and transmitting signal polarity, 17 ... receiver, 18 ……
Receiver that inverts signal polarity and receives

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-243426 (JP, A) JP-A-63-187818 (JP, A)

Claims (1)

(57) [Claims] A counting circuit (1), a polarity conversion circuit (2) for inverting the polarity of a bit string output from the counting circuit every other bit, and an output of the polarity conversion circuit for each bit. A count data output circuit, comprising: an output circuit (3) for outputting to the outside in parallel every time.