JPS6028968Y2 - Output direct selection type interface circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an output direct selection type interface circuit with a simplified circuit configuration.

An information processing system with a parallel wiring type common bus line with a tri-state output format is roughly configured as shown in Figure 1, and includes a parallel wiring type common bus line BUS, an MPU (microprocessor unit) 1, a main memory 2, and a floppy disk. 3. A bidirectional gate (driver receiver) D/R is required between the controller 4 and the like.

In other words, since the bus line BUS is tri-state, its level is 1" (for example +5v), "O" (OV)
In addition to the two states, there is a third state in which the DC potential is unstable (
None of the gates are selected and both ends of the bus line are in a high impedance state).

On the other hand, since the input/output level of the MPUI, memory 2, etc. is always at the 2[TL (transistor logic) level] of 1 or "0", conversion between the TTL level and the tri-state level is required.

The bidirectional gate D/R is a part of the interface circuit used for this conversion. For example, in the case of the control unit 4 that controls the display 5, a solid line arrow is sent to the input register 6 addressed from the MPU 1 through the D/R. Data is written as shown by , and data is output from the output register 7 as shown by a broken line arrow.

Incidentally, since a plurality of registers of this kind are usually provided, for example, in the case of the output register 7, an interface system including a signal source switching function is required as shown in FIG.

Figure a shows an example where the signal A1 of the first output register and the signal A1 of the second output register are selected and output.The TTL level signal AI-A2 is first sent to the multiplexer MPX, and one of them is output. selected, then its selected output A
is converted to tristate level A' by tristate buffer BUF (which constitutes one gate of bidirectional gate D/R).

The figure equivalently represents the functions of multiplexer MPX and buffer BUF. The state where switch SW is connected to terminal 1 or 2 is due to the selection function of multiplexer MPX, and the state where switch SW is connected to terminal 3. This is due to the conversion function of buffer BIJF.

However, in the above-mentioned interface system, the selection signals S□, which are different between the multiplexer MPX and the buffer BUF,
Since it is necessary to use S2 (the former is for switching the signals Al and A2, and the latter is for selecting whether to make them half-level), the peripheral circuit becomes complicated, and the number of ICs increases due to the use of the multiplexer MPX. It has many disadvantages.

This will be explained with reference to FIGS. 3 and 4.

FIG. 3 shows parallel outputs of 4 bits A□ to D1. A2~D2
Two output registers REG1 . This is an example of the interface circuit □F for REG2, which is composed of one 4-channel multiplexer chip MPX□ and 273 tri-state buffer chips 8.

The 4-channel multiplexer chip has two registers REG□, REG2 outputs A□-D1. The only function is to select one of A2 to D2 using the signal S1□ (the multiplexer is usually made as a 4-channel 2-circuit type).

), an additional 4-bit output register R is added as shown in Figure 4.
When EG3 is added, another 4-channel multiplexer MPX2 is required to switch between the outputs A to D of the multiplexer MPX□ and the output of the register REG3 using the signal S1□.

On the other hand, the tri-state buffer chip 8 has 6 chips per chip.
Since it has three tri-state buffers BUF,
In the case of FIG. 4, it is sufficient to use 2n tri-state buffer chips 8 as in FIG. 3.

In the end, the interface circuit IF in Fig. 3 is 1 as a whole.
It is composed of 273 chips (the fraction is rounded up, so it ends up being 2 chips), and two types of signals S11. Requires S2.

In addition, the interface circuit IF in Fig. 4 has a total of 22
It is composed of 13 (3 chips) and requires three types of signals S1□S1□ and S2.

Although not shown, if there are four 4-bit output registers, three 4-channel multiplexer chips and 2n tri-state buffer chips are required (3 chips in total), and if there are 5 registers, In some cases, 4 multiplexer chips and 273 tri-state buffer chips (4213 chips total) are required.

The present invention attempts to simplify the configuration of such an interface circuit, and includes a parallel wiring type common bus line (BUS) with a tri-state output format, a plurality of registers with outputs at TTL level, and a plurality of registers. A tri-state buffer (BUF) is provided between the bus line and the bus line for each signal.
) and a selection signal (S21, 522) connected to these tri-state buffers to specify each register.
The present invention is characterized in that the tri-state buffer is selectively connected to the bus line by a signal specifying each register. will be explained in detail.

Figure 5 shows the basic configuration of the present invention, in which TTL level signals A□ and A2 from different registers are directly transferred to the tri-state buffer BU without switching using a multiplexer.
Signal A' at tri-state level at F 1. The difference from FIG. 2 is that it is converted to A'2.

In other words, the TTL level signal A1. A2 respectively different signals S21. The tri-state level signal AI is individually controlled by the tri-state buffer BUF controlled by S2□.
Once converted to 'A2', the output end of the buffer BUF can be directly connected to the corresponding line of the common bus line BUS in a wire-or-or manner, so that the function of a multiplexer can be replaced by such a group of tri-state buffers.

This eliminates the need for multiplexers, so even if the number of tri-state buffers increases, the overall number of chips is reduced, and the number of control signals is also reduced.

FIG. 6 is a diagram showing an embodiment of the present invention, in which two output registers REG1. This is aimed at REG2.

If the output registers REG1 and REG2 are both 4 bits, the interface circuit W of the present invention has four tri-state buffers BUF controlled by the signal S21 and the signal S
4 tri-state buffers BUF controlled by 22
Consists of.

And one tri-state buffer chip 8 has 6
buffers BtJF are included, so there are 11 buffers in total.
An ink face circuit IF is composed of 73 chips 8.

Compared to the conventional example shown in Figure 3, the number of chips is reduced. 11 1-5-1-g = voice is decreasing.

FIG. 7 is a diagram showing another embodiment of the present invention, which targets three output registers REG□ to REG3 similarly to FIG. 4.

Since each register has a 4-bit output, there is a total of 12-bit parallel output, but if two tri-state buffer chips 8 are used, all signals can be controlled individually, so an interface circuit equivalent to that shown in Fig. 4 can be created. can be configured with two chips.

Therefore, in this case, the number of chips is smaller than in Figure 4. 2Z z=2. Individual Can be reduced (actually reduced by one by rounding up).

In the example of FIG. 7, a buffer BUF3 for converting the tri-state level to the TTL level is provided in order to write data to the registers REG to REG3, but as shown in FIG. Generator C
When a bidirectional gate D/R is provided for G, there is no particular need to provide a reverse buffer BUF3.

Further, FIG. 7 shows the buffer BUF1. Each parallel output of BUF2 is led independently to the common bus line BUS, but the corresponding ones are connected in advance in the interface circuit IF by wired OR, and in this example, they are connected by four wires. It may also be connected to a common bus line.

FIG. 8 also shows this in a simplified manner.

Furthermore, although not shown in the figure, when there are four registers (one strength), 22 buffer chips are required, but the number of chips is 32 - 22 = 1 less than when using a multiplexer, and the number of registers is In the case of 5 pieces (2 forces), the number of chips can be reduced by 2 1 1 4a 3a=la.

In this way, as the number of output signals increases, the effect of reducing the number of chips becomes more noticeable.

Further, since the selection signal is only related to the buffer, the peripheral circuit configuration is simplified compared to the conventional interface system including the multiplexer selection signal.

As described above, the present invention has the advantage that the configuration of the interface circuit can be simplified, and in particular, the number of IC chips used can be reduced.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a system using a parallel wiring type common bus, Figures 2a and b are basic configuration diagrams and equivalent circuit diagrams of conventional interface circuits, and Figures 3 and 4 are diagrams of conventional interface circuits. FIG. 5 is a basic configuration diagram of an interface circuit of the present invention, and FIGS. 6 to 8 are configuration diagrams showing different embodiments of the present invention. In the figure, BUS is a parallel wiring common bus line, REG□~RE
G3 is an output register, BUF is a tri-state buffer, and W is an interface circuit.

Claims (1)

[Scope of utility model registration request] Parallel wiring common bus line with tri-state output format (B
(us), a plurality of registers whose outputs are at TrL level, a tri-state buffer (BUF) provided between the plural registers and the bus line for each signal, and a tri-state buffer (BUF) connected to these tri-state buffers and each Selection signal S21 for specifying a register. An output direct selection type ink face circuit comprising a signal line to which S2□ is supplied, and a tri-state buffer is selectively connected to a bus line by a signal specifying each register.