JPH01126756A - Bus interface circuit - Google Patents

Abstract

PURPOSE:To improve the flexibility of system design by connecting buses without providing a separate swap buffer at the time of the mutual connection of the buses which have the different bus widths of an n-bit and a 2n-bit. CONSTITUTION:In the case of the external bus of the bus width n-bit, the said external bus is connected to a couple of an input terminal group 2 or 3 and the turning-on of a said first or second disconnecting means is continued. As the result, the internal bus of the n-bit is connected to the external bus of the n-bit. In the case of the external bus of the bus width 2n-bit, said external bus is divided into the n-bit and respectively connected to two couples of input and output terminal groups. The turning-on and off of the first and second disconnecting means is alternatively repeated and as the result, the respective external buses, which are divided into the n-bit, and the internal bus of the n-bit are alternatively connected.

Description

[Detailed Description of the Invention] [Summary] Regarding the bus interface circuit, it is possible to connect two types of buses having different bus widths of n bits (for example, n = 8) and 2n bits without providing a separate swamp buffer or the like. The purpose is to provide a bus interface circuit that is capable of providing an internal bus with n wires, two sets of input/output terminals each having n terminals, and one set of input/output terminals and the internal bus. a first connecting/disconnecting means interposed between the input/output terminal group and the internal bus and connecting/disconnecting the input/output terminal group and the internal bus according to a predetermined control signal; and a second connecting/disconnecting means for connecting/disconnecting the input/output terminal group and the internal bus according to a predetermined control signal; Outputs a control signal that turns on and off the disconnecting means of the connected set, or when an external bus is connected to only one set of input/output terminals, outputs a control signal that turns on and off the disconnecting means of the connected set. and a control means that outputs a control signal to prompt the user.

[Industrial application field]

TECHNICAL FIELD The present invention relates to bus interface circuits, and in particular to n
The present invention relates to a bus interface circuit applied to, for example, a DMA controller, which can connect buses having two different bus widths, ie, 2 bits and 2n bits, without separately providing a swap buffer or the like.

In systems centered on microcomputers, information is transmitted via a common data bus. by the way,
When the word lengths handled by microcomputers and peripheral circuits differ, for example, when a microcomputer with a word length of 8 bits and a peripheral circuit with a word length of 16 bits are connected to a common data bus, the number of lines of the common data bus is While supporting this 16-bit data bus, bus width conversion from 16 bits to 8 bits is required between the common data bus and the microcomputer.

[Conventional technology]

Conventional bus width conversion methods include, for example, dividing a 16-bit data bus into two groups of 8 bits each, upper and lower, and connecting the lower group to a microcomputer, while connecting the upper group and the microcomputer to 8-bit groups.
Connect through a bit swap buffer. and,
When the swap buffer is turned on, the upper 8-bit data in the upper group is loaded into the microcomputer, and when the swap buffer is turned off, the lower 8-bit data in the lower group is loaded into the microcomputer. There is a method of converting the bus width from 16 bits to 8 bits.

[Problem that the invention seeks to solve]

However, in such conventional methods, it is necessary to separately install a swap buffer between the external bus and the microcomputer, and furthermore, it is necessary to provide a control signal to control the opening/closing timing of this swap buffer. There was a problem in that it made the system construction complicated.

The present invention was made in view of these problems, and
To provide a bus interface circuit capable of connecting two types of buses having different bus widths of n bits (for example, n=8) and 2n bits without separately providing a swap buffer or the like. The purpose is to

[Means for solving problems]

In order to achieve the above object, the present invention has an internal bus with one wire, two sets of input/output terminals each having n terminals, and one set of input/output terminals and the internal bus. intervening between
a first connecting/disconnecting means for connecting/disconnecting the input/output terminal group and the internal bus according to a predetermined control signal; a second connecting/disconnecting means for connecting/disconnecting the input/output terminal group and the internal bus, and when an external bus is connected to the two sets of input/output terminal groups;
Outputs a control signal that turns the first and second disconnection means on and off alternately, or disconnects and disconnects the connected pair when an external bus is connected to only one set of input/output terminals. The control means outputs a control signal for prompting the means to turn on.

[For production]

In the present invention, in the case of an external bus having a bus width of n bits, the external bus is connected to one set of input terminals, and the corresponding first or second disconnecting means is kept on,
As a result, the n-bit internal bus is connected to the n-bit external bus.

Further, in the case of an external bus having a bus width of 2n bits, the external bus is divided into n bits each, and each is connected to two sets of input/output terminal groups. Then, the first and second disconnection stages are alternately turned on and off, and as a result, each of the external buses divided into n bits and the n-bit internal bus are alternately connected.

Therefore, the bus width of the external bus is n bits or 2n bits.
In either case, the connection can be made without separately providing a swamp buffer or the like.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing one embodiment of a bus interface circuit according to the present invention.

First, the configuration will be explained. In Figure 1, ■ is, for example,
An integrated circuit such as a microcomputer, 2.3 is two sets of input/output terminals each having n terminals (n-8 in this embodiment), and 4 is an address terminal group having m terminals. D7
~D0 and DI5~D. is an external data bus in which 2n bits are divided into two parts of n bits each, of which the lower 8 bits external data bus D, ~D0 are connected to the above input/output terminal group 2, and the upper 8 bits external data bus DIS~Do is an input bus. Connected to output terminal group 3. Furthermore, A□ to A0 are m-bit external address buses, and this external address bus A11''Ao is connected to the internal address bus inAm-A of the integrated circuit 1 via the address terminal group 4.

connected to.

inD7 to Do and inD+s to De are internal data buses each having n lines, and the lower 8-bit internal data buses 1nDt to D0 are connected to the input/output terminal group 3 via the first buffer BFI. At the same time, the upper 8-bit internal data bus in
Connected to D+s to Da. Also, inD+s~D
I+ is also connected to the input/output terminal group 2 via the third buffer BF. A lower access strobe signal τ■1 from a buffer control logic CNT, which will be described later, is input to the first buffer BF, and the second buffer BF
The upper access strobe signal 100X3 is input to Z and the third buffer BF. These B F
r~BF, are LAS and H as input control signals.
When A100 is active at the [L] level, its internal resistance is minimized and it is turned on.

FIG. 2 is a circuit diagram of buffers BF to BF3.

In the figure, 5.5' is a set of 3-state buffers connected in a loop.
The number of pairs of ' is this buffer BF.

~B F The number of lines is equal to the number of data buses connected to 3. For example, if the number of data buses is n, then n sets are provided. πAS (LAS in the case of BFI) is applied to the 3-state buffer 5.5', and RAS=CL
) level, the three-state buffer 5.5' minimizes its internal resistance and turns on, bidirectionally transmitting data on the connected data bus.

FIG. 3 is a circuit diagram of the buffer control logic CNT.

The buffer control logic CNT has a switch 6, a register 7, NAND8, NAND9, and NANDIO, and the switch 6 connects the ground potential (corresponding to the [L] level) when the bus width of the external data bus supports n=8 bits. choose,
When 2n=16 bits are supported, the power supply Vcc (corresponding to the (H) level) is selected to generate the selection signal SW. It goes without saying that instead of the switch 6, a signal from a microcomputer or other control device may be used as the direct selection signal SW.

The register 7 takes in the status of the selection signal SW applied to the D terminal at the rising edge of the reset signal R and ST from the control section (not shown) and inputs the word signal WORD from the Q terminal.
At the same time, the status of the word signal WORD is held until the next rising edge of the reset signal R3T. For NAND8, the chip select signal C8 from a control unit (not shown) or from the outside is at the (L3 level), and the word signal WORD is at the [H] level (i.e., 16
bit correspondence), the A of the address signal. The bit is (H
) level, the upper access strobe signal HAS
Set active and output.

For NAND9 and 10, the chip select signal C8 is [L]
] level and the word signal WORD is at the (L) level (that is, corresponds to 8 bits), or when the chip select signal C8 is at the (L) level and the A0 bit of the address signal is at the [L] level. At this time, the lower access strobe signal LA100 is set active and output. That is, the buffer control logic CNT outputs the address signal A when the switch 6 selects 16-bit support and the chip select signal T is active. The upper access strobe signal RAS and the lower access strobe signal τ■
1 is alternately set to active, and when 8-bit support is selected and 1 is active in the chip select signal, only the lower access strobe signal LAS is always set to active.

Next, while referring to the timing chart in Figure 4,
The operation of the circuit shown in Figures 3 to 3 will be explained.

First, at time t0, the reset signal R3T becomes [L]
When the selection signal S rises to [H] level from
The status of W (CL level in this case) is in register 7.
The word signal WORD is sent to the (L) level.

Next, when the chip select signal 1 enters the active period, the lower access strobe signal LA100 is set to the (L) level, and this lower access strobe signal LA
All three-state buffers 5.5' to 5n, 5'n of the first buffer BFI to which S is added are turned on.

As a result, lower 8-bit external data buses D7-D0 and lower 8-bit internal data buses 1nD7-D.

are connected with low resistance, and output data from the integrated circuit 1 or input data from the outside is exchanged bidirectionally via the first buffer BF. That is, by setting the selection signal SW to the (L) level, raising the reset signal R3T, and further activating the chip select signal T, the lower 8-bit internal data bus 1nD7 to D0 of the 8-bit bus width is set. It can be connected to lower 8-bit external data buses D7 to D0 having the same bus width. In addition,
During this period, the word signal WORD is fixed at the [L] level, so the upper access strobe HAS maintains an inactive state, and the second and third buffers BF2, B
F3 is off and maintains high resistance. Therefore, even if the high-order 8-bit external data buses DI5 to D8 are connected to the input/output terminal group 2, they are not involved in the internal operation of the integrated circuit 1 at all.

On the other hand, time 1. The reset signal R3T changes from [L] to (H
) level, and if the status of the selection signal SW at this time is the (H) level, that is, if it supports 16 bits, the word signal WORD is set to the (H) level.Then, the address signal Ao is set to the (H) level. If it is at the [H] level, the upper access strobe signal RAS is set to active, thereby causing the second and third buffers B
FZ and BF3 are turned on, and the upper 8 bits external data bus D
IS~D8 and upper 8-bit internal data bus inD, 5~
D8 and lower 8-bit internal data bus inD~Do
are connected with low resistance. Therefore, the data on the upper 8-bit external data bus I)+s to DIl is fetched from the upper 8-bit internal data bus inD+s to DI+ to the lower 8-bit internal data bus 1nDy to D0, or
The data on the lower 8-bit internal data buses 1nD7-Do are output to the upper 8-bit external data buses DI5-Dll through the upper 8-bit internal data buses inD+s-D8. Note that during this period, the word signal WORD is [H].
Since the level is fixed, lower access strobe signal L
The AS remains inactive and the first buffer BF
, are turned off, and the lower 8-bit external data buses D, -D0 and the lower 8-bit internal data buses 1nD7-D0 are disconnected.

When the word signal WORD remains fixed at the (H) level and the address signal Ao changes to the [L] level, the upper access strobe signal HAS changes to the inactive state, while the lower access strobe signal τA1 becomes the active state. and the second and third buffers B F2
, BF3 is turned off, and the first buffer BF is turned on.

Therefore, the data on the lower 8-bit external data buses D7-Do are transferred to the lower 8-bit internal data buses 1nD7-Do.
be taken in.

That is, by setting the selection signal SW to the (H) level,
When the reset signal R3T is raised and the chip select signal C8 is made active, the address signal A at that time. The upper 8-bit external data bus DIS~D8 and the lower 8-bit external data bus D, ~
The data on D0 is alternately transferred to the lower 8 bits of internal data bus i.
nD, ~D0, and in this case, the upper 8-bit external data bus DIS~Dll with a 16-bit bus width and the lower 8-bit external data bus D7~Do are transferred to the lower 8-bit internal data bus 1nI)+~D with an 8-bit bus width. .

Bus width conversion will be performed.

In this way, in this embodiment, two sets of input/output terminal groups 2.3 corresponding to a total of 16 bits are provided in the integrated circuit l, and these input/output terminal groups 2.3 and the upper 8-bit internal data bus inD+
s~D8 and lower 8-bit internal data bus 1nD7~
D0 and the first buffer BF.

and a third buffer BF, and further,
Upper 8-bit internal data bus inD+s to D8 and lower 8
Bit internal data buses 1n07 to Do are connected via a second buffer BF, and these BFs are
Buffer control logic CN controls on/off of I~BF3
It is controlled by T.

Therefore, by turning on only BF, the lower 8-bit external data buses D, ~Do and the lower 8-bit internal data buses 1nD7-D0 can be connected, and in this case, the 8-bit bus width is supported, or the first Buffer BF,
By alternately turning on and off the second and third buffers BF2 and BF3, the upper 8-bit external data buses DIS to DB and the lower 8-bit external data buses D,
~D.

The lower 8-bit internal data buses inD, ~D0 are alternately
In this case, it supports a 16-bit bus width. As a result, the integrated circuit 1 can be connected to both 8-bit and 16-bit bus widths without the need for a separate converter circuit such as a swap buffer, which eases restrictions on bus width and improves system design. Flexibility can be improved.

In this embodiment, n=8 bits, but n=16 bits or n=4 bits. In short, it can be applied to all two types of bus widths that have a 1:2 relationship.

〔Effect of the invention〕

According to the present invention, when connecting two types of buses having bus widths of n bits and 2n bits, it is possible to connect these buses without separately providing a swap bus or the like.

Therefore, when constructing a system using various integrated circuits that share a bus, restrictions on the bus width are relaxed, and flexibility in system design can be improved.

[Brief explanation of the drawing]

1 to 4 are diagrams showing an embodiment of the bus interface circuit according to the present invention. FIG. 1 is a configuration diagram thereof, FIG. 2 is a circuit diagram of its buffer, and FIG. 3 is a diagram of its buffer control logic. The circuit diagram and FIG. 4 are timing charts for explaining the operation of FIG. 1. 2.3... Input/output terminal group, inD, ~D0... Lower 8-bit internal data bus (internal bus),

Claims (1)

[Scope of Claims] An internal bus with n wires, two sets of input/output terminal groups each having n terminals, and a predetermined bus interposed between one set of input/output terminal groups and the internal bus. a first connecting/disconnecting means for connecting/disconnecting the input/output terminal group and the internal bus according to a control signal; A second connecting/disconnecting means connects/disconnects the input/output terminal group and the internal bus, and when an external bus is connected to the two input/output terminal groups, the first and second
Outputs a control signal that turns on and off the disconnecting means of the connected set, or when an external bus is connected to only one set of input/output terminals, outputs a control signal that turns on and off the disconnecting means of the connected set. A bus interface circuit comprising: a control means for outputting a control signal for prompting; and a bus interface circuit.