JPH10334032A - Computer system, and peripheral device used for the system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a peripheral component inter-connection(PCI) device capable of flexibly deal with the change of configuration address. SOLUTION: The PCI device 15 is provided with a device number setting register 151 for setting up a device number to be allocated to the device 15 itself, a prescribed bit is selected from AD[31:11] by a selector 153 based on IAD4-0 set up in the register 151 and the selected bit is used as internal IDSEL for selecting a configuration register 154. Since which bit in the AD[31:11] is selected as the internal IDSEL is determined by the IAD4-0 set up in the register 151, the device 15 can flexibly deal with the change of configuration address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a peripheral device used in the computer system, and more particularly to a computer for selecting an arbitrary bit of an upper bit portion of address data in a configuration cycle in a configuration register of the peripheral device. The present invention relates to a computer system used as a selection signal and peripheral devices used in the system.

[0002]

2. Description of the Related Art Conventionally, an ISA (Industry) is used as a system bus for a personal computer.
The standard architectural (EISA) bus and the EISA (extended ISA) bus have been the mainstream. Recently, however, in order to increase the data transfer speed and to construct a system architecture independent of a processor, a PCI (Peripheral Component) is used.
nt Interconnect buses are beginning to be adopted.

The PCI bus is a clock synchronous input / output bus, and all cycles on the PCI bus are performed in synchronization with the PCI bus clock. The frequency of the PCI bus clock is a maximum of 33 MHz. The PCI bus has an address / data bus (AD bus) used in a time-division manner. This address / data bus is 32 bits wide. A cycle on the PCI bus consists of an address phase followed by one or more data phases. In the address phase, the address and transfer type are output, and in the data phase, 8-bit, 16-bit, or 32-bit data is output. All data transfer is based on block transfer, and each of these block transfers is realized using burst transfer.
Thereby, for example, a data transfer rate of 133 Mbytes / sec at the maximum can be realized on the PCI bus.

Therefore, when the PCI bus is adopted,
Data transfer between I / O devices and between a system memory and an I / O device can be performed at high speed, and system performance can be improved.

By the way, in the PCI bus specification, I
A configuration cycle is prepared in addition to the / O cycle and the memory cycle. The configuration cycle is used to set the operating environment of each peripheral device connected to the PCI bus. That is, P
Each peripheral device connected to the CI bus has a configuration register for setting the characteristics, type, operation mode, etc. of the device, and the cycle used to access the configuration register is configured. It is a ration cycle.

[0006] There are two types of configuration cycles, "type 0" and "type 1". "Type 0"
Is a cycle in which all peripheral devices connected to the PCI bus can be targeted, and the "type 1" configuration cycle is a cycle in which only the PCI-PCI bridge responds. The “type 1” configuration cycle is used only when starting access across the PCI bus.

[0007] Both types of configuration cycles consist of an address phase and a subsequent data phase.
D bus lines have different definitions. FIG. 6 shows the definition of the AD bus line in the address phase.

AD [1: 0] indicates the type of configuration cycle, and “00” indicates type 0, “0”.
1 "indicates type 1. In type 1, FIG.
As shown in FIG. 6B, the contents of the AD bus include all of the bus number, device number, function number, and register number, but in the case of type 0, it is shown in FIG. As described above, the contents of the AD bus do not include the bus number and the device number. Type 0 without bus number
Is a bus cycle used only in the same PCI bus.

In type 0, instead of a device number,
IDSEL (Initialization Devi)
ce Select) is used. This IDSEL is used as a chip select signal, and is a signal valid only in the address phase of the type 0 configuration cycle. Each peripheral device is provided with a pin for inputting IDSEL, IDSEL is asserted, and AD [1: 0]
Is the target of the configuration cycle only when is "00".

Normally, for the purpose of simplifying the routing of wiring on the system board, each peripheral device is provided with unused A in a type 0 configuration cycle.
One of D [31:11] is input as IDSEL. In this case, IDSEL in each peripheral device
Are as shown in FIG. 7A.

Further, when a plurality of devices are constituted by one chip LSI, it is necessary to use a plurality of IDSELs in one LSI. This state is shown in FIG. FIG. 7B shows the configuration register # 1
Device and configuration register # including
This is an example of a case where the second device including the device ID 2 is integrated into a one-chip LSI. In this case, as shown in the figure, a first IDSEL (IDSEL1) used to access the configuration register # 1 and The second I used to access the configuration register # 2
DSEL (IDSEL2) is required.

[0012]

As described above, conventionally, a device number to be assigned to a peripheral device, that is, a configuration address, is determined by the connection of the IDSEL pin of each peripheral device. For this reason, after the system is mounted, there is a problem that it is not possible to cope with a change in the configuration address.

Also, one IDS is provided for each module.
Since EL is required, a plurality of modules can be
In the case of SI, a plurality of IDSELs
Had to be entered. For this reason, there has been a problem that the number of pins of the LSI is increased and the cost is increased.

The present invention has been made in view of such a point, and an object of the present invention is to provide a computer system and a peripheral device that can flexibly respond to a change in a configuration address.

It is another object of the present invention to provide a computer system and a peripheral device capable of realizing a plurality of modules by a one-chip LSI without increasing the number of IDSEL signals.

[0016]

According to the present invention, a computer for executing a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of a peripheral device. In the system, the peripheral device includes a device number setting register in which a device number to be assigned to the peripheral device is set.
Means for selecting a predetermined bit from the upper bit portion of the address data based on the device number set in the device number setting register, and using the bit as a selection signal for selecting a configuration register of the peripheral device; A computer system comprising:

In this computer system, a device number setting register for setting a device number to be assigned to the device is provided in a peripheral device, and an address is set based on the device number set in the device number setting register. One predetermined bit is selected from the upper bit part of the data. This selected bit is the IDS that selects the configuration register.
Used as EL and used to access a configuration register in a type 0 configuration cycle. Therefore, if one bit in AD [31:11] asserted in the address phase of the type 0 configuration cycle is the selected one bit, the configuration register is accessed.

Which bit of the address data is selected is determined by the device number set in the device number setting register. Therefore, the system designer can assign an arbitrary device number to the peripheral device regardless of the connection of the IDSEL on the system board, and can easily change the device number.

The I / O assigned to the peripheral device
In the case where the O address is fixedly determined, or in the case of a peripheral device that is always used for a specific I / O address even if it is variable, the device number setting register uses the I / O cycle. I accessed
The / O register can be used. As a result, the device number can be set and changed without using a configuration cycle, so that a configuration in which no input pin for the IDSEL signal is used can be realized.

Further, a plurality of modules can be integrated into a one-chip LSI.
, It is preferable to provide the above-described configuration for each module. As a result, IDSEL
A one-chip LSI incorporating a plurality of modules can be realized without increasing the number of pins for inputting signals.

Further, a plurality of modules are connected to one chip LS
In the case of I conversion, one corresponding to a specific module
Only one IDSEL signal input pin is prepared, a registerless designating a device number of another module is prepared in a configuration register of the module, and an IDSEL of another module is generated from the device number set in the register. It is more preferable to do so.
As a result, the device number of another module can be set in a configuration cycle for a specific module.
Even in a device for which an O address is set, it is possible to execute a configuration cycle for all modules without any problem simply by providing one input pin for an IDSEL signal.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention.
This computer system is a portable personal computer of a notebook type or a laptop type. On a system board thereof, a processor bus 1, a PCI bus 2, a CPU 11, a host-PCI bridge device 12, a main memory 13, various PCI devices are provided. 1
4, 15 are provided.

The CPU 11 is, for example, a microprocessor “Pent” manufactured and sold by Intel Corporation in the United States.
ium "etc. This CPU 11
Processor bus 1 directly connected to the input / output pins of
It has a 4-bit data bus. Main memory 13
Is a memory device that stores an operating system, a device driver, an application program to be executed, processing data, and the like.
M.

The main memory 13 is connected to the host-PCI bridge device 12 via a dedicated memory bus having a 32-bit or 64-bit data bus. The data bus of the processor bus 1 can be used as the data bus of the memory bus. in this case,
The memory bus includes an address bus and various memory control signal lines.

The host-PCI bridge device 12 is a bridge LS connecting the processor bus 1 and the PCI bus 2.
I, which functions as one of the bus masters of the PCI bus 2. The host-PCI bridge device 12 has a function of bidirectionally converting a bus cycle including data and addresses between the processor bus 1 and the PCI bus 2, and a function of controlling access to the system memory 13 via the memory bus. And so on.

The PCI bus 2 is a clock synchronous type input / output bus, and all the cycles on the internal PCI bus 2
This is performed in synchronization with the I bus clock. The frequency of the PCI bus clock is a maximum of 33 MHz. PCI bus 2
Has an address / data bus used in a time-division manner. This address / data bus is 32 bits wide.

A cycle on the PCI bus 2 comprises an address phase and one or more data phases following it. In the address phase, an address and a transfer type are specified, and in the data phase, 8-bit, 16-bit, 24-bit or 32-bit data is output.

The cycles executed on the PCI bus 2 include a memory cycle, an I / O cycle, and a configuration cycle. The configuration cycle includes type 0 and type 1 as described above. In the address phase of the type 0 configuration cycle, the host-PCI bridge device 12 controls the address / data bus (AD) AD [3].
1:11] is asserted.

The PCI devices 14 and 15 are host-PC
Like the I-bridge device 12, it is an agent of the PCI bus 2, and operates as an initiator or a target. Actually, for example, a graphics controller, a PC
I-ISA bridge, PC card controller, DVD
Peripheral devices such as decoders are used for these PCI devices 1
4, 15 are provided.

Hereinafter, taking the PCI device 15 as an example,
Configuration address change or IDSEL
A configuration for reducing the number of pins will be described. here,
It is assumed that the PCI device 15 is a single function device. As shown in the figure, the PCI device 15 has a device number setting register 151, a decoder 152, a selector 153,
And a configuration register 154.

The device number setting register 151 stores P
A device number assigned to the CI device 15, that is, information indicating which bit in AD [31:11] to use as the IDSEL in the address phase of the type 0 configuration cycle is set.
This information is shown in FIG.

The 5 bits of IAD4-0 are 1 in 21 bits of AD [31:11] that can be used as IDSEL.
Specify one. ENB indicates the validity / invalidity of the IAD 4-0, and is used to prevent an erroneous configuration access from being performed, for example, when the power is turned on or when the setting of the configuration address is changed. For example, ENB is set to "1" only after the correct IAD4-0 is set in the system initialization processing after power-on, and is set to "0" until that time.

The decoder 152 decodes the IAD4-0 of the device number setting register 151 and asserts one bit of the 21-bit address selection signal SAD31-11 to "1". The decoding operation of the decoder 152 is prohibited when ENB = "0", and the address selection signal S
All bits of AD31-11 are held at "0".

A 21-bit address selection signal SAD31
-11 corresponds to 21 bits of AD [31:11], respectively. The selector 153 outputs the address selection signal S
An internal IDS for selecting one bit from the 21 bits of AD [31:11] based on AD31-11 and using it to access the configuration register 153
Output as an EL signal. That is, one bit in AD [31:11] corresponding to the asserted one bit in the address selection signal SAD31-11 is set to the internal IDSE.
Generated as an L signal. FIG. 3 shows a specific configuration example of the selector 153.

As shown in FIG.
3 has 21 two-input AND gates 201 and these A
21-input OR to which the output from ND gate 201 is input
It can be composed of a gate 202.

Next, the operation of the PCI device 15 for a type 0 configuration cycle will be described. Here, the I of the device number setting register 151
It is assumed that AD 31 is assigned as the device number of the PCI device 15 by AD 4-0.
In this case, the most significant bit S in the 21-bit address selection signal SAD31-11 output from the decoder 152
Since AD31 is asserted to “1”, the selector 15
3 selects AD 31 and outputs it as internal IDSEL.

In the address phase of the type 0 configuration cycle targeting the PCI device 15, AD31 is asserted to "1".
Therefore, the internal IDSEL is asserted to “1”,
The configuration register 154 will be selected. The timing of the type 0 configuration read cycle is as shown in FIG. 4, which is the same as a normal cycle using the IDSEL signal pin.

As described above, according to the configuration of FIG.
Device number setting register 1 for setting a device number to be assigned to the device in I device 15
51 is provided, and AD [3] is set based on the IAD4-0 set in the device number setting register 151.
1:11], a predetermined bit is selected, which selects the configuration register 154.
Used as EL. Therefore, if one bit in AD [31:11] asserted in the address phase of the type 0 configuration cycle is the selected one bit, the configuration register 154 is accessed.

Which bits of AD [31:11] are internal I
Whether it is selected as DSEL is determined by the IAD 4-0 set in the device number setting register 151. Therefore, the system designer can assign an arbitrary device number to the PCI device 15 regardless of the connection of the IDSEL on the system board, and can easily change the device number.

The PCI device 15 is a device in which an I / O address assigned to the PCI device 15 is fixed, or a specific I / O address is always used even if it is variable. In some cases, the device number setting register 151 includes an I / O
I / O registers accessed in cycles can be used.

This makes it possible to set and change the device number in the device number setting register 151 without using a configuration cycle.
A configuration in which no input pin for the DSEL signal is used can be realized.

When the PCI device 15 is constituted by a one-chip LSI including a plurality of modules each having a configuration register, the device number setting register 151 and the decoder 15
2, and the selector 153 are provided for each configuration register of each module. This makes it possible to integrate a plurality of devices, each of which has been conventionally used as a single device, into a one-chip LSI without providing an IDSEL signal input pin for each module.

Next, referring to FIG.
5 will be described. This PCI device 15
Is used as, for example, a PCI-ISA bridge, and is configured by a one-chip LSI including a plurality of modules each having a configuration register. Configuration register 101 of FIG.
Is for setting the operating environment of the first module. Access to the configuration register 101 is performed using a predetermined bit in AD [31:11] input via an IDSEL signal pin, as in the related art.

The configuration register 101 has device number setting registers 111 and 112 for designating device numbers of other modules. The device number setting register 111 is for setting a device number of a module for which an operation environment is set by the configuration register 102.

The module in which the operating environment is set by the configuration register 102 is provided with a decoder 252 and a selector 253 similar to the decoder 152 and the selector 153 described with reference to FIG.

According to the configuration shown in FIG. 5, another type 0 configuration cycle for the first module using a predetermined bit in AD [31:11] input via the IDSEL signal pin is used for another configuration. Since the device number of the module can be set, even for a device for which an I / O address is set in a configuration cycle, a device for all other modules can be provided simply by providing one input pin for an IDSEL signal. Numbers can be set and changed normally.

Although a single function device has been described as an example in the above description, a similar configuration can be applied to a multifunction device. However, the multifunction device is I
Since there is little need for a plurality of DSEL signal input pins, the merit tends to be reduced.

[0048]

As described above, according to the present invention, it is possible to flexibly cope with the change of the configuration address and to realize a plurality of modules by a one-chip LSI without increasing the number of IDSEL signals. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an entire computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing data contents of a bus number setting register used in the computer system of the embodiment.

FIG. 3 is an exemplary circuit diagram showing a specific configuration of a selector used in the computer system of the embodiment.

FIG. 4 is an exemplary timing chart showing a type 0 configuration cycle executed by the computer system of the embodiment;

FIG. 5 is an exemplary view showing another configuration example of the PCI device used in the computer system of the embodiment.

FIG. 6 is a diagram showing a use form of an address bus in an address phase of a configuration cycle used in a normal PCI system.

FIG. 7 is a diagram showing a connection state of an IDSEL signal in a conventional PCI device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Processor bus 2 ... PCI bus 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 14, 15 ... PCI device 151 ... Device number setting register 152 ... Decoder 153 ... Selector 154 ... Configuration register

Claims (8)

[Claims] 1. A computer system for executing a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of a peripheral device, wherein the peripheral device comprises: A device number setting register in which a device number to be assigned to the peripheral device is set, and a predetermined bit is selected from the upper bit portion of the address data based on the device number set in the device number setting register, and Means for using as a selection signal for selecting a configuration register of a peripheral device. 2. The computer system according to claim 1, wherein said device number setting register is an I / O register accessible by an I / O cycle executed by said computer system. 3. The method according to claim 1, wherein said device number setting register is valid.
2. The computer system according to claim 1, further comprising means for designating invalidity. 4. A computer system for executing a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of a peripheral device, wherein the peripheral device comprises: A first device number setting register configured from a one-chip LSI including first and second modules each having a configuration register, wherein a device number to be assigned to the first module is set; A first bit for selecting a predetermined first bit from an upper bit part of the address data based on a device number set in a number setting register, and selecting the first bit for selecting a configuration register of the first module. Selection signal A second device number setting register in which a device number to be assigned to the second module is set; and the address data based on the device number set in the second device number setting register. Means for selecting a predetermined second bit from the upper bit part of the second module and using the second bit as a second selection signal for selecting a configuration register of the second module. Computer system. 5. The computer according to claim 4, wherein said first and second device number setting registers are I / O registers accessible by an I / O cycle executed by said computer system. system. 6. A computer system for executing a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of a peripheral device, wherein the peripheral device comprises: A one-chip LSI including first and second modules each having a configuration register, and a first selection signal for selecting a configuration register of the first module, a predetermined value in an upper bit part of the address data An input terminal to which the first bit of the first module is input; and a configuration register of the first module selected by the first selection signal input from the input terminal, which should be assigned to the second module. A device number setting register in which a device number is set; and a predetermined second bit selected from the upper bit portion of the address data based on the device number set in the device number setting register. Means for use as a second selection signal for selecting a configuration register of the second module. 7. A peripheral device used in a computer system that executes a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of the peripheral device. A device number setting register in which a device number to be assigned to the peripheral device is set; and a predetermined bit selected from the upper bit portion of the address data based on the device number set in the device number setting register. Means for using as a selection signal for selecting a configuration register of the peripheral device. 8. A peripheral device used in a computer system for executing a configuration cycle by using an arbitrary bit of an upper bit portion of address data as a selection signal for selecting a configuration register of the peripheral device. The peripheral device includes a one-chip LSI including first and second modules each having a configuration register, and the address data as a first selection signal for selecting a configuration register of the first module. An input terminal to which a predetermined first bit in the upper bit portion of the first module is input; and an input terminal provided in a configuration register of the first module selected by the first selection signal input from the input terminal; Two moji A device number setting register in which a device number to be assigned to the module is set; and a second predetermined bit selected from the upper bit portion of the address data based on the device number set in the device number setting register. Means for using a bit as a second selection signal for selecting a configuration register of the second module.