JPS63223848A - Computer system - Google Patents

Abstract

PURPOSE:To decrease the number of pins of an LSI and to shorten the delay time by using a specific pattern of a space identifier of each LSI as a common segment. CONSTITUTION:The output of a logical address part L of a TLB 31 in an address conversion buffer (TLB)-LSI 3 is inputted to a comparator 32. The output of a space identifier (ID) part S is inputted to a comparator 33 and also to a decoder 36. When the coincidence is detected from both comparators 32 and 33, an OR gate 35 and an AND gate 34 are opened and the coincidence signals are outputted from the TLB-LSI 3 for each LSI. While the part S outputted from the TLB 31 is decoded by decoder 36 and the gate 35 is opened for a pattern that is previously specified as a common segment. In this case, if the comparator 32 detects the coincidence, an AND gate 34 is opened and the coincidence signals are outputted from the LSI 3 for each LSI.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a computer system using multiple virtual memory.
The present invention relates to a computer system that eliminates common segment bits passing through an LSI, thereby reducing the number of LSI pins and reducing delay time.

[Conventional technology]

Conventionally, each entry in an address translation buffer (hereinafter referred to as TLB) of a computer system that employs a multiple virtual memory method includes a space identifier (hereinafter referred to as space ID), a common segment bit, a logical address, and a physical address. There is.

The space ID identifies which virtual space the logical address belongs to, and the common segment bit indicates that the logical address belongs to the common space. In addition, related technology is
There is No.-55654.

[Problem that the invention seeks to solve]

In the above conventional technology, when a memory access is performed, the TLB is indexed, and (1) when the logical address and space ID at the time of the memory access match the logical address and space ID written in the TLB entry, (2) When the logical address at the time of the memory access matches the logical address written in the 'l'LB entry and the common segment bit written in the TLB entry is "11", the real address of the corresponding TLB entry is used. main memory is accessed.

Therefore, the TLB is configured with multiple LSIs, and the space I
When D is divided into multiple LSIs, it is necessary to send a common segment pit to each LSI and use it as a DR with a spatial ID matching signal, which increases the number of LSI pins and increases the delay time. There was a growing problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiple virtual memory computer system that eliminates the above-mentioned problems, eliminates the LSI crossing of the common segment pit, reduces the number of LSI pins, and reduces delay time. be.

[Means for solving problems]

The above purpose is to create a space ID L that is divided into multiple LSIs.
This is accomplished by using a specific pattern of SI units as a common segment.

[Effect]

In each LSI of the TLB composed of multiple LSIs, the comparison result of the space ID and the signal decoded with the specific pattern of the space ID are ORed, and the output is ANDed with the comparison result of the logical address and output from each LSI. .

In other words, a coincidence signal for each LSI can be obtained from each LSI without passing the common segment pit from one LSI to another.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The output of the lower part of logical address register 1 is TLB-L.
SI3 and TLB - TLB31 and T in LS I4
It is input as the address of LB41.

Also, the output of the upper part of logical address register 1 is TLB
- The output of the middle part of the logical address register 1 is input to the comparator circuit 3' in the TLB-LSI S.
It is input to the comparison circuit 42 in J.

The output of the upper part of space ID register 2 is TLB-LSI
The output of the lower part of register 2 from the space is input to the comparison circuit 53 in TLB-LS I4.
is man-powered.

The output of the logical address part (L part) of TLB 51 in TLB-LS I 5 is input to the comparison circuit 32, and the space ID
The output of the section (8th section) is input to the comparator circuit 33 and also to the decoder 56. The output of the comparison circuit 33 and the output of the decoder 56 are input to the OR gate 35, and the output of the comparison circuit 52 and the output of the OR gate 35 are input to the AND gate 54.
is man-powered.

The output of the AND gate 34 and the output of the real address section (P section) of the TLB 51 are output from the TLB-LSI 5.

Logical address section (L) of TLB41 in TLB-LSI4
The output of the space ID section (8) is input to the comparator circuit 42, and
The output of the section) is input to the comparator circuit 43 and also to the decoder 46. Output of comparison circuit 43 and decoder 4
The output of the comparison circuit 42 and the output of the OR gate 45 are output to the AND gate 44.

The output of the AND gate 44 and the real address part of the TLB 41 (
The output of section P) is output from TL'B-LSI, a.

TLB-LS I 5's AND gate 34 output and TL
The output of the AND gate 44 of the B-LS I 4 is input to the AND gate 5.

The TLB 51 in the TLB-LSIS is accessed using the lower part of the logical address register 1 as an address, and outputs a logical address part (L part), a space ID part (8 parts), and a real address part (P part).

The (L part) and (8 part) output from the TLB 51 are compared with the upper part of the logical address register 1 and the upper part of the space ID register 2 by comparison circuits 52.55, respectively, and the (P part) is output from the TLB- Output from LSI3.

If the comparison circuits 52 and 53 both detect a match, the OR gate 35 and the AND gate 34 are opened, and the TLB
- LSI 3 outputs a match signal for each LSI.

On the other hand, the (8 parts) output from the TLB 51 is decoded by the decoder 36, and when the pattern is specified as a common segment in advance, the OR gate 55 is opened. At this time, if the comparison circuit 52 detects a match, the AND gate 34 is opened and the TLB-LSI 5 to LS
A coincidence signal of I units is output.

Similarly, a match signal in LSI units is obtained from TLB-LSI 4, except that the inputs of comparator circuits 42 and 45 are the middle part of logical address register 1 and the lower part of space ID register, respectively. Since this is just an operation, the explanation will be omitted.

The LSI unit match signal obtained from TLB-LSI s 4 is ANDed by an AND gate 5 to obtain a TLB match signal.

FIG. 2 shows a conventional embodiment for comparison.

In the conventional embodiment shown in FIG. 2, the decoders 36 and 46 of the present invention shown in FIG. This is the same as the present invention except that the common segment bits are input to TLB-LSI 5 to TLB-LSI 4.
This leads to an increase in the number of LSI bins due to the transfer of the LSI to the LSI.

The delay time until a matching output is obtained in LSI units is increased.

Therefore, according to this embodiment, the number of LSI pins can be reduced and the delay time can be reduced.

〔Effect of the invention〕

According to the present invention, in a computer system using a multiple virtual memory method in which a space identifier is divided into address translation buffers made up of a plurality of LSIs, the LSI of the space identifier of each LSI is
By using a common segment as the unit specific pattern, the number of LSI pins can be reduced and the delay time can be reduced. Furthermore, since the logic of each LSI can be configured with similar logic, LSI repeats can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1...Logical address register. 2...Space ID register. 3.4...TLB-LSI. 51.41...TLB. 52.55.42.45... Comparison circuit 54.44.5
...and gate. 55.45...or gate. 36.46...decoder. ／′−＼

Claims (1)

[Claims] 1. In a computer system using a multiple virtual memory method in which space identifiers are divided into address translation buffers made up of multiple LSIs, a multiple virtual memory is characterized in that a specific pattern of the space identifiers of each LSI for each LSI is used as a common segment. method computer system.