JPS6159553A - Address converter - Google Patents

Abstract

PURPOSE:To obtain an address converter executing a plural level of PX conversion functions efficiently by providing a plural prefix register (PXR) and executing more than two level of PX conversion functions by one comparison circuit or more. CONSTITUTION:A selector 9 selects a guest real address of a signal line 111 when a signal line 115A of a selector control circuit 8 is '1', selects all '0' of a signal line 114 when a signal line 115B is '1', and selects a guest PX value GPXR2 when a signal line 115C is '1', and a host PX value HPXR 3 of a signal line 113 when a signal line 115D is '1' respectively. The output of the selector 9 is trasnfered to a signal line 116 as a host absolute address. The specified conversion is made possible from the elation between a condition of the selector 9 and the host absolute address, i.e., two level of PX conversion is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address translation device for an information processing system having a virtual memory function.

[Background of the invention]

Generally, in an information processing system having a virtual memory function, there is a prefix conversion function as one of the address conversion processes. This prefix conversion function is a function that converts the accessed address using a prefix value specified in advance when the information processing system accesses the main memory and the address points to a specific area. be.

The most common prefix conversion function is that when an information processing system attempts to access addresses 0 to 4095, (
Convert the address to access the address (prefix value) + (0 to 4095), and then (prefix value) + (
0-4095) When trying to access an address, 0-4
This is a function that converts addresses so that 095i locations are accessed.

A conventional information processing system is equipped with one prefix register and one prefix conversion circuit each holding a prefix value for performing the prefix conversion, and realizes Lebel's prefix conversion function.

On the other hand, in order to realize a virtual computer system.

It is necessary for the virtual computer to have the same functions as the real computer, and the prefix conversion function is also required for both the real computer and the virtual computer. In this way, a virtual computer system requires two different prefix conversion functions, but as mentioned above, a real computer is only equipped with Lebel's prefix conversion function, and the prefix conversion function of a virtual computer is This was accomplished by passing the prefix conversion function of a computer to a virtual computer or by simulating it using a program on a real computer.

However, with the method of passing the prefix conversion function of the real computer to the prefix conversion function of the virtual computer, the real computer cannot perform prefix conversion during this time.In other words, this method essentially performs two-level prefix conversion. Therefore, it is necessary to arrange the program on the real computer and the virtual computer so that there is no contradiction even if the prefix conversion cannot be executed on the real computer side. This limitation is a major problem in realizing a virtual computer system. In addition, in the method of simulating the prefix conversion function of a virtual computer on a real computer,
The simulation overhead is large, and this is a problem that cannot be ignored even when the simulation is implemented using a microprogram on a real computer.

Incidentally, related virtual computer systems of this type include, for example, Japanese Patent Application Laid-Open No. 57-212680.

Next, as a conventional technique for preparing and using a plurality of prefix registers, for example, Japanese Patent Publication No. 58-50383 can be cited. Although this conventional technology has multiple prefix registers, only one prefix conversion circuit is provided.
and uses the contents of multiple prefix registers exclusively. That is, it is impossible to perform multiple prefix conversions at the same time, and as a result, even with this method, prefix conversions of two or more levels cannot be performed.
While the program on the virtual computer side is being executed, the program placement on the real computer side and the placement of the virtual computer must be done so that there is no conflict even if prefix conversion cannot be executed on the real computer side.

[Purpose of the invention]

An object of the present invention is to provide a virtual computer system.

An object of the present invention is to provide an address translation device that efficiently executes a multi-level prefix translation function.

[Summary of the invention]

A feature of the present invention is that a plurality of prefix registers are provided to store prefix values, and one or more comparison circuits are used to efficiently realize a prefix conversion function of two or more levels. In other words, by providing a prefix register for the virtual machine and a prefix register for the real machine, and efficiently executing both prefix conversion functions in hardware, efficient main memory access by the virtual machine is realized. . The contents of the plurality of prefix registers are checked simultaneously, and two or more levels of prefix conversion are performed in parallel.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. Sho 1
In this embodiment, there are two prefix registers storing prefix values, and two-level prefix conversion is performed.

In Figure 1, 1 is the address before prefix conversion (
This is an address translation subunit that sends out guest real addresses (hereinafter referred to as guest real addresses). 2 is a prefix register (hereinafter referred to as GP) that stores the prefix value used for the first prefix conversion (hereinafter referred to as guest prefix value).
This GPXR2 is preset with a predetermined guest prefix value via the signal a101.
is a prefix register (hereinafter referred to as HPXR) that stores a prefix value (hereinafter referred to as host prefix value) used for the second prefix conversion, and a predetermined host prefix value is stored in this GPXR3 via signal B102. is set in advance. 4 means all inputs are 0"
This is a zero detection circuit that detects that . Reference numerals 5, 6 and 7 are comparison circuits that detect coincidence between two input signals, and 8 is a selector control circuit that sends a predetermined signal to the signal line 115 according to the pattern of the input signal and controls the selector 9. A selector 9 selects and sends one of the input signal lines to the signal line 116.

The guest real address is transmitted from the address conversion subunit 1 via the signal line 111 to the zero detection circuit 4° comparator circuit 5. The guest prefix value is input to the comparison circuit 6 and the selector 9 from the GPXR 2 via the signal line 112. The signal is input to the comparison circuit 7 and the selector. HPXR
The host prefix value is sent to the comparator circuit 6.3 via the signal 1l13. 2 is input to the comparator circuit 7 and the selector 9. Furthermore, the all zero value is input to the selector 9 via the signal Ml14.

The zero detection circuit 4 sends 1'' to the signal line 201 if the guest real addresses input from the signal line 111 are all rr ON, and otherwise sends 0''. If the guest real address inputted from the signal line 111 and the guest prefix value inputted from the signal line 112 are equal, the comparison circuit 5 sends a signal 'l'' to the signal 111202, otherwise it sends II O'g. The comparison circuit 6 compares the guest real address input from the signal line 111 with the signal line 1.
If they are equal to the host prefix value input through signal a113, it sends '1'' to signal line 203, otherwise it sends out 11011. Comparison circuit 7 compares the guest prefix value input from signal a112 with the signal If the host prefix value input from the line 113 is equal (1"' is sent to the i-band line 204, otherwise "0" is sent.

The selector control circuit 8 includes a zero detection circuit 4 and a comparison circuit 5.
．． The outputs of comparison circuits 6 and 7 are connected to signal lines 201 and 2, respectively.
02, 203 and 204. Further, the output of the selector control circuit 8 is input to the selector 9 via a signal line 115. The selector 9 selects one of the data on the signal lines 111, 112, 113, or the signal line 114 under the control of the signal on the signal line 115, and sends it to the signal line 116. The data sent to this signal line 116 is the address C (which is referred to as a host absolute address) after two-level prefix conversion.

FIG. 2 shows details of the selector control circuit 8. Signal line 11
5A is a signal line that instructs the selector 9 to select and send the signal line 111, which is the guest real address, to the signal line 116, which is the output of the selector 9. Similarly, signal line 1
15B, 115C and signal line 115D are connected to the signal line 116 which is the output of the selector 9, the signal line 114 which is all zero, and the signal line 11 which is the guest prefix value, respectively.
This is a signal line that instructs to select and transmit the signal line 113 which is 2 or the host prefix value.

The operation of the selector control circuit 8 is as follows.

When the signal lines 201, 202 and the signal line 203 are both "0", the outputs of the inverters 21, 22 and 23 are both 1".
', and 1'' is sent to the signal line 115A via the AND gate 31. When both the signal line 201 and the signal line 202 are II OI/ and the signal line 203 is II L H, the inverter 21 and the inverter 22 Both outputs are “
1'', and '1'' is sent to the signal line 115B via the AND gate 32 and the OR gate 41. When both the signal line 201 and the signal a204 are II II II and the signal line 202 is '0'', The output of inverter 22 is 11
111, and rr 1 u is sent to the signal line 115B via the AND gate 33 and the OR gate 41. Signal line 201 is rr 1 n, signal line 202 and signal line 2
04 are both NOII, inverters 22 and 24
The outputs of both become '1', and '1' is sent to the signal line 115C via the AND gate 34. The signal line 202
is II 1 gg, II L H is sent to the signal line L15D via the AND gate 35.

The operations shown in FIG. 2 above are summarized in a table as shown in FIG. 3.

The selector 9 selects the guest real address of the signal line 111 when the signal line 115A of the selector control circuit 8 is P1''', and selects the guest real address of the signal line 111 when the signal line 115B is II II II.
4, all zeros, and when the signal line 115C is 1'', set the guest prefix value of the signal line 112 to the signal line 115C.
When D is 111'', each host prefix value of signal 47113 is selected.The output of selector 9 is sent to signal line 116 as the host absolute address.The relationship between the conditions of selector 9 and the host absolute address is summarized in a table. 6, that is, 2 levels of prefix conversion as shown in FIG. 4 is realized.

The illustrated embodiment can be modified as follows.

Although the embodiment shown in FIG. 1 has three comparison circuits, it is also possible to use one or two comparison circuits and perform the comparison operation sequentially, and one input of the comparison circuit can be used instead of the zero detection circuit. The zero detection circuit may be replaced with a comparator circuit in such a configuration that the zero detection circuit is set to 0''.

The AND gate 35 in the embodiment of FIG. 2 may be deleted,
Further, the signal lines 115A to 115D may be configured to send encoded outputs.

In the embodiment shown in FIG. 2, the signal lines 201 to 204 are input without any input conditions, but by connecting an AND gate to the input of each input signal and inputting a mode signal to this AND gate, the signal lines 201 to 204 are input to the inverter. Force input of 110
．． 7 may be used. In a similar manner, a configuration having a mode in which the individual signals of the signal lines 115A to 115C are forcibly set to ``0'''' may be adopted.

In the embodiment of FIG. 2, when the signal line 201 is 1'',
Although the configuration is such that III II II is output to 115A, 115B, or 115D, a configuration may be adopted in which only the signal line 115D becomes "1" by inputting a mode.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, two-level prefix conversion using two or more prefix values can be realized in one step, and the processing performance of the two-level prefix conversion function is dramatically improved. It is possible to improve the Furthermore, it is possible to adopt two-level prefix conversion from a performance standpoint, and it is also possible to solve the problem that was a restriction on the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a diagram summarizing the operation of the selector control circuit in Figure 2, and Figure 4 is a diagram showing the details of the selector control circuit in Figure 1.
FIG. 3 is a diagram summarizing the relationship between selection conditions and outputs of the selectors shown in the figure. 1... Address conversion subunit, 2, 3...
Prefix register, 4...Zero detection circuit, 5
．． 6.7... Comparison circuit, 8... Selector control circuit, 9... Selector. Figure 1 Figure 4

Claims (1)

[Claims] (1) An address conversion device having a prefix conversion function, which is characterized by comprising a plurality of prefix registers and one or more comparison circuits for prefix conversion, and performing multiple prefix conversion using a plurality of prefix values. Device.