JPH04156620A - Virtual computer system - Google Patents

Abstract

PURPOSE:To travel different OS in different processors by providing registers whose number is that of scalar units sharing vector units on the output port-side of address generation parts for vector registers. CONSTITUTION:Since copy registers RR holding address bases and address limits are incorporated to respective vector units VU in a virtual computer, different values can be set for respective vector processors VP. Thus, the domains of different virtual computers can be allocated to respective vector processors VP. Thus, respective vector processors VP can independently execute OS which can use a vector part. Then, different OS share a main storage and I/O and transfer data between OS at high speed while they can function as the totally different computers without the overhead of the virtual computer.

Description

[Detailed Description of the Invention] [Summary] An efficient virtual machine mechanism that allows different O8s to run on different processors in this type of virtual machine system, regarding a virtual machine system equipped with a scalar unit and a vector unit. With the aim of realizing The register holds the address base register value and address limit register value of the corresponding scalar unit.

[Industrial application field]

The present invention relates to a virtual computer system including a scalar unit and a vector unit.

With the development of vector processing devices in recent years, a plurality of OSs that can utilize vector processing mechanisms have come into existence, and a virtual computer mechanism that can run multiple O3s simultaneously is required. In a multiprocessor in which multiple vector processing units share main memory, each vector processing unit must be able to run a different virtual machine in order to run a different O3 that can use the vector processing mechanism for each processor. be.

[Conventional technology]

As a method of implementing a virtual machine mechanism in a conventional vector processing device, the vector unit has a copy of the address base register/address limit register that exists in the scalar unit, and the address base register/address limit register that exists in the scalar unit is stored in the vector unit. HARD copy register of vector unit when setting register/address limit register
It has already been proposed to execute and set the command as a command (see Japanese Patent Application No. 1-177640).

However, depending on the mode, vector computer systems (specially Japanese Patent Application No. 1-181377) and a vector computer system in which the vector access processing section is configured with multiple systems and the vector address generation section and main memory priority control section of all systems are synchronously controlled (Japanese Patent Application Laid-Open No. 1-181377). 127768), vector
Since the unit had only one set of address base register/address limit register, it was not possible to realize a virtual machine mechanism that functioned effectively in any mode.

[Problems to be Solved by the Invention] Therefore, for example, in the case of multiple processors, a problem arises in that the domain of a common virtual machine must be accessed.

An object of the present invention is to realize an efficient virtual machine mechanism in which different O8s can be run on different processors in a complex vector processing system as described above.

[Means to solve the problem] FIG. 1 is an explanatory diagram of the principle of the invention according to claim (1).

In the virtual computer system of the invention of claim (1), a plurality of vector processors vP each consisting of a scalar unit SU that processes scalar instructions and a vector unit ■U that processes vector instructions are installed in one main storage device. In a virtual machine system that shares an MSU, each vector unit U is provided with a duplicate register RR that holds the address base and address limit for the virtual machine, and the scalar unit's address base register/ When setting the address limit registers ABR/ALR, the corresponding vector unit vU's duplicate register RR
The feature is that the O value is also updated.

FIG. 2 is an explanatory diagram of the principle of the invention of claim (2).

The virtual computer system according to the invention of claim (2) is accessed by a vector processor vP including a scalar unit SU that processes scalar instructions and a plurality of vector units vU that processes vector instructions, and a vector processor vP. A virtual computer system comprising a main storage unit MSU, in which a replica register RR for holding an address base and an address limit for the virtual machine is provided for each vector unit (Vtl), and is connected to a scalar unit SU. In this mode, the scalar unit SU registers the address base register/address limit register ABR. /ALR is set, the replication register RRO values of all vector units VLI connected to the scalar unit SU are also updated at the same time.

FIG. 3 is an explanatory diagram of the principle of the invention of claim (3).

In the virtual computer system according to the invention of claim (3), the plurality of scalar units SKI are one vector unit v
A virtual computer system that shares a vector unit set consisting of U or a plurality of vector units vU, in which each vector unit vU corresponds to each scalar unit SU that shares the vector unit VU. A duplicate register RR is provided to hold the address base and address limit for the virtual machine, and the address base register/
When setting address limit registers ABR/ALR, the corresponding replica register RR of vector unit VU is updated.

FIG. 4 is an explanatory diagram of the principle of the invention of claim (4).

The virtual computer system of the invention of claim (4) is
3) In the virtual computer system described, each vector
For each address generation unit ADRS of a unit, a copy register RR that holds an address base and an address limit is provided corresponding to each scalar unit SU that shares the vector unit, and each scalar unit SU The hypervisor mode HP is added to the tag of the vector instruction sent to the vector unit vU from
V, and the vector instruction control unit Vi sends address generation information, hypervisor mode HP, to the address generation unit ADR5.
V, the scalar unit that identifies the scalar unit SU.
A main memory access instruction is sent with a unit number added, and the address generation unit ADR5 issues a request for the required vector length to the storage control unit MCU.
is on, the address base of the replicated register RR is not checked and the address limit check is not performed using the address limit of the replicated register RR, and when the hypervisor mode is off, the scalar unit is This system is characterized by performing address matching and address limit checking based on the address base and address limit of the duplicate register RR specified by the number.

[Effect]

The operation of the virtual computer system according to the invention of claim (1) will be explained. In the invention of claim (1), since each vector unit (U) has a copy register RR that holds an address base and an address limit, different values can be set for each vector processor vP. Therefore, it is possible to allocate different virtual machine domains to each vector processor vP. This allows each vector processor vP to independently execute O3 that can use the vector part, and
It becomes possible for O8 to share the main memory and Ilo to perform data transfer between O8 at high speed, and to function as a completely different computer with almost no virtual machine overhead.

The operation of the virtual computer according to the invention of claim (2) will be explained. In the virtual computer system of FIG. 2, the address generators of two vector units Vυ are connected to the same scalar unit SU. When an instruction to set the address base register/address limit register ABR/ALR is issued in the scalar unit Sυ, the vector instruction control part of the upper vector unit vU is sent from the scalar unit SU. Incoming address base value and address limit value and duplicate register R1? ABR/A to set data to
The LR setting instruction is sent to the address generation unit, and the connected address generation unit is activated. Address base value, address limit value and ABR/A
The LR setting instruction is sent to the replication register RR via the address generation section. In the virtual computer system according to the invention of claim (2), the replica register RR receives and receives the address base value, the address limit value, and the ABR/ALR setting instruction, and then changes the value of the replica register RR. Since all the duplicate registers of the vector units connected to the SU are updated at the same time, there is no loss of efficiency and control is simple (originally, in this mode, multiple address generators could be activated at the same time). structure). Therefore, there is no loss caused by having a plurality of duplicate registers RR holding address bases and address limits, and it is possible to configure a multiprocessor with highly parallel vector units.

The operation of the virtual computer system according to the invention of claim (3) will be explained. In the virtual computer system according to the invention of claim (3), a replication register RR is provided corresponding to each of the plurality of scalar units that share the vector unit vU. The address base and address limit are set in the replication register RR. In the example of FIG. 3, two duplicate registers RR are connected to the address generator, the upper duplicate register corresponds to the upper scalar unit SU, and the lower duplicate register corresponds to the lower scalar unit SU. Compatible with unit SU. scalar unit S
When setting the U address base register/address limit register ABR/ALR, this scalar
In the virtual computer system of the invention according to claim (3), which is characterized by all the duplicate registers RR corresponding to the unit SU, the address base and address limit are stored in the duplicate register RR every time the exclusive usage right of the vector unit VU is switched. It is efficient because there is no need to reconfigure the vector
HARD-OP ABR/ALR setting instructions in the unit
The scalar unit can be controlled separately from the vector unit (Japanese Unexamined Patent Publication No. 2-76069). In the virtual computer system according to the invention of claim (3), it is also possible to set different domains for each scalar unit, and each vector processor can independently flow O8 that can use the vector part, and different O3s can be used as main processors. memory and I
It is possible to share the lo and perform data transfer between O8s at high speed, while functioning as a completely different computer with almost no virtual machine overhead.

The operation of the virtual computer system according to the invention of claim (4) will be explained. In the virtual computer system according to the invention of claim (4), a scalar unit number SU and hypervisor mode 1 (PV) are added to each access request. , each of the scalar units that make up the dual scalar unit processor can switch between VM mode and hypervisor mode without being aware of other scalar units, and each scalar unit It can be operated in a so-called mixed mode, which mixes vector instructions without serializing them.

[Embodiment] FIG. 4 is a block diagram of an embodiment of the present invention, showing a multi-vector virtual computer system that covers all of claims (1) to 4). In the same figure, SU
O to 5t13 are scalar units, VUO and Vll
l is a vector unit, ViO and Vil are vector instruction control units, ^DR3O and ADR5I are address generation units, MCU is a storage control unit, PRIORITY is a priority circuit, MStl is a main storage unit, and ROI or I
? 05 is a tag register, R21 to R25 are also tag registers, 10 and 12 are selectors, 20 and 22 are switch circuits, 30 and 32 are data registers, 40 and 42
are merge circuits, 50 and 52 are selectors, 60 and 62 are start address registers/distance address registers, 70 to 73 are selectors, 80 to 83 are logical address holding registers, 90 to 93 are index registers, 100 103 to 103 are adders, 110 to 113 are logical address registers, 120 to 1
23 is an address translation register, 130 to 133 are merge circuits, 150 to 153 are request address registers, 160 to 163 are adders, 170 to 173 are selectors, 180 to 183 are merge circuits, 190 to 193 are addressing exceptions Check circuits 200 to 203 are scalar unit addresses.
Duplicate registers holding base and address limits, 210-213 represent selectors, respectively.

Scalar unit SUO and scalar unit SU1 are connected to vector instruction control section ViO of vector unit vUO, and scalar unit SU2 and scalar unit SU3 are connected to vector instruction control section Vi of vector unit VUI. .

When a vector main memory access instruction is detected, the scalar unit SUO transmits the detected vector main memory access instruction, address creation information (start address, distance, index, etc.), vector length, etc. to the vector instruction control unit. Send to Vi. Furthermore, when setting or updating the contents of its own address base register/address limit register, the scalar unit sends control information or an ABR/ALR setting command to the vector unit.

Send address base value and address limit value to vector unit. For details, please refer to Japanese Patent Application No. 1-177.
No. 640. Other scalar units SU
I to SU3 perform similar operations.

Vector unit vUO and vector unit VLI
Since I has the same configuration, the vector unit v
The UO will be mainly explained.

The vector unit VUO is a vector instruction control unit Vi
0 and an address generating section ADR5O.

The vector instruction control unit ViOO includes a selector 10 and a switch circuit 20. Data register 30. merge circuit 4
0. There are tags, registers ROI, etc. Selector 1
The data sent out from the scalar unit SUO and the data sent out from the scalar unit SU1 are input to 0, and the input data designated by the switch circuit 20 is outputted from the selector 10. switch circuit 20
is used to instruct the selector 10 which input data should be selected. For example, switch circuit 20
When it indicates 0, the data sent from the scalar unit SUO is output from the selector 10, and when it indicates 1, the data output from the scalar unit SUI is output from the selector 10. Further, a scalar unit number is output from the switch circuit 20, and this scalar unit number is input to the tag register ROI.

The scalar unit number corresponds to a selection instruction signal sent from the switch circuit 20 to the selector 10.

Address creation information (starting address, distance, index) and control information are set in the data register 30. The control information includes a bit opcode, a part of psw, and the like. The hypervisor bit specifies whether or not it is in hypervisor mode.

The scalar number of the tag register ROI and the control information of the data register 30 are input to a merge circuit 40, and the merge circuit 40 outputs tag information consisting of a scalar unit number and control information.

Address generation unit ADR5O has a selector 50. The upper input terminal of the selector 50 is connected to the output of the data register 30 of the vector instruction control unit ViO, and the lower input terminal is connected to the output of the data register 32 of the vector instruction control unit Vil. Data output from selector 50 is sent to start address register/distance register 60. Code 70.80.・
. . , 130 constitute a 0-side address pipeline, and 71.81° . . . , 131 constitute a 1-side address pipeline. The 0-side address pipeline is used for block accesses, and the 0-side and 1-side address pipelines are used alternately for distance or indirect accesses. be done. There are two address translation registers 120, and the one designated by the scalar unit number is used. The same applies to address translation registers 121, 122, and 123. Regarding the address pipeline, JP-A-61
Since it is explained in detail in Japanese Patent No. 264455, the explanation will be omitted.

The tag information from the merge circuit 40 is input to the upper input terminal of the selector 140, and the tag information from the merge circuit 42 is input to the lower input terminal of the selector 140. The tag information output from the selector 140 is sent to the storage control device MCυ via tag registers RO2, RO3, and RO4. Selector 50 and selector 140 perform the same operation. That is, when the selector 50 selects the data on the upper input terminal, the selector 140 also selects the data on the upper input terminal, and when the selector 50 selects the data on the lower input terminal, the selector 140 also selects the data on the lower input terminal. do.

The storage control device MC[I will be explained. The request address from the merge circuit 130 of the address generator ADR5O is set in the request address register 150 of the storage control device MC[I. Upper address of request address register 150 and selector 210
The adder 160 adds the address base output from the adder 160. The output of adder 160 and the upper address of request address register 150 are selector 1
70, and the selector 170 selects the upper input data when the hypervisor bit is 0, and selects the lower input data when the hypervisor bit is 1.

The output of selector 170 and the lower address of request address register 150 are merged by merge circuit 180. Addressing exception check circuit 190
outputs 1 if the address from the merge circuit 180 (system absolute address) exceeds the address limit from the selector 211.

The request address register 151 receives a request from the merge circuit 131 of the address generator ADR3O.
Address is set. The upper address of the request address register 151 and the address base are added by an adder 161, and the addition result and the request address
The upper address of the register 151 is input to the selector 171, the output of the selector 171 and the lower address of the request address register are merged in the merge circuit 181, and the output (system absolute address) of the merge circuit 181 exceeds the address limit. The addressing exception check circuit 191 checks whether the limit is exceeded.

The tag information in the tag register RO5 includes a scalar unit number and control information (hypervisor bits.

operation code, part of psw, etc.).

When the hypervisor bit is 0, selector 170
selects the upper input data, and when the hypervisor bit is 1, the selector 170 selects the lower input data. Selector 171 performs the same operation as selector 170.

A copy register 200 is provided at the upper input terminal of the selector 210.
The address base of the copy register 201 is input to the lower input terminal of the selector 210. The address limit of the copy register 200 is input to the upper input terminal of the selector 211, and the address limit of the copy register 201 is input to the lower input terminal of the selector 211.

If the hypervisor bit of tag register RO5 is 0 and the scalar unit number is 00, selector 210 selects the upper input data;
In this case, the selector 210 selects the lower input data. Selector 211 also performs the same operation as selector 210.

If the opcode indicates an ABR/ALR setting, registers 200 and 201 are in a write enable state. Note that ABR/ALR represents address base register/address limit register.

Furthermore, when setting ABR/ALR, the address base and address limit flow through the address pipeline on the O side. Under the ABR/ALR setting state, if the scalar unit number in the tag information is 0, the merge circuit 13
The address base and address limit from 0 are set in the duplicate register 200, and the scalar in the tag information is
If the unit number is 1, the address base and address limit from the merge circuit 130 are the duplicate register 2.
Set to 01.

Portions 152 to 212 and portions 153 to 213 in the storage control unit MCU are address generators ^DR.
This is the part for 5I. The parts 152 to 212 and the parts 153 to 213 are 150 to 210.
The operation is the same as that of the section and the sections 151 to 211.

The system of FIG. 4 can be configured with various types of DSUPs (dual scalar unit processors). With the system shown in Figure 4, two DSUPs can be realized. In this case, the scalar unit SUO
, scalar unit 5ill and vector unit vUO constitute one DSUP, and scalar unit S
U2, scalar unit SU3, and vector unit vU1 constitute another DStJP. The selector 50 and selector 140 of the vector unit VUO select the upper input booter, and the vector unit VUI
The selector 52 and selector 142 select lower input data.

SCARA unit 5 units 0. a DSUP composed of a scalar unit SUI and a vector unit vUO;
Scalar unit SU2, Scalar unit 5t13
and vector unit) VIJI DSU
Since the operation of P is the same, the scalar unit SUO,
Scalar unit SUI and vector unit vu
The operation of the DSUP configured with o will be explained.

When the scalar unit SUO sends the ABR/ALR setting command, address base value and address limit value to the vector unit vUO, these address base value and address limit value are set in the replication register 200. Similarly, scalar unit SU1 is ABR/
When the ALR setting command, address base value, and address limit value are sent to the vector instruction control unit ViO, these address base value and address limit value are set in the copy register 201.

When scalar unit SUO or SUI sends a vector main memory access command, address creation information, etc. to vector unit vUO, a request address is output from address generator ADR5O. Address generation part ADR
The request address from 3O is scalar unit S
If it is based on instructions and data from the UO, the duplicate register 200 is selected. Address generation part AD
Duplicate register 201 is selected if the request address from R5O is based on instructions and data from scalar unit SUI.

In the system shown in Figure 4, the scalar unit SUO.

Scalar unit SUI, vector unit VUO.

One DSUP can be configured with a vector unit VUI. In this case, the vector unit vU
The selector 50 and selector 140 of O select the upper input data, and the selector 52 of vector unit vU1 selects the upper input data.
The selector 142 also selects the upper input data. Scalar unit SU2 and scalar unit SU3 operate without a vector unit.

Scala uni) SUO, Scala uni nt SUI.

vector unit VUO, vector uni-no) VL
The operation of DSUP configured with tl will be explained.

When the scalar unit SUO sends the ABR/ALR setting command, the address base value and the address limit value to the vector unit vUO, these address base values and address limit values are stored in the duplicate register 200.2.
Set to 02. Similarly, the scalar unit SUI
When the ABR/ALR setting command, address base value, and address limit value are sent to the vector instruction control unit ViO, these address base value and address limit value are set in the copy registers 201 and 203.

When the scalar unit SUO or SUI sends a vector main memory access command, address creation information, etc. to the vector unit vUO, the address generators ADRS0, A
A request address is output from DHSI. If the requested address from the address generator ADRSO is based on instructions and data from the scalar unit SUO, the duplicate register 200 is selected and the requested address from the address generator ADRSO is based on the instruction and data from the scalar unit SUO. If it is based on instructions and data, the duplicate register 201 is selected. Furthermore, if the request address from the address generator ADR3I is based on the instruction and data from the scalar unit SUO, the duplicate register 202 is selected, and the request address from the address generator ADR3I is the scalar unit). If it is based on instructions and data from the SUI, the duplicate register 203 is selected.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the DSUP system can be used for both vector multi-processors and vector uni-processors in a mode in which a plurality of vector units operate in parallel. too,
For mixed mode of DSUP, each vector processor can utilize different O3O3-
It is possible to realize a virtual computer system that can operate by taking advantage of the advantages of 1-TC.

[Brief explanation of drawings]

1 to 4 are diagrams explaining the principle of the present invention, and FIG. 5 is a block diagram of one embodiment of the present invention. SUO or SU3...scalar unit, VUO and vUl...vector unit, ViO and Vil ・
...Vector instruction control unit, ADRSO and ADRSI...
・Address generation unit, MCU...Storage control unit, PRI
ORITY...priority circuit? lSU...
Main memory, ROI to RO5... tag register, R21 to R25... tag register, 10 and 1
2... Selector, 20 and 22... Switch circuit, 3
0 and 32...data register, 40 and 42...merge circuit, 50 and 52...selector, 60 and 62...
・Start address register/distance address・
Registers, 70 to 73...Selectors, 80 to 83...Logical address holding registers, 90 to 93
...index register, 100 to 103.
...Adder, 110 to 113...Logical address
Registers, 120 to 123...Address translation registers, 130 to 133...Merge circuits, 150 to 153...Request address registers, 1
60 to 163...Adder, 170 to 173.
. . . Selector, 180 . . . Merge circuit, 190 to 193 . . . Addressing exception check circuit, 200 to 203 .
··selector. Patent Applicant Fujitsu Limited Representative Patent Attorney Kyotani Yotsube 1st Criminal θ Moon Hara Factory Land Meizu Figure 1 Toki Bg, right? , Zhang Seday yi

Claims (4)

[Claims] (1) Scalar unit (SU) that processes scalar instructions
and a vector unit (VU) that processes vector instructions.
A plurality of vector processors (VP) consisting of
A virtual machine system that shares one main storage unit (MSU), where each vector unit (VU) is provided with a replicated register (RR) that holds an address base and an address limit for the virtual machine. A virtual computer characterized in that when setting an address base register/address limit register (ABR/ALR) of a scalar unit, a value of a replication register (RR) of a corresponding vector unit (VU) is also updated. system. (2) Scalar unit (SU) that processes scalar instructions
and multiple vector units (
A virtual computer system comprising a vector processor (VP) consisting of a VU) and a main storage unit (MSU) accessed by the vector processor (VP), wherein each vector unit (VU) A replica register (RR) is provided to hold the address base and address limit for the computer, and each vector unit (VU) connected to the scalar unit (SU) can perform divided processing units of one vector instruction in parallel. Under this mode state, the scalar unit (SU
) sets the address base register/address limit register (ABR/ALR), the replicated register (RR) of all vector units (VUs) connected to the relevant scalar unit (SU). A virtual computer system characterized in that the value of is also updated at the same time. (3) A virtual computer system in which multiple scalar units (SU) share one vector unit (VU) or a vector unit set consisting of multiple vector units (VU), For each vector unit (VU), there is a replicated register (RR) that holds the address base and address limit for the virtual machine, corresponding to each scalar unit (SU) that shares the vector unit (VU). ) and address base register/address limit register (ABR/ALR) of the scalar unit (SU).
A virtual computer system characterized in that when setting a vector unit (VU), a corresponding replication register (RR) is also updated. (4) In the virtual computer system according to claim (3), an address generation unit (ADRS) of each vector unit.
For each scalar unit (SU) that shares the vector unit, a replicated register (R
R), and from each scalar unit (SU) to a vector unit (
The vector instruction control unit (Vi) adds the hypervisor mode (HPV) to the tag of the vector instruction sent to the address generation unit (AD).
Address generation section (ADRS) adds address creation information, hypervisor mode (HPV), and a scalar unit number to identify the scalar unit (SU) and sends a main memory access instruction to the address generation section (ADRS). Then, a request for the required vector length is issued to the storage control unit (MCU), and when the hypervisor mode (HPV) is on, the storage control unit (MCU) issues the address of the replication register (RR). When the hypervisor mode is off without performing address enforcement by the base and address limit checking by the address limit of the replicated register (RR), the replicated register (RR) specified by the scalar unit number is ), based on the address base and address limit of the virtual computer system.