JPS63168752A - Address conversion buffer control system - Google Patents

Abstract

PURPOSE:To improve the processing capability of a processor by providing two buffers, an address conversion buffer in a processor chip and an address conversion buffer at the outside of the processor chip. CONSTITUTION:Even when no objective address conversion information exists in the address conversion buffer 2 in the processor chip, when the information exists in the address conversion buffer 7 at the outside of the processor chip, since the information is used for registration on an address conversion buffer in the processor chip and for address conversion, the address conversion processing is applied at a high speed. Moreover, the entry number and the constitution of the address conversion buffer 2 in processor chip are decided independently, the rate of indexing the address conversion list on the memory in case of the address conversion is reduced without giving affect on the processor chip by increasing the number of entries of the address conversion buffer 7 at the outside of the processor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for an address translation buffer in a microprocessor or the like which employs a virtual memory method and has an address translation buffer within a processor chip.

[Conventional technology]

The address translation buffer holds address translation pairs of logical addresses and real addresses in memory page units, and performs address translation from logical addresses to logical addresses at high speed without indexing the address translation table in memory. It was established for this purpose.

The number of address translation pairs that can be registered in the address translation buffer (i.e., the number of address translation pairs that can be registered in the address translation buffer) is determined by the number of required pages of the fo daram executed on the processor.

If the number of entries in the address translation buffer is large, the address translation table in memory will not be indexed during program execution (i.e., only the information registered in the address translation buffer will be used).
Address conversion can be performed and program processing can be performed at high speed.

[Problem that the invention seeks to solve]

However, in processors such as microprocessors that have an address translation buffer built into the processor chip, the amount of hardware that can be accommodated in one chip is small. , it was often necessary to index the address translation buffer in memory, which slowed down program processing time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for increasing the number of entries in an address translation buffer in a processor such as a microprocessor that has an address translation buffer built into the processor chip without increasing the amount of hardware in the processor chip.

[Companion means and effects for solving the problem] The present invention provides a low-speed, large-capacity address translation buffer outside the processor chip in a CPU (central processing unit) of a virtual memory type information processing system, and performs address translation. In this case, even if the high-speed, small-capacity address translation buffer inside the processor chip does not have the required information, if the address translation buffer outside the processor chip tends to have the address translation information, the address read from the address translation buffer outside the processor chip. The most important feature is that address translation is performed using translation information and the address translation information is registered in an address translation buffer within the processor chip.

This technology differs from the conventional technology in that it has two address translation buffers: an address translation buffer inside the processor chip and an address translation buffer outside the processor chip.

〔Example〕

FIG. 1 is a diagram explaining one embodiment of the present invention, in which 1 is a register that holds a logical page address within a processor chip, 2 is an address translation buffer within the processor chip, and 3 is a value of address register 1. A circuit for comparing the contents of the logical address section of the address translation buffer 2; 41 a dirt circuit for outputting the real address section of the address translation buffer 2; 5 a control circuit for indexing the address translation table on the memory to obtain a real address; 6 is a register that holds the real page address within the processor chip; 8 is an AND circuit; 11
4 is a register that holds a logical page address outside the processor chip; 7 is an address conversion buffer outside the processor chip; 31 is a circuit that compares the value of the address register 11 with the contents of the logical address section of the address conversion buffer 7;
2 is a dart circuit for outputting the real address part of the address translation buffer 7.

Address translation buffer 2 inside the processor chip consists of four entries (201 to 2o4) addressed by the lower two bits of address register l, and address translation buffer 7 outside the processor chip consists of four entries (201 to 2o4) addressed by the lower two bits of address register l.
16 entries addressed in the lower four pits of (
701 to 716). Each entry in the address translation buffer consists of a logical address section that holds the upper bits of the logical page address and an address section that holds the real page address.

When the processor performs address conversion, a logical page address (L bit) is set in both address registers 1 and 11.

When a logical page address is set in the address register l, the comparator circuit 3 reads out the entry 201 indicated by the lower two bits of the address register l among the entries in the address translation buffer 2, and reads out the entry 201. The contents of the logical address field and the upper part of address register 1 (L-
2) Compare with bit. If the content of the logical address field of the entry 201 and the upper (L-2) bit of the address register 1 match, the content of the real address field of the entry 201 is the desired real page address, and the dart circuit 41
is set in the address register 6 via the address register 6.

The desired address translation information is present in the address translation buffer 2 (that is, the contents of the logical address part of the entry 201 indicated by n indicated by the lower two bits of the address register 1,
If the upper (L-2) bit of address register 1 matches), the processor.

Information read from the address conversion buffer 7 outside the satig is suppressed by the dart circuit 42.

When the address register 11/C logical page address outside the processor chip is set, the comparator circuit 31ii reads out the entry 705 indicated by the lower 4 bits of the address register 11 among the entries in the address conversion buffer 7, and reads out the next entry. The contents of the logical address field 705 and the upper (L-4) bit of the address register 11 are compared. If the contents of the logical address field of the process/triff 05 and the upper (L-4) bit of the address register 11 match, fc
If the content of the address section of entry 705 is the desired real page address, and there is no desired address translation information in the address translation buffer 2 in the processor chip, then (
In other words, the lower two bits of address register 1, indicated by
If the contents of the logical address field of the entry 201 and the upper (L-2) bit of the address register 1 do not match), the contents of the real address field of the entry 705 are sent to the address register 6 via the dart circuit 42. Set. te, the lower 2 bits of the address register 1 of the address translation buffer 2 in the processor chip, and the value of the upper (L-2) bit of the address register 1 in the entry 201 indicated by g,
The real page address read from the real address field of entry 705 of address translation buffer 7 is registered.

There is no required address translation information in the address translation buffer 2 in the processor chip (that is, the contents of the logical address part of the entry 201 indicated by the lower 2 bits of the address register 1 and the upper (L-2) of the address register 1)
bits do not match), and there is no required address translation information in the address translation buffer 7 outside the processor chip (
In other words, if the contents of the logical address section of the entry 705 indicated by n indicated by the lower 4 bits of the address register 11 do not match the upper (L-4) bits of the address register 11, the control circuit 5 The conversion table is indexed, the logical baso address is converted to a real page address, and the address is set in the address register 6. Also, address register 1 of address translation buffer 2 in the processor chip
The value of the upper (L-2) bits of address register 1 and the real page address obtained from the address conversion table are registered in the entry 201 indicated by the lower two bits of
Entry 70 indicated by the lower 4 bits of the address register 11 of the address translation buffer 7 outside the processor chip
5, the value of the upper (L-4) bit of the address register 11 and the real page address obtained from the address conversion table are registered.

In this way, in the present invention, even if there is no address translation information required in the address translation buffer 2 within the processor chip, if there is information required in the address translation buffer 7 outside the processor chip, the address translation and internal processing are performed using this information. Because registration is performed in the address translation buffer, the address translation process is faster than in the case where the real page address is obtained by indexing an address translation table in memory.

In addition, address conversion outside the processor chip
The number of entries and configuration (number of sexy lines, number of entries in sexy days) can be determined independently of the number of entries and configuration of the address translation buffer 2 in the processor chip. Therefore, by increasing the number of entries in the address translation buffer 7 outside the processor, search, and program, the ratio of indexing the address translation table in memory during address translation can be reduced without affecting the processor chip.

〔Effect of the invention〕

The present invention makes it possible to increase the number of entries in the address translation buffer without increasing the amount of hardware on the processor chip in a processor such as a microprocessor that has an address translation buffer built into the processor chip. Conversion processing can be performed at high speed, and the throughput of the processor can be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a groove bottom showing an embodiment of the present invention. 1... A register that holds a logical page address in the processor chip, 2... Address translation buffer in the processor chip, 3... Compare the value of address register 1 and the contents of the logical address part of address translation buffer 2. 41...address conversion circuit. A dart circuit for the output of the real address section of NOA 2, 5... A control circuit that indexes the address conversion table on the memory to obtain a real address, 6... A register that holds a real page address in the processor chip, 8 ...AND circuit, 1 no.
...A register that holds logic (-) addresses outside the grossette chip, 7...An address translation buffer outside the grosser chip 7', 31...The contents of the address register IIO value and the logical address part of the address translation buffer 7 are stored. Comparison circuit 42: a dirt circuit for outputting the real address part of the address conversion buffer 7.

Claims (1)

[Claims] In a CPU of a virtual memory type information processing system, a high-speed, small-capacity first address translation buffer and a low-speed, large-capacity second address translation buffer are provided to perform address translation from a logical address to a real address. If the desired address translation information is registered in the first address translation buffer, address translation is performed using the address translation information read from the first address translation buffer, and the desired address translation information is registered in the first address translation buffer. If the address translation information is not registered in the second address translation buffer, address translation is performed using the address translation information read from the second address translation buffer, and the address translation information is registered in the first address translation buffer. ,
If the desired address translation information is not in either the first or second address translation buffer, address translation is performed using the address translation information obtained by referring to the address translation table in memory, and the address translation information is transferred to the second address translation buffer. An address translation buffer control method characterized by registering in both a first address translation buffer and a second address translation buffer.