JPS6322344B2 - - Google Patents
Info
- Publication number
- JPS6322344B2 JPS6322344B2 JP57233539A JP23353982A JPS6322344B2 JP S6322344 B2 JPS6322344 B2 JP S6322344B2 JP 57233539 A JP57233539 A JP 57233539A JP 23353982 A JP23353982 A JP 23353982A JP S6322344 B2 JPS6322344 B2 JP S6322344B2
- Authority
- JP
- Japan
- Prior art keywords
- semaphore
- bus
- access
- microprocessor
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 8
- 230000015654 memory Effects 0.000 description 24
- 238000010586 diagram Methods 0.000 description 8
- 239000000872 buffer Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101000654674 Homo sapiens Semaphorin-6A Proteins 0.000 description 1
- 102100032795 Semaphorin-6A Human genes 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57233539A JPS59123063A (ja) | 1982-12-28 | 1982-12-28 | マルチ・プロセツサ・システムの共有資源アクセス方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57233539A JPS59123063A (ja) | 1982-12-28 | 1982-12-28 | マルチ・プロセツサ・システムの共有資源アクセス方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59123063A JPS59123063A (ja) | 1984-07-16 |
JPS6322344B2 true JPS6322344B2 (bs) | 1988-05-11 |
Family
ID=16956631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57233539A Granted JPS59123063A (ja) | 1982-12-28 | 1982-12-28 | マルチ・プロセツサ・システムの共有資源アクセス方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59123063A (bs) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0222630U (bs) * | 1988-07-28 | 1990-02-15 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006151560A (ja) * | 2004-11-26 | 2006-06-15 | Mitsubishi Electric Corp | 乗客コンベアの制御装置 |
-
1982
- 1982-12-28 JP JP57233539A patent/JPS59123063A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0222630U (bs) * | 1988-07-28 | 1990-02-15 |
Also Published As
Publication number | Publication date |
---|---|
JPS59123063A (ja) | 1984-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5392436A (en) | Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration | |
US5555425A (en) | Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters | |
US5067071A (en) | Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus | |
US5625779A (en) | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | |
JPS5837585B2 (ja) | ケイサンキソウチ | |
US20030126381A1 (en) | Low latency lock for multiprocessor computer system | |
JPH0218657A (ja) | 複数バス・マイクロコンピユータ・システム | |
JPH0833875B2 (ja) | バス裁定システム | |
JP2007219816A (ja) | マルチプロセッサシステム | |
JPS6322344B2 (bs) | ||
JPS59229662A (ja) | 共有メモリ制御回路 | |
JP3240863B2 (ja) | 調停回路 | |
JPS63175964A (ja) | 共有メモリ | |
JPH05257903A (ja) | マルチプロセッサシステム | |
JPH054710B2 (bs) | ||
JPH0724044B2 (ja) | Dmaアクセスが可能なコンピユータ・システム | |
JPH0575140B2 (bs) | ||
JPS63298555A (ja) | 共有メモリ制御方式 | |
JPS642985B2 (bs) | ||
JP2001075826A (ja) | 並列計算機における高効率セマフォ処理方式 | |
JPS5830676B2 (ja) | メモリノフクシヤホウシキ | |
JPH086905A (ja) | マルチポートramのアクセス調停回路 | |
JPS62298861A (ja) | バスロツク制御方式 | |
JPH05204866A (ja) | マルチcpuシステムのデータ交換方式 | |
JPS6332649A (ja) | マルチプロセツサシステム |