JPS63222454A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS63222454A JPS63222454A JP62055973A JP5597387A JPS63222454A JP S63222454 A JPS63222454 A JP S63222454A JP 62055973 A JP62055973 A JP 62055973A JP 5597387 A JP5597387 A JP 5597387A JP S63222454 A JPS63222454 A JP S63222454A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- semiconductor device
- chip
- support plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000011347 resin Substances 0.000 claims abstract description 7
- 229920005989 resin Polymers 0.000 claims abstract description 7
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置およびその製造方法に係り、特に
半導体素子の実装に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to mounting of semiconductor elements.
樹脂封止型の半導体装置は、通常、第５図に示す如く、
半導体集積回路（以下ＩＣ）等の作り込まれた半導体チ
ップ１を、リードフレーム２のダイパッド３上に搭載し
、ボンディングワイヤ４等によって結線した後、モール
ド用樹脂５による封止を経て完成せしめられる。A resin-sealed semiconductor device usually has the following structure, as shown in FIG.
A built-in semiconductor chip 1 such as a semiconductor integrated circuit (hereinafter referred to as IC) is mounted on a die pad 3 of a lead frame 2, connected with bonding wires 4, etc., and then sealed with a molding resin 5 to complete the process. .
近年、半導体テクノロジーのめざましい進歩と共に半導
体チップには、いろいろな機能を有するものが出現し、
チップサイズについても、多種多様のものが用いられる
ようになってきている。In recent years, with the remarkable progress of semiconductor technology, semiconductor chips with various functions have appeared.
A wide variety of chip sizes are also being used.
ところで、量産性の面から考えるとリードフレームは、
同種の物を多量に生産するのが望ましい。By the way, from the perspective of mass production, lead frames are
It is desirable to produce large quantities of similar products.
しかし、ダイパッド３の大きさに対し、これに載置する
半導体チップ１′が小さい場合、第６図に示す如く、ボ
ンディングワイヤ４がダイパッド３に接触し、短絡する
いわゆるパッドタッチ（ベッドタ゛ツチ）と呼ばれる不
良現象が発生することがある。However, if the semiconductor chip 1' placed on the die pad 3 is small compared to the size of the die pad 3, the bonding wire 4 comes into contact with the die pad 3, causing a short circuit, as shown in FIG. Defects may occur.
また、ダイパッドの大きさに対し、これに載置する半導
体チップが大き過ぎるとインナーリードの先端に接触す
る等の不都合が生じる。Furthermore, if the semiconductor chip placed on the die pad is too large relative to the size of the die pad, problems such as contact with the tips of the inner leads will occur.
このため、従来は、チップサイズに応じて、リードフレ
ームのダイパッドの大きさを決定しなければならず、こ
れがリードフレームの汎用性を阻害する原因の１つとな
っていた。For this reason, conventionally, the size of the die pad of the lead frame had to be determined according to the chip size, which was one of the causes of inhibiting the versatility of the lead frame.
そこで、ダイパッドを別体として形成し、チップサイズ
に応じてダイパッドのみを選択するという方法も提案さ
れている。Therefore, a method has also been proposed in which the die pad is formed separately and only the die pad is selected depending on the chip size.
しかしながら、リードフレームへの接続時において短絡
不良等が発生し易く、高精度の位置決めが必要である上
、信頼性が悪いという問題があった。However, there have been problems in that short circuits and the like are likely to occur when connecting to a lead frame, high precision positioning is required, and reliability is poor.
そこで、本発明の半導体装置では、封止用パッケージ内
で半導体チップが絶縁性の支持板を介してリードフレー
ム上に固着せしめられるようにしている。Therefore, in the semiconductor device of the present invention, the semiconductor chip is fixed on the lead frame within the sealing package via an insulating support plate.
また、本発明の方法では、半導体チップを絶縁性の支持
板に固着せしめ、この支持板をリードフレームの少なく
とも１本のインナーリードの先端に貼着し、ワイヤボン
ディングを行なった後、樹脂封止を行なうようにしてい
る。Further, in the method of the present invention, the semiconductor chip is fixed to an insulating support plate, this support plate is attached to the tip of at least one inner lead of the lead frame, wire bonding is performed, and then resin sealing is performed. I try to do this.
本発明の半導体装置によれば、半導体チップのチップサ
イズに応じて絶縁性の支持板の大きさを適宜選択するよ
うにすれば、チップサイズが変化しても、短絡等の不良
が発生することはない。According to the semiconductor device of the present invention, if the size of the insulating support plate is appropriately selected depending on the chip size of the semiconductor chip, defects such as short circuits will not occur even if the chip size changes. There isn't.
すなわち、いわゆるパッドタッチに近い現象が生じても
、ボンディングワイヤの接触部分は絶縁性の支持板であ
るため、短絡等の不良が生じることはない。That is, even if a phenomenon similar to a so-called pad touch occurs, defects such as short circuits will not occur because the contact portion of the bonding wire is an insulating support plate.
また、本発明の方法によれば、半導体チップは絶縁性の
支持板上に固着せしめられるため、チップサイズとダイ
パッドの大きさを一致させる必要はなく、汎用性が向上
する上従来のようにダイパッド上にダイボンディングす
る場合のように、高度の位置精度は不要となり、作業性
が高められる。Further, according to the method of the present invention, since the semiconductor chip is fixed on the insulating support plate, there is no need to match the chip size with the die pad size, which improves versatility and eliminates the need for the die pad as in the conventional method. Unlike the case of die bonding, a high degree of positional accuracy is not required, improving work efficiency.
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明実施例のメモリ用ＩＣを示す説明図、
第２図（ａ）および（ｂ）は、同メモリ用ＩＣの実装工
程の１部を示す説明図である。FIG. 1 is an explanatory diagram showing a memory IC according to an embodiment of the present invention;
FIGS. 2(a) and 2(b) are explanatory diagrams showing a part of the mounting process of the memory IC.
このメモリ用ＩＣは、第２図（ａ）に示すように、ダイ
パッドをもたず、所定数のインナーリード１０およびア
ウターリード１１を具えたリードフレーム１２のインナ
ーリード１０の先端部に、第１図に示す如くメモリ用Ｉ
Ｃの作り込まれた半導体チップ１３を搭載してなる耐熱
性の絶縁フィルム１４を裁置し、ボンディングワイヤ１
５によって半導体チップ１３上のボンディングパッド１
６とインナーリード１０との間を結線せしめられ、アウ
ターリード１１の１部を除いて全体が樹脂パッケージ１
７内に封止せしめられてなるものである。As shown in FIG. 2(a), this memory IC does not have a die pad and has a lead frame 12 having a predetermined number of inner leads 10 and outer leads 11. As shown in the figure, I for memory
A heat-resistant insulating film 14 on which a semiconductor chip 13 is mounted is placed, and a bonding wire 1 is attached.
Bonding pad 1 on semiconductor chip 13 by 5
6 and the inner lead 10, and the entire resin package 1 except for a part of the outer lead 11
7 and is sealed inside.
次に、このメモリ用ＩＣの製造方法について説明する。Next, a method of manufacturing this memory IC will be explained.
まず、第２図に（ａ）示す如く、ダイパッドをもたない
デュアルインライン（Ｄ Ｉ Ｌ）型ＩＣ用のリードフ
レーム１２を用意する。First, as shown in FIG. 2(a), a lead frame 12 for a dual in-line (DIL) type IC without a die pad is prepared.
そして、第２図（ｂ）に示す如く絶縁性フィルム１４上
に絶縁性の接着剤Ｂを介して半導体チップ１３を固着し
た後、前記リードフレームのインナーリード１０先端部
に絶縁性の接着剤Ｂを介してこの絶縁フィルム１４を貼
着する。Then, as shown in FIG. 2(b), after the semiconductor chip 13 is fixed onto the insulating film 14 via an insulating adhesive B, an insulating adhesive B is applied to the tip of the inner lead 10 of the lead frame. This insulating film 14 is attached via the.
この後、ワイヤボンディングによって半導体チップ１３
上の各ボンディングパッド１６とリードフレーム１２の
各インナーリード１０との間を接続する。After this, the semiconductor chip 13 is bonded by wire bonding.
Each upper bonding pad 16 and each inner lead 10 of the lead frame 12 are connected.
そして最後に、樹脂封止工程を経て、リードフレームの
タイバー１８を切除すると共に、アウターリードを所望
の形状に成型して完成せしめられる。Finally, through a resin sealing process, the tie bars 18 of the lead frame are cut out and the outer leads are molded into a desired shape to complete the process.
このようにして形成されたメモリ用ＩＣは、リードフレ
ームのダイパッドの有無あるいは寸法に関係なくパッド
タッチによる短絡不良もなく、極めて信頼性の高いもの
となっている。The memory IC thus formed has extremely high reliability, with no short-circuit failures caused by pad touching, regardless of the presence or absence of a die pad on the lead frame or its size.
更に、リードフレームの汎用性が高められチップサイズ
によって設計を変更することなくそのままのリードフレ
ームで、いろいろなチップサイズのＩＣチップに対応す
ることができる。Furthermore, the versatility of the lead frame is increased, and the lead frame can be used as is to accommodate IC chips of various chip sizes without changing the design depending on the chip size.
また、実装に際しては、ダイボンディング時における厳
密な位置合わせは不要となり作業性が向上すると共に、
位置ずれによる短絡等の不良もなく、信頼性が向上する
。In addition, during mounting, strict alignment during die bonding is not required, improving work efficiency and
There are no defects such as short circuits due to misalignment, and reliability is improved.
なお、実施例では、ダイパッドをもたないリードフレー
ム１２を用いたが、第３図に示す如くダイパッド２２ｂ
を存するリードフレーム１２を使用しダイパッド２２ｂ
を絶縁フィルム１４の支持に用いるようにしてもよい。In the embodiment, the lead frame 12 without a die pad was used, but as shown in FIG.
The die pad 22b is
may be used to support the insulating film 14.
また、第４図に示す如くインナーリード２０を１本おき
に長くし、長い方のインナーリードの先端で絶縁フィル
ム１４を支持するようにし、ボンディング位置を千鳥状
にすれば、ボンディングワイヤ同志の接触および短絡が
防止される。Furthermore, as shown in FIG. 4, if every other inner lead 20 is made longer and the insulating film 14 is supported by the tip of the longer inner lead, and the bonding positions are staggered, the bonding wires can come into contact with each other. and short circuits are prevented.
更に、絶縁性の支持板として絶縁フィルムを用いたが、
可撓性の材料に限定されることなく、剛性の薄板を用い
てもよいことはいうまでもない。Furthermore, an insulating film was used as an insulating support plate, but
Needless to say, the material is not limited to a flexible material, and a rigid thin plate may be used.
以上説明してきたように、本発明の半導体装置によれば
、対土用パッケージ内で、半導体・チップが絶縁性の支
持板を介してリードフレーム上に固着せしめられている
ため、半導体チップのチップサイズとリードフレームの
ダイパッドのサイズとの差による短絡等の不良が防止さ
れ信頼性が向上する。As explained above, according to the semiconductor device of the present invention, since the semiconductor/chip is fixed on the lead frame via the insulating support plate in the earth-bound package, the semiconductor chip Defects such as short circuits due to the difference between the size and the size of the die pad of the lead frame are prevented, and reliability is improved.
また、本発明の方法によれば、半導体チップを絶縁性の
支持板に固着せしめ、この支持板をリードフレームの少
なくとも１本のインナーリードの先端部に貼着するよう
にしているため、チップサイズに左右されることなくリ
ードフレームを使用することができるためリードフレー
ムの汎用性が大幅に高められる。Further, according to the method of the present invention, the semiconductor chip is fixed to an insulating support plate, and this support plate is attached to the tip of at least one inner lead of the lead frame, so that the chip size Since the lead frame can be used regardless of the conditions, the versatility of the lead frame is greatly increased.
【図面の簡単な説明】
第１図は、本発明実施例のメモリ用ＩＣを示す図、第２
図（ａ）および（ｂ）は、同メモリ用ＩＣの製造工程の
１部を示す図、第３図および第４図は、夫々、本発明の
他、の実施例を示す図、第５図は、従来の半導体装置を
示す図、第６図は、従来の半導体装置における不良現象
を示す図である。
１．１′・・・半導体チップ、２・・・リードフレーム
、３・・・ダイパッド、４・・・ボンディングワイヤ、
５・・・対土用樹脂、１０・・・インナーリード、１１
・・・アウターリード、１２・・・リードフレーム、１
３・・・半導体チップ（メモリ用ＩＣチップ）、１４・
・・絶縁フィルム、１５・・・ボンディングワイヤ、１
６・・・ボンディングパッド、１７・・・封止用パッケ
ージ、１８・・・タイバー。
第１図
第２図（Ｑ） 第２図（ｂ）第３図
第４図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing a memory IC according to an embodiment of the present invention, and FIG.
Figures (a) and (b) are diagrams showing a part of the manufacturing process of the same memory IC, Figures 3 and 4 are diagrams respectively showing other embodiments of the present invention, and Figure 5 is a diagram showing a part of the manufacturing process of the memory IC. 6 is a diagram showing a conventional semiconductor device, and FIG. 6 is a diagram showing a failure phenomenon in the conventional semiconductor device. 1.1'... Semiconductor chip, 2... Lead frame, 3... Die pad, 4... Bonding wire,
5... Resin for soil, 10... Inner lead, 11
... Outer lead, 12 ... Lead frame, 1
3... Semiconductor chip (memory IC chip), 14.
... Insulating film, 15 ... Bonding wire, 1
6... Bonding pad, 17... Sealing package, 18... Tie bar. Figure 1 Figure 2 (Q) Figure 2 (b) Figure 3
Figure 4
Claims (4)
に、前記半導体チップ上に形成されたボンディングパッ
ドとリードフレームのインナーリードとを接続してなる
半導体装置において、 前記半導体チップは、絶縁性の支持板を介してリードフ
レーム上に固着せしめられるようにしたことを特徴とす
る半導体装置。(1) In a semiconductor device in which a semiconductor chip is mounted on a lead frame and bonding pads formed on the semiconductor chip are connected to inner leads of the lead frame, the semiconductor chip is mounted on an insulating support plate. 1. A semiconductor device characterized in that it can be fixed onto a lead frame via.
あることを特徴とする特許請求の範囲第（１）項記載の
半導体装置。(2) The semiconductor device according to claim (1), wherein the insulating support plate is a heat-resistant insulating film.
すように形成されており、長い方のインナーリードの先
端に前記支持板が固着せしめられるようにしたことを特
徴とする特許請求の範囲第（１）項又は第（２）項記載
の半導体装置。(3) The inner lead is formed such that the tips are alternately long and short, and the support plate is fixed to the tip of the longer inner lead. The semiconductor device according to item (1) or item (2).
とも１本の先端に絶縁性の支持板を介して半導体チップ
を固着し、リードフレーム組立構体を形成するマウント
工程と、 前記半導体チップと前記インナーリードとを電気的に接
続するワイヤボンディング工程と、前記リードフレーム
組立構体に、樹脂封止を施すモールド工程とを含むこと
を特徴とする半導体装置の製造方法。(4) a mounting step of fixing a semiconductor chip to the tip of at least one of the inner leads of the lead frame via an insulating support plate to form a lead frame assembly structure; A method for manufacturing a semiconductor device, comprising: a wire bonding step for electrically connecting the lead frame assembly; and a molding step for applying resin sealing to the lead frame assembly structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62055973A JPS63222454A (en) | 1987-03-11 | 1987-03-11 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62055973A JPS63222454A (en) | 1987-03-11 | 1987-03-11 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63222454A true JPS63222454A (en) | 1988-09-16 |
Family
ID=13014018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62055973A Pending JPS63222454A (en) | 1987-03-11 | 1987-03-11 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63222454A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS6016754A (en) * | 1983-07-09 | 1985-01-28 | Akira Ishikawa | Timer telephone automatic service machine |
| JPS60167454A (en) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | Semiconductor device |
| JPS6112095A (en) * | 1984-06-27 | 1986-01-20 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPS61258458A (en) * | 1985-05-13 | 1986-11-15 | Hitachi Ltd | Resin-sealed ic |
-
1987
- 1987-03-11 JP JP62055973A patent/JPS63222454A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105970A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Assembling method for semiconductor device |
| JPS6016754A (en) * | 1983-07-09 | 1985-01-28 | Akira Ishikawa | Timer telephone automatic service machine |
| JPS60167454A (en) * | 1984-02-10 | 1985-08-30 | Hitachi Ltd | Semiconductor device |
| JPS6112095A (en) * | 1984-06-27 | 1986-01-20 | 日本電気株式会社 | Hybrid integrated circuit device |
| JPS61258458A (en) * | 1985-05-13 | 1986-11-15 | Hitachi Ltd | Resin-sealed ic |
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