JPS63221677A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To simplify manufacturing steps and to improve the yield of a thin film transistor by deciding the channel length of an enhancement type transistor to a specific value or more and the channel length of a depletion type transistor to other specific value or less, and simultaneously forming both types of transistors. CONSTITUTION:An Al-Ta-O layer is formed by a sputtering method as a gate insulating film 3 covered on part or all of a gate electrode 2 formed on a glass substrate 1, and a CdSe layer 4 is formed, for example, by a resistance heating evaporation method. Then, an aluminum layer is formed as source, drain electrodes 4 on a region which partly contains the layer 4. When a depletion type transistor is formed in the electrode forming steps, a distance between the drain electrode and the source electrode, i.e., a channel length La is set to 20mum or longer, while when the enhancement type transistor is formed, a channel length Lb is set to 10mum or less. Then, a heat treatment is, for example, conducted in vacuum. Accordingly, both the depletion type and the enhancement type can be simultaneously formed. Since a photolithography method is used, the channel length has preferable reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a thin film transistor having uniform characteristics over a large area and used in a drive circuit for a display device, such as an electroluminescent display.

BACKGROUND ART Conventionally, the case where an electric circuit is manufactured using CdS·-TPT will be explained in detail using an inverter which is one of the basic circuits. FIG. 2 can be considered as an example of the configuration of an inverter. Of these, 0-MO in Figure 2 a
The S-type is difficult because it is difficult to produce a P-type CaS film. When both the load transistor and the driver transistor are configured with enhancement type transistors as shown in FIG.

This has many problems in terms of deterioration of Ca5e-TPT, and also requires only one power supply (V,
extra is needed.

If a depletion type transistor is used as the load transistor of C, and an enhancement type transistor is used as the driver transistor, it is advantageous compared to B in terms of deterioration of the load transistor, but once the enhancement type transistor is used. After that, it was necessary to form a depletion type transistor in which only a predetermined TPT is not doped with impurities.

Problems to be Solved by the Invention When creating an electric circuit using edge-TPT,
It is not possible to form a depletion type transistor and an enhancement type transistor at the same time, and once an enhancement type transistor is made, it is necessary to dope only the TPT with impurities to make it a depletion type. For this reason, the process of forming a circuit using TPT becomes complicated and causes a decrease in yield.
Reproducibility was also poor because it required the addition of very small amounts of impurities.

In order to solve this problem, the present invention provides a backtrack method for thin film transistors that can simultaneously form a depletion type transistor and an enhancement type transistor.

Means for Solving the Problems The present invention provides that when an electric circuit is manufactured using C(Is thin film transistors), the channel length of the enhancement type transistor is set to 20 μm or more, and the channel length of the depletion type transistor is set to 10 μm or less. By this, an enhancement type transistor and a depletion type transistor are formed at the same time.

The working depletion mode transistor has a channel length of 1
By setting the channel length to 0 μm or less and the enhancement type transistor to 20 μm or more, both a depletion type transistor and an enhancement type transistor can be manufactured at the same time in one TPT manufacture.

Furthermore, since the photolithography method is used, the channel length has good reproducibility. Therefore, the reproducibility of the enhancement type depletion type transistor is also improved.

Embodiments Below, embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 1a and 1b, a layer having a predetermined shape and a film thickness of approximately sonm is formed on a glass substrate 1 by a resistance heating evaporation method or the like to form a gate electrode 2. . next,
As the gate insulating film 3 having a shape that covers part or all of the gate electrode 2, an ao-oxide film formed by, for example, a sputtering method is used.
A 1-Ta-0 layer with a thickness of about 1.0 oz. is formed, and a semiconductor layer with a thickness of about 5 oz. The CaSO layer 4 having the following properties is formed by, for example, a resistance heating evaporation method. Next, a layer 1 is formed as a source/drain electrode 6 in a region partially including the edge layer 4. In this source/drain electrode formation process, when forming a depletion type transistor, the distance between the drain and source electrodes, that is, the channel length, is set to 20 μm or more, as shown in Figure 1a, and the enhancement type transistor is formed. In this case, the channel length is set to 10 μm or less as shown in FIG. Thereafter, heat treatment is performed at 300'C for 1 hour in a vacuum, for example.

c when the channel length is 10μFff, 20/jFFj
The static characteristics of the ase thin film transistor are shown in FIGS. 4IL and b, respectively.

As is clear from Fig. 4, when the channel length is 10 μm, the threshold voltage vth is approximately -2V, which is a depression type, and when the channel length is 20 μm, the threshold voltage vth
It can be seen that the voltage is approximately 3V, indicating enhancement type characteristics.

In addition, Fig. 3 shows case ・TPT channel length and T
It shows the relationship between the threshold voltage vth of PT. As is clear from the figure, when the channel length becomes short to 10 μm or less, the characteristics of caseφTPT change from enhancement type to depletion type.

Effects of the invention In producing an electric circuit using C+ISe@TPT,
Since depletion-type transistors and enhancement-type transistors can be manufactured simultaneously, the detonation process can be simplified and yields can be improved.Also, since the channel length of thin film transistors is determined using photophosphorography, reproducibility can be improved. Therefore, the reproducibility of enhancement type and depletion type transistors is also improved compared to conventional ones.

[Brief explanation of the drawing]

FIG. 1 (IL), (1)) is a cross-sectional view of a depression type thin film transistor according to the present invention, and FIG. 2 (IL)
, (t)), (0) is a circuit diagram of an enhancement type thin film transistor, Fig. 3 is a diagram showing the relationship between channel length and threshold voltage vth of a thin film transistor, and Fig. 4 (&) is a depletion type thin film transistor according to the present invention. FIG. 4(b) is a static characteristic diagram of the enhancement type thin film transistor according to the present invention. 1... Glass substrate, 2... Gate insulating film, 4... Case layer. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
Ichiriki-ras 1i anti? -Click the gate ]a;x
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+ jaiK4-CdSεbrow5--source, drain th T3-engine HA〉sumesito type MQS T4-engineer〉ha〉fument 1 giant MQS Ts -? 7LA, Shin-type M□, 3 7≧--Enginnojisume〉Tota bar MO, SV. Figure 3

Claims (1)

[Claims] The channel length of the enhancement type transistor is 20
A method for manufacturing a thin film transistor, characterized in that an enhancement type transistor and a depletion type transistor are formed at the same time by setting the channel length of the depletion type transistor to 10 μm or more.