JP2000332258A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT, capable of suppressing a rise in the temperature of a substrate due to ion implantation. SOLUTION: This method of manufacturing a thin-film transistor comprises the steps of forming an insulating protective film 11 made of an SiO2 film on a glass substrate 10, forming an active layer 12 made of a p-Si film 12 thereon, a lower first gate insulating film 13 made of an SiN film and an upper second gate insulating film 14 made of an SiN film thereon, removing the film 14 in part or in whole using an upper gate electrode 15 as a mask. Since ion implantation is conducted only through the film 13, the ion implantation can be effected as far as to the film 12 with low accelerated energy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art In recent years, active matrix type LCDs have been developed.
(Thin Film Transi) using a p-Si film formed on a transparent insulating substrate as an active layer as a pixel driving element of a (Liquid Crystal Display) device
stor, hereinafter referred to as “TFT”. ) Is under development.

[0003] Poly-silicon TFT (Poly-Silicon Thi)
n Film Transistor: Hereinafter, referred to as “p-SiTFT”. ) Is an amorphous silicon thin film (Amorphous Silicon Thin Film: hereinafter, using an amorphous silicon film as an active layer).
This is referred to as “a-SiTFT”. ) Has the advantage that the electric field mobility is large and the driving capability is high.
Using an iTFT, a high-performance LCD can be realized,
Not only the pixel portion but also the peripheral driver circuit can be integrally formed over the same substrate.

In such a p-Si TFT, a heat treatment is performed to activate the p-Si film as an active layer after forming the source and drain regions in the p-Si film by performing ion implantation in both regions. ing.

Hereinafter, a conventional method of manufacturing a TFT will be described.

FIG. 4 is a sectional view of a TFT manufactured by a conventional TFT manufacturing method.

As shown in FIG. 1, a first gate insulating film 13 made of a SiO ₂ film and a second gate insulating film 14 made of a SiN film formed thereon are formed on the entire surface of the substrate including the p-Si film 12. Is formed.

FIG. 5 is a sectional view showing a manufacturing process of a conventional TFT.

Step 1 (FIG. 5A): An SiO ₂ film 11 as an insulating protective film is formed on an insulating substrate 10 made of quartz glass, non-alkali glass, or the like by using a plasma CVD method. An a-Si film 12 is formed on the SiO ₂ film 11 by a plasma CVD method. And the a-Si
The surface of the film 12 is irradiated with a XeCl excimer laser beam while being scanned, an annealing process is performed, and the a-Si film 12 is melted and recrystallized to be reformed into a p-Si film 12, and then the p-layer which becomes an active layer -The Si film 12 is island-etched.

Step 2 (FIG. 5B): A first gate insulating film 13 made of a SiO ₂ film and a second gate insulating film 14 made of a SiN film are formed on the p-Si film 12 by CVD.
Is formed on the entire surface. On the SiN film 14, chrome (C
r), a conductive material made of a high melting point metal such as molybdenum (Mo) is formed by sputtering, and the gate electrode 15 is overlapped with the semiconductor film 12 by photolithography and dry etching by RIE. To form

Then, using the gate electrode 15 as a mask,
First and second gate insulating films 1 for p-Si film 12
P-type or N-type ion implantation 16 is performed through 3 and 14. This ion implantation 16 implants P-type or N-type impurity ions into the p-Si film 12 not covered with the gate electrode 15 depending on the type of TFT to be formed. Thus, the p-Si film 12 below the gate electrode 15 becomes an intrinsic or substantially intrinsic p-Si film 12.

Step 3 (FIG. 5C): A resist 17 that covers the gate electrode 15 and the second insulating film 14 is formed to have a width smaller than that of the p-Si film 12. Then, this resist 17
Implantation 18 is performed using the mask as a mask. Thus, a region in which impurity ions are implanted at a low concentration, so-called LDD
(Lightly Doped Drain) region 12LD and regions into which impurity ions are implanted at a high concentration, that is, source 12s and drain 12d are formed.

As a result, the p-
In the Si film 12, the channel 12 is located immediately below the gate electrode 15.
c, and the portions on both sides of the gate electrode become the source 12s and the drain 12d.

Step 4 (FIG. 5D): After removing the resist 17, a SiN film 19 and a SiO ₂ film 20 are formed on the entire surface of the substrate 10 including the p-Si film 12 by plasma CVD.
Are sequentially laminated by using the SiN film 19 and the SiO ₂ film 2.
A two-layered interlayer insulating film is formed.

After forming the SiN film 19 and the SiO ₂ film 20, a first contact hole 3 penetrating the interlayer insulating film at a position corresponding to the source 12s and the drain 12d.
0 is formed so as to reach the p-Si film 12, and a source electrode 21 and a drain electrode 22 made of a metal such as aluminum are formed in the first contact hole 30. Further, a planarizing insulating film 2 made of an organic resin or the like is further formed thereon.
3 is deposited. Then, a contact hole 32 is formed at a position corresponding to the source electrode 21 in the planarization insulating film 23, and ITO as a transparent electrode material is deposited and patterned to form a display electrode 24.

As described above, a TFT using a p-Si film
Has an advantage such as high electric field mobility, but has crystal defects at its crystal grain boundaries, so that electrons traveling in the film are easily trapped. In particular, it is not preferable that such crystal defects exist in the channel portion of the TFT. Therefore, it has been considered that hydrogen is introduced into the film to terminate the ring ring bond existing in the defect with the hydrogen. As a method of introducing hydrogen into the p-Si film, the SiN film containing a large amount of hydrogen ions and the p-Si film are heated together to transfer hydrogen ions from the SiN film to the p-Si film. Are known.

Here, in order to supply hydrogen (H) atoms in the SiN film 14 to the p-Si film 12 by heat treatment,
Preferably, the SiN film 14 is as close as possible to the p-Si film 12.

However, when the p-Si film 12 and the SiN film 14 are in direct contact with each other, the threshold value of the TFT using the p-Si film 12 fluctuates due to fixed charges generated in the SiN film 14. And therefore the top gate T as described above
In the FT, the SiN film 14 cannot be provided directly on the p-Si film 12 as a gate insulating film. Therefore, FIG.
As shown in FIG. 5, it is necessary to provide an SiN film 14 as an upper layer in which the SiO ₂ film 13 is provided on the p-Si film 12. Then, the gate insulating film preferably has a two-layer structure.

[0019]

However, when the gate insulating film of the top gate TFT has the two-layer structure of the SiO ₂ film 13 and the SiN film 14 in order from the lower layer as described above, when ion implantation is performed on the semiconductor film, The acceleration energy of the ion implantation must be increased so as to pass through the two gate insulating films and reach the p-Si film 12. For example, when phosphorus (P) is implanted, it must be implanted with an acceleration energy of 100 keV or more. for that reason,
There is a disadvantage that the power consumption of the injection device increases.

If the acceleration energy for ion implantation is increased, the substrate temperature at the time of implantation becomes approximately 200 ° C. In this case, the temperature of the resist 17 covering the gate electrode 15 and the LDD formation region deteriorates due to the temperature, for example, the periphery thereof is distorted, or the resist 17 is hardly peeled off when removing the resist after ion implantation. was there.

Accordingly, the present invention has been made in view of the above-mentioned conventional drawbacks, and is intended to manufacture a TFT capable of suppressing an increase in substrate temperature that occurs when ion implantation is performed with high acceleration energy. The aim is to provide a method.

[0022]

According to the method of manufacturing a TFT of the present invention, a semiconductor film, a first gate insulating film, a second
A method of manufacturing a thin film transistor, comprising sequentially forming a gate insulating film and a gate electrode, wherein the second gate insulating film on the first gate insulating film is partially or entirely removed by etching using the gate electrode as a mask. Is what you do.

Further, in the above-described method of manufacturing a TFT, after partially or entirely removing the second gate insulating film by etching, ions are further implanted into the semiconductor film using the gate electrode as a mask. T to be heated later
It is a manufacturing method of FT.

Further, the above-described method for manufacturing a TFT is a method for manufacturing a TFT in which the first gate insulating film is a silicon oxide film and the second gate insulating film is a silicon nitride film.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a TFT according to the present invention will be described.

FIG. 1 shows a sectional view of a TFT formed by the present invention.

As shown in the drawing, the point different from the TFT manufactured by the conventional method of manufacturing a TFT is that the second gate insulating film 14 made of the SiN film is etched using the gate electrode 15 as a mask, and the other portions than the gate electrode 15 are formed. The point is that the SiN film is not provided in the region of FIG.

FIG. 2 is a sectional view showing a manufacturing process of the TFT of the present invention.

Step 1 (FIG. 2A): An SiO ₂ film 11 as an insulating protective film is formed on an insulating substrate 10 made of quartz glass, non-alkali glass or the like by using a plasma CVD method. An a-Si film 12 is formed on the SiO ₂ film 11 by a plasma CVD method. And the a-Si
The surface of the film 12 is irradiated with a XeCl excimer laser beam while being scanned, an annealing process is performed to melt and recrystallize the a-Si film 12 so that the p-Si film 12 is modified. Is etched into islands. This p-S
The i film 12 becomes an active layer of the p-Si TFT.

Step 2 (FIG. 2B): A first gate insulating film 13 made of a SiO ₂ film and a second gate insulating film made of a SiN film are formed on the p-Si film 12 by CVD. 1
4 is formed on the entire surface. On the second gate insulating film 14, C
A conductive material made of a high melting point metal such as r or Mo is formed by a sputtering method, and a gate electrode 15 is formed so as to overlap with the semiconductor film 12 by a photolithography technique and a dry etching technique by an RIE method. At the same time as the formation of the gate electrode 15, a gate signal line connected to the gate electrode and supplying a gate signal is also formed (not shown).

Step 3 (FIG. 2C): Using the gate electrode 15 as a mask, the second insulating film 14 is removed by etching, leaving the second insulating film 14 only under the gate electrode 15. Then, P-type or N-type ion (impurity) implantation 16 is performed on the p-Si film 12. This ion implantation 16
Is the gate electrode 1 depending on the type of TFT to be formed.
5 and p-Si film 1 not covered by second insulating film 14
2 is implanted with P-type or N-type impurity ions. Therefore, the p-Si film 12 below the gate electrode 15 is an intrinsic or substantially intrinsic p-Si film 12 without impurity ions being implanted.

Step 4 (FIG. 2D): The gate electrode 15 and the second insulating film 14 have a smaller width than the p-Si film 12.
Is formed. Thereafter, ion implantation 18 is performed using the resist 17 as a mask. Thus,
A region in which impurity ions are implanted at a low concentration, so-called LD
A D (Lightly Doped Drain) region 12LD and regions into which impurity ions are implanted at a high concentration, that is, a source 12s and a drain 12d are formed.

Here, by heating at about 400 ° C. for 2 hours, the implanted impurities are activated and the
The hydrogen atoms in the SiN film, which is the gate insulating film 14 of FIG.
Hydrogenation can be achieved by being introduced into the Si film.

As a result, the p-
In the Si film 12, the channel 12 is located immediately below the gate electrode 15.
c, and the portions on both sides of the gate electrode 15 become the source 12s and the drain 12d.

When a P-channel type TFT is formed, P-type ions such as boron (B) are implanted. When an N-channel type TFT is formed, N-type ions such as phosphorus (P) are used.
Implant type ions.

Step 5 (FIG. 2E): After removing the resist 17, an SiN film 19 and a SiO ₂ film 20 are formed on the entire surface of the substrate 10 including the p-Si film 12 by plasma CVD.
Are sequentially laminated by using the SiN film 19 and the SiO ₂ film 2.
A two-layered interlayer insulating film is formed. After forming the SiN film 19 and the SiO ₂ film 20,
Heat for about an hour. By doing so, hydrogen ions are introduced into the p-Si film 12 from the SiN film in the interlayer insulating film, and hydrogenation can be achieved.

Thereafter, the source 12s and the drain 12d
Forming a first contact hole 30 penetrating the interlayer insulating film at a position corresponding to the p-Si film 12;
A source electrode 21 and a drain electrode 22 made of a metal such as aluminum are provided in the first contact hole 30.
To form Further, a flattening insulating film 23 made of an organic resin or the like is deposited thereon. Then, the planarizing insulating film 23
Contact hole 3 at a position corresponding to source electrode 21 of FIG.
Then, ITO as a transparent electrode material is deposited thereon and patterned to form the display electrode 24. Thus,
A p-Si TFT as a semiconductor element is formed.

As described above, the lower first gate insulating film 13 made of the SiO ₂ film and the upper second gate insulating film 13 made of the SiN film are used.
And the second gate insulating film 14 is removed by etching using the gate electrode 15 as a mask, and ion implantation is performed only through the first gate insulating film 13. The implantation can be performed up to the p-Si film 12.

In the ion implantation for forming the LDD formation region, the ion implantation can be performed at an acceleration energy at which the resist covering the LDD formation region does not deteriorate.

Therefore, the power consumption of the ion implantation apparatus can be suppressed, and the deterioration of the resist at the time of ion implantation can be prevented.

In the above-described embodiment, the second
In the above description, the gate insulating film 14 is etched and entirely removed except under the gate electrode so as to have almost the same shape as the gate electrode 15. However, the second gate insulating film 14 is completely removed. Instead, a part of the thickness of the insulating film 14 may be left.

FIG. 3 is a sectional view showing a manufacturing process of another embodiment.

FIG. 3 differs from FIG. 2 in that the second gate insulating film 14 has a partial thickness not only under the gate electrode 15 but also in other regions. Other structures and manufacturing steps are the same as those shown in FIGS.

Here, the thickness of the gate insulating film 14 left by the etching is determined by the source 12s and the drain 12d.
It is sufficient if the thickness is such that impurity ions can be implanted into the substrate.
For example, a thickness of 400 °
Make it 200Å. The average is about 150 °. Further, it is preferable that the thickness is such that hydrogen ions contained in the SiN film in the interlayer insulating film can be sufficiently introduced even when heated at about 400 ° C. for 2 hours.

Further, by leaving a part of the gate insulating film 14, when heating at about 400 ° C. for 2 hours after ion implantation, hydrogen is removed from the SiN film of the second gate insulating film 14 covering the p-Si film 12. The ions can be easily introduced into the entire surface of the p-Si film.

By leaving a part of the second gate insulating film 14 in this way, sufficient ion implantation can be performed and the entire semiconductor layer can be covered with a dense SiN film. TFT can be prevented
Reliability can be improved.

In each embodiment, a-Si
Although the case where a p-Si film is obtained by irradiating a laser to the film to obtain an active layer has been described, the same effect can be obtained when the p-Si film is directly formed on the insulating protective film by the CVD method or the like. Can be

This insulating protective film is formed to prevent sodium ions and the like from entering the p-Si film when a glass substrate or the like is used as the substrate 10.
In the case of using a substrate without such intrusion of impurities, it is not necessary to use an insulating protective film. However, when the substrate is a substrate that does not exhibit insulating properties, it is necessary to form an insulating protective film.

In each embodiment, the source 1
The source electrode 21 is formed by filling Al into the contact hole 30 provided corresponding to the second electrode 2s.
Although the display electrode 24 made of ITO was formed in contact with No. 1, the present invention is not limited to this. The display electrode 24 may be formed by filling the contact hole 30 with ITO and directly contacting the source 12 s.

Further, in each of the embodiments, the deterioration of the resist for forming the LDD region has been described. However, in the case of a TFT having an n-type channel TFT and a p-type channel TFT on the same substrate, one type is used. In the case of a resist provided on the other type of TFT in order to prevent that ion from being implanted when performing ion implantation of
It is also possible to prevent peeling off after ion implantation.

Further, in order to improve the TFT characteristics, hydrogen atoms are supplied from the SiN film containing a large amount of hydrogen atoms to the p-Si film by heating.
What is necessary is just to supply to the channel in the -Si film. this is,
Since the LD region 12LD, the source 12s, and the drain 12d are doped with impurities, the effect on the conductivity of the dangling bond in the p-Si film is small, but the p-Si
The channel region of the film is substantially intrinsic, and if dangling bonds in the film are not terminated in this region, T
This is because it greatly affects the operation characteristics of the FT. Therefore, according to the present invention, the Si remaining only under the gate electrode
Hydrogen atoms can be supplied more efficiently than the N film.

[0052]

According to the method of manufacturing a TFT of the present invention, it is possible to provide a method of manufacturing a TFT capable of suppressing an increase in substrate temperature that occurs when performing ion implantation.

[Brief description of the drawings]

FIG. 1 shows a TFT manufactured by the method for manufacturing a TFT of the present invention.
FIG.

FIG. 2 is a sectional view of a manufacturing process according to the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a TFT manufactured by a conventional TFT manufacturing method.

FIG. 5 is a sectional view of a conventional manufacturing process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 insulating substrate 11 insulating protective film 12 semiconductor film 12 s source 12 d drain 12 c channel 13 first gate insulating film 14 second gate insulating film 15 gate electrode 16 ion implantation 17 resist 18 ion implantation 19 first interlayer insulating film Reference Signs List 20 second interlayer insulating film 21 source electrode 22 drain electrode 23 planarizing insulating film 24 display electrode

Claims (3)

[Claims] 1. A method for manufacturing a thin film transistor, comprising: forming a semiconductor film, a first gate insulating film, a second gate insulating film, and a gate electrode on a substrate in this order, wherein the thin film transistor is formed using the gate electrode as a mask. A method for manufacturing a thin film transistor, characterized in that part or all of a second gate insulating film on the first gate insulating film is removed by etching. 2. The method according to claim 2, wherein after the second gate insulating film is partially or entirely removed by etching, ions are further implanted into the semiconductor film using the gate electrode as a mask, and heat treatment is performed after the ion implantation. The method for manufacturing a thin film transistor according to claim 1. 3. The method according to claim 1, wherein the first gate insulating film is a silicon oxide film, and the second gate insulating film is a silicon nitride film.