JPS63220583A - Submount - Google Patents
SubmountInfo
- Publication number
- JPS63220583A JPS63220583A JP62053019A JP5301987A JPS63220583A JP S63220583 A JPS63220583 A JP S63220583A JP 62053019 A JP62053019 A JP 62053019A JP 5301987 A JP5301987 A JP 5301987A JP S63220583 A JPS63220583 A JP S63220583A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- submount
- heat
- junctions
- glued
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 abstract description 19
- 238000009413 insulation Methods 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Led Device Packages (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置等に適用されるサブマウントに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a submount applied to semiconductor devices and the like.
［従来の技術］
■−ｖ族化合物半導体を材料とした半導体素子は、一般
に熱伝導率が小さい（例えば、ＧａＡｓでは０． １１
（ｃａｌ ７０ｗｔ−ｓ 争℃） 、Ｉ ｎＰでは０
、 １６ （ｃａｌ ／α・Ｓ・℃））ため、動作時の
温度上昇を防ぐべく発熱部（活性領域）から近い面に熱
伝導率の大きい材料からなるヒートシンクを接着してい
る。しかし、半導体素子の熱膨張係数とヒートシンクの
熱膨張係数が異なるため、両者を直接接着すると温度変
化によって素子に歪が加わり、活性領域での結晶欠陥の
発生等を招いて素子の信頼性の低下を引き起こす。そこ
で、一般に熱伝導率が大きくしかも熱膨張係数が素子材
料のものと近いような材質からなるサブマウントを半導
体素子とヒートシンク間に介在させることが行われてい
る。サブマウントの材質としてはシリコン、ダイヤモン
ド等があるが安価なシリコンが一般に使用されている。[Prior Art] ■-Semiconductor elements made of V group compound semiconductors generally have low thermal conductivity (for example, GaAs has a low thermal conductivity of 0.11
(cal 70wt-s), 0 for InP
, 16 (cal/α·S·°C)), a heat sink made of a material with high thermal conductivity is bonded to the surface near the heat generating part (active region) in order to prevent temperature rise during operation. However, since the coefficient of thermal expansion of the semiconductor element and that of the heat sink are different, if the two are directly bonded, the element will be strained due to temperature changes, causing crystal defects in the active region and reducing the reliability of the element. cause. Therefore, a submount made of a material having high thermal conductivity and a coefficient of thermal expansion close to that of the element material is generally interposed between the semiconductor element and the heat sink. Submount materials include silicon, diamond, etc., but silicon is generally used because it is inexpensive.
一方、例えば■−ｖ族化合物半導体を材料とする光半導
体素子を光送信器に搭載する場合、一般に素子のケース
を機器筐体と共にアースに接地する。このときに素子（
ダイオード特性を示す）の一方の電極がケースと導通し
ていると、使用電源の極性が限定されてしまう。従って
、使用の自由度を上げるには素子の両電極が素子ケース
（ヒートシンク）と絶縁されていることが必要である。On the other hand, when an optical semiconductor element made of, for example, a ■-v group compound semiconductor is mounted on an optical transmitter, the case of the element is generally grounded together with the device housing. At this time, element (
If one electrode of the diode (which exhibits diode characteristics) is electrically connected to the case, the polarity of the power source that can be used will be limited. Therefore, in order to increase the degree of freedom of use, it is necessary that both electrodes of the element be insulated from the element case (heat sink).
［発明が解決しようとする問題点］
シリコンからなるサブマウントを使用する場合、ケース
（ヒートシンク）と素子電極間の絶縁性をよくする（抵
抗が１００ＫΩ以上）ためには、比抵抗１０４Ωｃｍの
シリコンを用いても断面積１ｍｍ２の場合、厚さ１ ｍ
ｍ以上のものにする必要がある。その結果、素子からヒ
ートシンクまでの距離が大きくなり放熱性が悪くなる。[Problems to be solved by the invention] When using a submount made of silicon, in order to improve the insulation between the case (heat sink) and the element electrodes (resistance is 100KΩ or more), silicon with a specific resistance of 104Ωcm should be used. Even if used, if the cross-sectional area is 1 mm2, the thickness is 1 m
It is necessary to make it more than m. As a result, the distance from the element to the heat sink increases, resulting in poor heat dissipation.
また、高抵抗のシリコンウェハは高価である問題もある
。Another problem is that high-resistance silicon wafers are expensive.
本発明は、かかる点に鑑みてなされたものであり、熱伝
導性、絶縁性に優れ、しかも薄肉で放熱性に優れたサブ
マウントを提供するものである。The present invention has been made in view of these points, and provides a submount that is excellent in thermal conductivity and insulation, is thin, and has excellent heat dissipation.
［問題点を解決するだめの手段］
本発明は、放熱体の片面を素子貼着面とし、反対側の他
面をヒートシンク貼着面とするサブマウントにおいて、
素子貼着面から所定の深さの放熱対部分に該素子貼着面
と略平行に第１ＰＮ接合を有し、かつ、ヒートシンク貼
着面から所定の深さの放熱体部分に該ヒートシンク貼着
面と略平行に第２ＰＮ接合を有すると共に、該第１．第
２のＰＮ接合によって互に逆のダイオード特性を有する
ダイオードが形成されていることを特徴とするサブマウ
ントである。[Means for Solving the Problems] The present invention provides a submount in which one side of a heat sink is an element attachment surface, and the other surface on the opposite side is a heat sink attachment surface.
A first PN junction is provided approximately parallel to the element attachment surface at a heat dissipation pair portion at a predetermined depth from the element attachment surface, and the heat sink is attached to a heat sink portion at a predetermined depth from the heat sink attachment surface. A second PN junction is provided substantially parallel to the first . This submount is characterized in that diodes having mutually opposite diode characteristics are formed by the second PN junction.
［作用］
本発明に係るサブマウントによれば、放熱体内に１組の
逆向きのＰＮ接合を有するので、その祠質の熱伝導性を
十分に発揮させて、しかも、絶縁性に優れるため、薄肉
にして放熱効果を十分に高めることができる。その結果
、このサブマウントを適用することにより、温度特性、
信頼性に優れ、しかも、小型で安価な半導体装置を容易
に実現することができる。[Function] According to the submount according to the present invention, since it has a pair of reversely oriented PN junctions in the heat sink, the thermal conductivity of the abrasive material can be fully exhibited, and furthermore, it has excellent insulation properties. The heat dissipation effect can be sufficiently enhanced by making the wall thin. As a result, by applying this submount, the temperature characteristics,
A highly reliable, small, and inexpensive semiconductor device can be easily realized.
［実施例〕
以下、本発明の実施例について図面を参照して説明する
。第１図は、本発明に係るサブマウントを適用した半導
体装置の説明図である。図中１は、Ｃｕ、Ｆｅ等の金属
からなるステムである。ヒートシンク上には、半田層２
．サブマウント３．半田層４及び半導体素子５が順次積
層されている。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram of a semiconductor device to which a submount according to the present invention is applied. In the figure, 1 is a stem made of metal such as Cu or Fe. There is a solder layer 2 on the heat sink.
．． Submount 3. A solder layer 4 and a semiconductor element 5 are sequentially laminated.
ここで、サブマウント３は、第２図に示す如く、例えば
シリコンからなる放熱体６の素子貼着面及びヒートシン
ク貼着面から数μｍの深さのところまで、半導体素子５
の基板と反対導電型の不純物を導入し、１組の互に逆の
ダイオード特性を有する第１．第２のＰＮ接合７ａ、７
ｂを形成している。素子貼着面上及びヒートシンク貼着
面上には、半導体素子５及びヒートシンク１とのボンデ
ィング性を高めるために金等の金属層８が形成されてい
る。このように構成されたサブマウント３は、第３図に
示すような等価回路９を構成している。Here, as shown in FIG. 2, the submount 3 supports the semiconductor element 5 to a depth of several μm from the element attachment surface and the heat sink attachment surface of the heat sink 6 made of silicon, for example.
An impurity of a conductivity type opposite to that of the substrate is introduced to form a first substrate having a set of mutually opposite diode characteristics. Second PN junction 7a, 7
It forms b. A metal layer 8 such as gold is formed on the element adhesion surface and the heat sink adhesion surface in order to improve bonding properties between the semiconductor element 5 and the heat sink 1. The submount 3 configured in this manner constitutes an equivalent circuit 9 as shown in FIG.
なお、この場合、Ｎ基板（放熱体）にＰ型不純物を導入
しているが、夫々の接合７ａ、７ｂで形成されたダイオ
ードの逆方向ブレークダウン電圧は、放熱体６の比抵抗
及び接合を形成するための拡散不純物の濃度を制御する
ことにより所定のものに設定することができる。このた
め、半導体素子５の通常の動作時にサブマウント３の両
端に印加される電圧に対して十分な絶縁性を発揮させる
ことができる。In this case, although P-type impurities are introduced into the N substrate (heat sink), the reverse breakdown voltage of the diodes formed at the respective junctions 7a and 7b depends on the specific resistance of the heat sink 6 and the junction. By controlling the concentration of the diffusion impurity for formation, it can be set to a predetermined value. Therefore, sufficient insulation can be exhibited against the voltage applied to both ends of the submount 3 during normal operation of the semiconductor element 5.
このように構成された半導体装置は、サブマウント３が
極めて優れた熱伝導性、絶縁性及び放熱性を発揮するの
で、温度特性、信頼性に優れ、しかも、小型で安価なも
のとすることができる。Since the submount 3 exhibits extremely excellent thermal conductivity, insulation, and heat dissipation, the semiconductor device configured in this manner has excellent temperature characteristics and reliability, and can be made small and inexpensive. can.
［発明の効果］
以上説明した如く、本発明に係るサブマウントによれば
熱伝導性、絶縁性に優れ、しかも、薄肉で放熱性にも優
れる等顕著な効果を有するものである。[Effects of the Invention] As explained above, the submount according to the present invention has remarkable effects such as being excellent in thermal conductivity and insulation, and also having a thin wall and excellent heat dissipation.
【図面の簡単な説明】
第１図は、本発明に係るサブマウントを適用した半導体
装置の一実施例の説明図、第２図は、同サブマウントの
説明図、第３図は、同サブマウントの等価回路図である
。
１・・・ヒートシンク、２・・・半田層、３・・・サブ
マウント、４・・・半田層、５・・・半導体素子、６・
・・放熱体、７ａ、７ｂ・・・ＰＮ接合、８・・・金属
層、９・・・サブマウントの等価回路。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is an explanatory diagram of an embodiment of a semiconductor device to which a submount according to the present invention is applied, FIG. 2 is an explanatory diagram of the submount, and FIG. 3 is an explanatory diagram of the same submount. FIG. 3 is an equivalent circuit diagram of the mount. DESCRIPTION OF SYMBOLS 1... Heat sink, 2... Solder layer, 3... Submount, 4... Solder layer, 5... Semiconductor element, 6...
... Heat sink, 7a, 7b... PN junction, 8... Metal layer, 9... Equivalent circuit of submount.
Claims (1)
シンク貼着面とするサブマウトにおいて、素子貼着面か
ら所定の深さの放熱体部分に該素子貼着面と略平行に第
１ＰＮ接合を有し、かつ、ヒートシンク貼着面から所定
の深さの放熱体部分に該ヒートシンクク貼着面と略平行
に第２ＰＮ接合を有すると共に、該第１、第２のＰＮ接
合によって互に逆のダイオード特性を有するダイオード
が形成されていることを特徴とするサブマウント。In a sub-mount in which one side of the heat sink is an element attachment surface and the other side is a heat sink attachment surface, a groove is installed on the heat sink at a predetermined depth from the element attachment surface approximately parallel to the element attachment surface. 1 PN junction, and a second PN junction at a predetermined depth from the heat sink attachment surface in a portion of the heat sink approximately parallel to the heat sink attachment surface, and an interconnection between the first and second PN junctions. A submount characterized in that a diode having opposite diode characteristics is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62053019A JPS63220583A (en) | 1987-03-10 | 1987-03-10 | Submount |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62053019A JPS63220583A (en) | 1987-03-10 | 1987-03-10 | Submount |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63220583A true JPS63220583A (en) | 1988-09-13 |
Family
ID=12931188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62053019A Pending JPS63220583A (en) | 1987-03-10 | 1987-03-10 | Submount |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63220583A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103370779A (en) * | 2011-02-16 | 2013-10-23 | 奥斯兰姆奥普托半导体有限责任公司 | Carrier substrate and method for producing semiconductor chips |
-
1987
- 1987-03-10 JP JP62053019A patent/JPS63220583A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103370779A (en) * | 2011-02-16 | 2013-10-23 | 奥斯兰姆奥普托半导体有限责任公司 | Carrier substrate and method for producing semiconductor chips |
| JP2014506016A (en) * | 2011-02-16 | 2014-03-06 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Carrier substrate and method for manufacturing semiconductor chip |
| US9704945B2 (en) | 2011-02-16 | 2017-07-11 | Osram Opto Semiconductors Gmbh | Carrier substrate and method for producing semiconductor chips |
| US10224393B2 (en) | 2011-02-16 | 2019-03-05 | Osram Opto Semiconductors Gmbh | Method of producing semiconductor chips that efficiently dissipate heat |
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