JPH05327127A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To remarkably improve the thermal conductivity of a semiconductor element formed on an InP layer. CONSTITUTION:This semiconductor device is constituted so as to contain a semiconductor element formed in an indium phosphorus layer 4 which is formed on a silicon carbide layer 2 and thinner than said layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an element formed in an InP layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art Indium phosphide (InP) is a semiconductor laser,
It is used as a substrate for semiconductor light emitting devices such as light emitting diodes and transistors such as HEMTs and MISFETs.

For example, the InP MISFET is as shown in FIG.
Using a semi-insulating InP substrate 31, two n ⁺ type layers 33 and 34 separated by a groove 32 in the upper layer thereof, and a gate electrode 36 formed on the groove 32 via an Al ₂ O ₃ film 35.
And Au-G connected on the n ⁺ type layers 33 and 34, respectively.
The source electrode 37 and the drain electrode 38 are made of e.

In this case, as the InP substrate 31, an InP wafer having a thickness of about several hundreds of μm formed through processes such as slicing, grinding and polishing is used as it is as a device forming substrate.

[0005]

However, InP has a thermal conductivity of only 70 W / mK at room temperature, which is about half that of silicon. Therefore, there is a problem that the element cannot be cooled effectively and the degree of integration cannot be increased.

The present invention has been made in view of the above problems, and provides a semiconductor device capable of significantly improving the thermal conductivity of a semiconductor element formed in an InP layer, and a method of manufacturing the same. With the goal.

[0007]

The above-mentioned problems are solved by forming a semiconductor element on an indium phosphide layer 4 formed on the silicon carbide layer 2 and thinner than the silicon carbide layer 2, as illustrated in FIG. This is achieved by a semiconductor device characterized in that

Alternatively, as illustrated in FIG. 2, a step of forming an insulating film 23 on at least one surface of the SiC wafer 21 and the InP wafer 22; and a step of forming the insulating film 23 as a bonding surface to form the SiC wafer 21. This is achieved by a method of manufacturing a semiconductor device, which comprises a step of adhering the InP wafer 22 and a step of thinning the InP wafer 22 from the exposed surface side.

Alternatively, the SiC wafer 21 and the InP wafer 22
A step of applying an alcoholate liquid containing impurities on at least one surface of the SiC wafer 21 and the InP layer.
Bonding the wafer 22 and the InP wafer 22
And a step of thinning the exposed surface side from the exposed surface side.

Alternatively, in the step of adhering the SiC wafer 21 and the InP wafer 22, the SiC wafer 21
And a InP wafer 22 are applied with positive and negative pulse voltages.

[0011]

[Operation] According to the present invention, the SiC layer 2 (SiC wafer 2
Adhere a thin InP layer 4 (InP wafer 22) on 1),
A semiconductor element is formed on the InP layer 4 (InP wafer 22).

Therefore, as shown in FIG. 1, the heat generated by the operation of the device is conducted to the SiC layer 2 through the thin InP layer 4 and the insulating film 3 thereunder, and is transferred to the SiC layer 2. Are further emitted to the outside through a heat sink therebelow.

In this case, the thermal conductivity of SiC is three times that of InP,
At about 210W / mK, which is 1.5 times that of Si, heat is released more efficiently than when using the InP substrate as it is.
The cooling efficiency of the element formed in the P layer 4 is improved.

The coefficient of linear expansion of SiC is 4.6 × 10 ^-4.
/ K, which is almost the same as the linear expansion coefficient of InP of 4.5 × 10 ^-4 / K.
The InP wafer 22 is not stressed or cracked.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment of the Present Invention FIG. 1 (a) is a sectional view showing an embodiment of the present invention.

In FIG. 1A, reference numeral 1 is a substrate for forming a semiconductor device, which is a silicon carbide (SiC) layer 2 having a thickness of several hundreds μm and a film thickness of several tens nm laminated thereon. SO
Insulating layer 3 made of G, SiO ₂ or the like, and a thickness of 1 μ formed thereon
and an indium phosphide (InP) layer 4 of m or less.

Further, in the upper layer portion of the InP layer 4, two n ⁺ type layers 6 and 7 separated by the groove 5 and Al ₂ O on the groove 5 are formed.
A MISFET including a gate electrode 9 formed through the _three films 8, a source electrode 10 made of Au-Ge and a drain electrode 11 connected to each other on the n ⁺ type layers 6 and 7 is formed. There is.

In a semiconductor device having a plurality of such elements, heat generated by the operation of the elements is generated by the thin InP layer 4
Conducting to the SiC layer 2 through the
The heat transferred to the C layer 2 is the heat sink under it (not shown)
Is released to the outside via.

In this case, the thermal conductivity of the SiC layer 2 is the InP layer 4
3 times, about 210 W / m · K, which is more efficient than the case where the InP wafer is used as a substrate as it is, and the cooling efficiency of the element formed in the InP layer 4 is improved.

Next, a method of forming the above substrate will be described with reference to FIG. First, SiC wafer 21 and InP wafer 2
After polishing and flattening the surface of No. 2, as shown in FIG. 2 (a), an insulating film 23 such as SiO ₂ by the CVD method and SOG by the spin coating method is formed on the SiC wafer 21.
It is formed to a thickness of 000 nm. When the flatness of the insulating film 23 is not sufficient, the surface thereof is polished to improve the flatness.

Thereafter, as shown in FIG. 2B, the insulating film 23 and the InP wafer 22 are made to face each other, and In
After the P wafer 22 and the SiC wafer 21 are superposed on each other, they are heated to 600 to 900 ° C. to be bonded (FIG. 2 (c)).
In this case, if a pulse voltage of ± 100 to 300 V is applied between the wafers 21 and 22, the bonding becomes easier.

The coefficient of linear expansion of SiC is 4.6 × 10 ^-4.
/ K, which is almost the same as the linear expansion coefficient of InP of 4.5 × 10 ⁻⁴ / K, stress or cracking does not occur in the InP wafer 22 due to heating and cooling during bonding.

Since the insulating film 3 is extremely thin, its thermal conductivity and linear expansion coefficient can be ignored.
Next, the exposed surface of the InP wafer 22 is thinned to 1 μm or less by grinding, polishing, or etching.
Then, an element such as MISFET is formed on the InP layer 4 shown in FIG.

The surface on which the insulating film 23 is formed is not limited to the SiC wafer 21 side, and may be the InP wafer 22 side or the bonding surface of both wafers. (B) Description of Other Embodiments of the Present Invention In the above-mentioned embodiments, the insulating film 23 is formed on the bonding surface, but it is also possible to use one having electrode wiring formed therein. Further, instead of the insulating film 23, a polycrystalline silicon film formed by a CVD method may be used, or an alcoholate solution containing boron or phosphorus as impurities may be applied and adhered.

If the bonding surfaces of the SiC wafer 21 and the InP wafer 23 are sufficiently flat, these surfaces may be directly bonded and bonded by heating. Further, although the MISFET is formed in the InP layer 4 in the above-described embodiment, a pn junction diode or the semiconductor laser 12 as shown in FIG. 1B may be formed.

The semiconductor laser 21 shown in FIG. 1 (b) is made of Si.
The inverted mesa-shaped convex portion 14 formed on a part of the p-InP layer 4 formed on the C layer 2 via the insulating film 3, and the InGaAsP active layer 15 and the n- InP clad layer 1
6, the n-InP buried layer 17 formed on both sides of the position from the convex portion 14 to the lower part of the n-InP clad layer 16, and the upper surface of the clad layer 16 is reached from above the n-InP buried layer 17. And a p-InP buried layer 18 formed to a thickness. The buried layers 17 and 18 are pn junctions at the top and bottom. Also,
An n-electrode 13 is formed on the cladding layer 16, and
A p-electrode 19 is formed on the p-InP layer 13 on the sides of the buried layers 17 and 18.

[0027]

As described above, according to the present invention, SiC
Since a thin InP wafer is adhered on the wafer and semiconductor elements are formed on the InP wafer, the heat generated by the operation of the elements causes the thin InP wafer and the insulating film 3 below
The heat that is conducted to the SiC wafer through and is transmitted to the SiC wafer is released to the outside through the heat sink thereunder.

In this case, the thermal conductivity of SiC is about three times that of InP, so that heat can be released more efficiently than in the case of using the InP substrate as it is, and the cooling efficiency of the element formed on the InP wafer is improved. be able to.

Since the coefficient of linear expansion of SiC is almost the same as the coefficient of linear expansion of InP, it is possible to prevent stress and cracking of the InP wafer by heating and cooling during wafer bonding.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a side view showing a process of forming a substrate according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an example of a conventional device.

[Explanation of symbols]

1 substrate 2 SiC layer 3 insulating layer 4 InP layer 5 groove 6 n ⁺ layer 7 n ⁺ layer 8 Al ₂ O ₃ film 9 gate electrode 10 source electrode 11 drain electrode 21 SiC wafer 22 InP wafer 23 insulating film

Claims (4)

[Claims] 1. A semiconductor device characterized in that a semiconductor element is formed on an indium phosphide layer (4) formed on the silicon carbide layer (2) to be thinner than the silicon carbide layer (2). 2. A step of forming an insulating film (23) on at least one surface of the silicon carbide wafer (21) and the indium phosphide wafer (22), and the silicon carbide having the insulating film (23) as a bonding surface. Wafer (21) and the indium phosphide wafer (22)
And a step of thinning the indium phosphide wafer (22) from the exposed surface side, the method of manufacturing a semiconductor device. 3. A step of applying an alcoholate solution containing impurities to at least one surface of the silicon carbide wafer (21) and the indium phosphide wafer (22), and the application surface of the alcoholate solution being a bonding surface. A step of adhering the silicon carbide wafer (21) and the indium phosphide wafer (22) together, and a step of thinning the indium phosphide wafer (22) from the exposed surface side. Device manufacturing method. 4. In the step of adhering the silicon carbide wafer (21) and the indium phosphide wafer (22),
4. The method of manufacturing a semiconductor device according to claim 2, wherein a positive and negative pulse voltage is applied between the silicon carbide wafer (21) and the indium phosphide wafer (22).