JPS61234588A - Submount for optical semiconductor element - Google Patents
Submount for optical semiconductor elementInfo
- Publication number
- JPS61234588A JPS61234588A JP60077990A JP7799085A JPS61234588A JP S61234588 A JPS61234588 A JP S61234588A JP 60077990 A JP60077990 A JP 60077990A JP 7799085 A JP7799085 A JP 7799085A JP S61234588 A JPS61234588 A JP S61234588A
- Authority
- JP
- Japan
- Prior art keywords
- submount
- chip
- wire
- optical semiconductor
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ｎ型及びｐ型基板をもつ光半導体素子の実用
的パンケージの組立に共用できるサブマウントに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a submount that can be used commonly for assembling a practical pancage for optical semiconductor devices having n-type and p-type substrates.
第４図は例えば特開昭５８−８７８９２号に示された従
来のサブマウントを用いた光半導体素子の組立法を示し
、第４図（ａ）は従来法のサブマウントの例で、２は導
体からなるサブマウント ３はチップ接着部、４はワイ
ヤ接着部、７は絶縁体である。FIG. 4 shows a method for assembling an optical semiconductor device using a conventional submount, as disclosed in, for example, Japanese Patent Application Laid-Open No. 58-87892. FIG. 4(a) is an example of a conventional submount; A submount made of a conductor 3 is a chip bonding part, 4 is a wire bonding part, and 7 is an insulator.
第４図中）は第４図（ａ）のサブマウントを用いたレー
ザチップの組立法を示す図で、１はレーザチップ。4) is a diagram showing a method of assembling a laser chip using the submount of FIG. 4(a), and 1 is a laser chip.
６はステム、１１．１２はワイヤである。6 is a stem, and 11.12 is a wire.
次に動作について説明する。Next, the operation will be explained.
半導体レーザ（ＬＤ）、発光ダイオード（ＬＥＤ）等の
光半導体素子はステム（又はパッケージ）本体６の電気
的極性が正となるように決められている。従って第４図
の組立法では電流がサブマウント２．チップ１．ワイヤ
１１．ワイヤ１２の順に流れる。ワイヤ１２は負のリー
ド端子（図示せず）に接着される。Optical semiconductor elements such as semiconductor lasers (LDs) and light emitting diodes (LEDs) are determined so that the electrical polarity of the stem (or package) body 6 is positive. Therefore, in the assembly method shown in FIG. 4, the current flows from submount 2. Chip 1. Wire 11. The wires 12 flow in this order. Wire 12 is glued to a negative lead terminal (not shown).
従来の光半導体素子はｎ型又はｐ型の導電型を有する単
結晶基板上に結晶成長を行なうことによって形成される
。個々のチップの結晶の厚み構成としては、ＬＤの場合
一般に基板部公約１００μｍに対し、成長部分数μｍ程
度である。発光領域は結晶成長部分にあるので、基板側
を下にした場合、発光領域は上の方に来ることになる。Conventional optical semiconductor devices are formed by crystal growth on a single crystal substrate having n-type or p-type conductivity. In the case of an LD, the thickness of the crystal of each chip is generally about 100 μm in the substrate portion, while the thickness in the grown portion is approximately several μm. Since the light-emitting region is located in the crystal growth area, if the substrate side is placed down, the light-emitting region will be at the top.
チップをサブマウントに接着する方法には、基板側を下
にする（接着する）ジャンクションアップ（Ｊｕｎｃｔ
ｉｏｎｕｐ）法と、発光領域を下にするジャンクション
ダウン（Ｊｕｎｃｔｉｏｎ ｄｏｗｎ ）法がある。第
４図の組立法では、サブマウントが正でなければならな
いので、ｎ型基板を用いたチップではジャンクションダ
ウンＵｕｎｃｔｉｏｎ ｄｏｗｎ ）法、ｐ型基板を用
いたチップではジャンクションアップ（Ｊｕｎｃｔｉｏ
ｎ ｕｐ ）法しか採用することができない。The method of bonding the chip to the submount includes junction up (bonding) with the board side facing down.
There are two methods: an ion up method and a junction down method in which the light emitting region is placed at the bottom. In the assembly method shown in Figure 4, the submount must be positive, so the junction down method is used for chips using an n-type substrate, and the junction up method is used for chips using a p-type substrate.
n up ) method can only be adopted.
ジャンクションダウン（Ｊｕｎｃｔｉｏｎ ｄｏｗｎ
）法では発光領域の放熱性がよくなる一方、発光点がチ
ップ下方にあるので、接着時に発光領域にハンダが付着
し、ショートが起き、組立歩留が低下することが多い。Junction down
) method improves the heat dissipation of the light emitting region, but since the light emitting point is located below the chip, solder adheres to the light emitting region during bonding, often causing short circuits and lowering the assembly yield.
また、サブマウントとチップの線膨張係数のズレが大き
いと、発光領域に機械的歪が強く加わり、劣化の原因と
なる。ジャンクションアップ（Ｊｕｎｃｔｉｏｎ ｕｐ
）法では放熱性が悪くなるが組立易く、かつ発光領域
に機械的歪が加わりにくいという利点を有する。どちら
の組立法を用いるかはチップの特性とその使用状態によ
り決めなければならない。しかし、チップ構造（主に電
極構造）によっては採用できない組立法もある。Furthermore, if there is a large difference in linear expansion coefficient between the submount and the chip, strong mechanical strain will be applied to the light emitting region, causing deterioration. Junction up
) method results in poor heat dissipation, but has the advantage of being easy to assemble and hardly subjecting the light emitting region to mechanical strain. Which assembly method to use must be determined depending on the characteristics of the chip and the conditions in which it will be used. However, there are some assembly methods that cannot be adopted depending on the chip structure (mainly the electrode structure).
本発明は、上記のような問題点、即ちチップ組立法が限
定されるという点を解消するためになさレタもので、ｎ
型、ｐ型基板を問わずジャンクションアップ（Ｊｕｎｃ
ｔｉｏｎ ｕｐ ） ＋ ジャンクションダウン（Ｊｕ
ｎｃｔｉｏｎ ｄｏｗｎ ）組立が可能な光半導体素子
用サブマウントを提供することを目的とする。The present invention was made in order to solve the above-mentioned problem, that is, the chip assembly method is limited.
Junction up regardless of type or p type substrate.
tion up) + junction down (Ju
An object of the present invention is to provide a submount for an optical semiconductor element that can be assembled.
本発明に係る光半導体素子用サブマウントは、サブマウ
ント本体を熱伝導率が良好で、電気的絶縁体から構成し
、該サブマウント上に光半導体素子チップを接着するた
めの導電性のチップ接着部と、ワイヤを接着するための
導電性のワイヤ接着部とを備えたものである。The submount for optical semiconductor devices according to the present invention has a submount body having good thermal conductivity and made of an electrical insulator, and a conductive chip adhesive for bonding the optical semiconductor device chips onto the submount. and a conductive wire bonding portion for bonding the wire.
この発明においては、サブマウント本体が電気的絶縁体
からなっているので、チップ接着部に接着されたチップ
はワイヤが接続されてない状態ではステムとも負リード
電極とも絶縁された状態となり、これに適当にワイヤを
接続することにより、ｎ型、ｐ型基板を問わず、種々の
組立法が可能となる。In this invention, since the submount body is made of an electrical insulator, the chip bonded to the chip bonding part is insulated from both the stem and the negative lead electrode when no wire is connected. By connecting the wires appropriately, various assembly methods are possible for both n-type and p-type substrates.
以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による光半導体素子用サブマウン
トを示し、図中、第４図と同一符号は同一部分を示す。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a submount for an optical semiconductor device according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 4 indicate the same parts.
第１図（ａ）はサブマウントを示し、２は電気的絶縁体
からなるサブマウント本体、３は該サブマウント本体２
上に設けられ、その上にチップを接着するためのチップ
接着部、４は上記サブマウント本体２上に設けられ、そ
の上にワイヤを接着するためのワイヤ接着部である。FIG. 1(a) shows a submount, 2 is a submount body made of an electrical insulator, and 3 is the submount body 2.
A chip bonding section 4 is provided on the submount main body 2 to bond a chip thereon, and a wire bonding section 4 is provided on the submount body 2 to bond a wire thereon.
ここで上記サブマウント本体２の寸法は幅１．２゜奥行
０．４．厚み９．３３ｍｍとした。Here, the dimensions of the submount main body 2 are width 1.2 degrees and depth 0.4 degrees. The thickness was 9.33 mm.
第１図（ｂｌは第１図（ＩＩ）のサブマウントを用いた
レーザチップの組立法を示す図であり、１はレーザチッ
プ、６はステム（又はパッケージ）、１１゜１２．１３
はワイヤ、２０は出力光（レーザ光）である。このサブ
マウント本体２はその絶縁体部分を、ＢｅＯ又はＳｉＣ
を主成分とする物質とすることにより、熱伝導性が良好
となり、チップの放熱性を良くすることができる。FIG. 1 (bl is a diagram showing a method of assembling a laser chip using the submount of FIG. 1 (II), 1 is a laser chip, 6 is a stem (or package), 11° 12.13
is a wire, and 20 is an output light (laser light). This submount main body 2 has an insulator part made of BeO or SiC.
By using a substance containing as a main component, the thermal conductivity becomes good and the heat dissipation of the chip can be improved.
次に動作について説明する。Next, the operation will be explained.
第１図の組立法では電流がワイヤ１３から流入し、チッ
プ１．ワイヤ１１．ワイヤ１２の順に流れる。この組立
法はｎ型基板を用いたチップのジャンクションダウン（
Ｊｕｎｃｔｉｏｎ ｄｏｗｎ ）組立、ｐ型基板を用い
たチップのジャンクションアップ（Ｊｕｎｃｔｉｏｎ
ｕｐ ）組立のいずれにも適応できる。In the assembly method of FIG. 1, current flows from wire 13 into chip 1. Wire 11. The wires 12 flow in this order. This assembly method uses an n-type substrate to junction down the chip (
Junction down assembly, chip junction up using a p-type substrate
UP) Applicable to any assembly.
第２図は上記実施例のサブマウントの他の使用法を示す
図である。図中、第１図と同一符号は同一部分を示す。FIG. 2 is a diagram showing another method of using the submount of the above embodiment. In the figure, the same symbols as in FIG. 1 indicate the same parts.
第２図の組立法では電流がワイヤ１３から流入し、チッ
プ１．ワイヤ１２の順に流れる。この組立法も上記第１
図の組立法と同様、ｎ型基板を用いたチップのジャンク
ションアップ（Ｊｕｎｃｔｉｏｎ ｕｐ組立、ｐ型基板
を用いたチップのジャンクションダウンＵｕｎｃｔｉｏ
ｎ ｄｏｗｎ ）組立のいずれにも適応できる。この組
立法ではワイヤ接着部４は必要ではない。In the assembly method of FIG. 2, current flows from wire 13 into chip 1. The wires 12 flow in this order. This assembly method is also the same as the first one above.
Similar to the assembly method shown in the figure, there is a junction up assembly of a chip using an n-type substrate, and a junction-down assembly of a chip using a p-type substrate.
n down ) can be applied to any assembly. This assembly method does not require the wire bond 4.
なお、第１．第２ｖｊ！Ｊで示した例では、サブマウン
トが直接ステム（又はパッケージ）に接着されていたが
、このサブマウントは導電体を介してステムに接着する
こともできる。In addition, 1. 2nd vj! In the example shown in J, the submount was directly bonded to the stem (or package), but the submount could also be bonded to the stem via a conductor.
第３図はステム６に相当する導電体として銀ブロックを
用いた場合の他の組立例を示し、図中、第１図と同一符
号は同一部分を示す、５は銀ブロック５からなる導電体
である。ワイヤ１３は導電体５に接着されている。FIG. 3 shows another example of assembly in which a silver block is used as the conductor corresponding to the stem 6. In the figure, the same reference numerals as in FIG. It is. The wire 13 is bonded to the conductor 5.
この構造を採用することにより、以下の実際的な利点が
生ずる。即ち、導電体（銀ブロック）５に組立られたチ
ップ１を最小単位として、チップを種々のパッケージに
組込む（組換える）ことが可能となる０組込みに際して
は、負リード端子からワイヤ１２を取外す必要が生ずる
が、ワイヤ１） ２はチップ本体とは分離されている為
、チップに力が加わることがなく、信頼性上問題が生ず
ることはない。Adopting this structure provides the following practical advantages. That is, when the chip 1 assembled on the conductor (silver block) 5 is used as the minimum unit and the chip can be assembled (recombined) into various packages, it is necessary to remove the wire 12 from the negative lead terminal. However, since the wires 1) and 2 are separated from the chip body, no force is applied to the chip, and no reliability problems occur.
以上のようにこの発明に係る光半導体素子用サブマウン
トによれば、サブマウント本体を熱伝導性が良好で、電
気的絶縁体から構成し、該サブマウント本体上に導電性
のチップ接着部とワイヤ接着部とを電気的に分離させて
設けたので、ｎ型基板、ｐ型基板を用いたチップに対し
、ジャンクションアップ（Ｊｕｎｃｔｉｏｎ ｕｐ ）
＋ ジャンクションダウン（Ｊｕｎｃｔｉｏｎ ｄｏ
ｗｎ ）組立のいずれもが可能となり、あらゆる組立法
が可能となる。さらに熱伝導性のよいサブマウントを用
いているので、チップの放熱性も良好となる効果がある
。As described above, according to the submount for optical semiconductor devices according to the present invention, the submount body has good thermal conductivity and is made of an electrical insulator, and the submount body has a conductive chip bonding part on the submount body. Since the wire bonding part is electrically separated from the wire bonding part, junction up is possible for chips using n-type and p-type substrates.
+ Junction do
wn) Any assembly method is possible. Furthermore, since a submount with good thermal conductivity is used, the heat dissipation of the chip is also improved.
第１図はこの発明の一実施例を示す図であり、第１図（
ａ）はサブマウントを示す図、第１図中）はサブマウン
トを用いた組立法を示す図、第２図は上記実施例を用い
た他の組立法を示す図、第３図はさらに他の組立法を示
す図であり、第４図は従来の組立法を示す図、第４図（
ａ）は従来のサブマウントを示す図、第４図（ｂ）はこ
のサブマウントを用いた組立法を示す図である。
１はチップ、２はサブマウント本体、３はチッ７”接ｆ
ＦｌＩＳ、 ４はワイヤ接着部、６はステム、１１゜
１２．１３はワイヤである。FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
a) is a diagram showing a submount, FIG. 1) is a diagram showing an assembly method using a submount, FIG. 2 is a diagram showing another assembly method using the above embodiment, and FIG. Figure 4 is a diagram showing a conventional assembly method, Figure 4 (
FIG. 4(a) is a diagram showing a conventional submount, and FIG. 4(b) is a diagram showing an assembly method using this submount. 1 is the chip, 2 is the submount body, 3 is the chip 7” contact f
FlIS, 4 is a wire bonding part, 6 is a stem, and 11°12.13 is a wire.
Claims (3)
ウント本体と、該サブマウント本体上に設けられその上
に光半導体素子チップを搭載するための導電性のチップ
接着部と、上記サブマウント本体上に上記チップ接着部
と電気的に分離されて設けられワイヤを接着するための
導電性のワイヤ接着部とを備えたことを特徴とする光半
導体素子用サブマウント。(1) A submount main body that has good thermal conductivity and is an electrical insulator, and a conductive chip adhesive part provided on the submount main body for mounting an optical semiconductor element chip thereon; A submount for an optical semiconductor element, comprising: a conductive wire bonding part for bonding a wire, which is provided on the submount body to be electrically separated from the chip bonding part.
）を含むものであることを特徴とする特許請求の範囲第
１項記載の光半導体素子用サブマウント。(2) The submount for an optical semiconductor device according to claim 1, wherein the submount body contains BeO (beryllium oxide).
イド）を含むものであることを特徴とする特許請求の範
囲第１項記載の光半導体素子用サブマウント。(3) The submount for an optical semiconductor device according to claim 1, wherein the submount body contains SiC (silicon carbide).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60077990A JPS61234588A (en) | 1985-04-11 | 1985-04-11 | Submount for optical semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60077990A JPS61234588A (en) | 1985-04-11 | 1985-04-11 | Submount for optical semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61234588A true JPS61234588A (en) | 1986-10-18 |
Family
ID=13649266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60077990A Pending JPS61234588A (en) | 1985-04-11 | 1985-04-11 | Submount for optical semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61234588A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482537A (en) * | 1987-09-24 | 1989-03-28 | Mitsubishi Electric Corp | Sub-mount for optical semiconductor element |
| US5214660A (en) * | 1990-09-25 | 1993-05-25 | Fujitsu Limited | Laser diode module and method for fabricating the same |
| JP2001345507A (en) * | 2000-06-01 | 2001-12-14 | Rohm Co Ltd | Semiconductor laser and optical pickup |
| JPWO2019116981A1 (en) * | 2017-12-15 | 2020-12-17 | ローム株式会社 | Submount and semiconductor laser equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59167038A (en) * | 1983-03-14 | 1984-09-20 | Hitachi Ltd | Structure of submount for photo semiconductor element |
-
1985
- 1985-04-11 JP JP60077990A patent/JPS61234588A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59167038A (en) * | 1983-03-14 | 1984-09-20 | Hitachi Ltd | Structure of submount for photo semiconductor element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482537A (en) * | 1987-09-24 | 1989-03-28 | Mitsubishi Electric Corp | Sub-mount for optical semiconductor element |
| US5214660A (en) * | 1990-09-25 | 1993-05-25 | Fujitsu Limited | Laser diode module and method for fabricating the same |
| JP2001345507A (en) * | 2000-06-01 | 2001-12-14 | Rohm Co Ltd | Semiconductor laser and optical pickup |
| JPWO2019116981A1 (en) * | 2017-12-15 | 2020-12-17 | ローム株式会社 | Submount and semiconductor laser equipment |
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