JPS6320638U - - Google Patents
Info
- Publication number
- JPS6320638U JPS6320638U JP11201286U JP11201286U JPS6320638U JP S6320638 U JPS6320638 U JP S6320638U JP 11201286 U JP11201286 U JP 11201286U JP 11201286 U JP11201286 U JP 11201286U JP S6320638 U JPS6320638 U JP S6320638U
- Authority
- JP
- Japan
- Prior art keywords
- switching transistor
- circuit
- turned
- level
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案に係るデータ伝送回路の実施例
を示す回路図、第２図ａ，ｂはそれぞれ第１図に
おけるスイツチングトランジスタの動作レベルを
示す図、第３図は各スイツチングトランジスタの
データ信号レベルに対する出力レベルを示す図、
第４図は本考案の他の実施例を示す回路図、第５
図は従来のデータ伝送回路を示す回路図である。
Ｒ１……抵抗、Ｑ１，Ｑ２……スイツチングト
ランジスタ、ｌ……伝送ケーブル、１……定電流
回路。
FIG. 1 is a circuit diagram showing an embodiment of the data transmission circuit according to the present invention, FIGS. 2a and b are diagrams showing the operating levels of the switching transistors in FIG. 1, and FIG. A diagram showing the output level relative to the data signal level,
FIG. 4 is a circuit diagram showing another embodiment of the present invention;
The figure is a circuit diagram showing a conventional data transmission circuit. R1 ...Resistor, Q1 , Q2 ...Switching transistor, l...Transmission cable, 1...Constant current circuit.
Claims (1)
スイツチングトランジスタと、 該第１のスイツチングトランジスタに接続した
該トランジスタオン時の第１の整合用負荷抵抗と
、 前記第１のスイツチングトランジスタと直列接
続された該トランジスタと相補型の第２のスイツ
チングトランジスタ、該第２のスイツチングトラ
ンジスタの電流制限素子及び前記第２のスイツチ
ングトランジスタオン時の第２の整合用負荷抵抗
を含み、伝送ケーブル短絡時において前記第２の
スイツチングトランジスタを保護するための定電
流回路とを備え、 前記第１及び第２のスイツチングトランジスタ
に入力データを印加すると共に、各トランジスタ
のオンレベル及びオフレベルにヒステリシスを持
たせるように構成したことを特徴とするデータ伝
送回路。[Claims for Utility Model Registration] A first switching transistor for sending data to a transmission cable; a first matching load resistor connected to the first switching transistor when the transistor is turned on; a second switching transistor complementary to the first switching transistor connected in series; a current limiting element of the second switching transistor; and a second matching when the second switching transistor is turned on. a constant current circuit for protecting the second switching transistor in the event of a short circuit in the transmission cable; 1. A data transmission circuit characterized in that the circuit is configured to have hysteresis in the on level and off level of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201286U JPS6320638U (en) | 1986-07-23 | 1986-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201286U JPS6320638U (en) | 1986-07-23 | 1986-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6320638U true JPS6320638U (en) | 1988-02-10 |
Family
ID=30992480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11201286U Pending JPS6320638U (en) | 1986-07-23 | 1986-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320638U (en) |
-
1986
- 1986-07-23 JP JP11201286U patent/JPS6320638U/ja active Pending
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