JPH0170428U - - Google Patents

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Publication number
JPH0170428U
JPH0170428U JP1987166232U JP16623287U JPH0170428U JP H0170428 U JPH0170428 U JP H0170428U JP 1987166232 U JP1987166232 U JP 1987166232U JP 16623287 U JP16623287 U JP 16623287U JP H0170428 U JPH0170428 U JP H0170428U
Authority
JP
Japan
Prior art keywords
key
source
active
signal
impedance state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987166232U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987166232U priority Critical patent/JPH0170428U/ja
Publication of JPH0170428U publication Critical patent/JPH0170428U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本考案の第1、第2の実施例
を示す回路図で、第3図は従来の回路例、第4図
はスイツチS1、スイツチS2を同時にONした
時の電流の経路を示した図である。 1……IC、1′……IC、2〜5……逆流防
止用ダイオード、S1,S2……スイツチ、KS
〜KS,KS′〜KS′……キーソース
信号出力端子、K〜K,K′〜K′……
キーリターン信号入力端子。
Figures 1 and 2 are circuit diagrams showing the first and second embodiments of the present invention, Figure 3 is a conventional circuit example, and Figure 4 is the current when switches S1 and S2 are turned on at the same time. FIG. 1...IC, 1'...IC, 2-5...backflow prevention diode, S1, S2...switch, KS
0 ~ KS3 , KS0 '~ KS3 '...Key source signal output terminal, K0 ~ K3 , K0 '~ K3 '...
Key return signal input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] キーソース信号とキーリターン信号でマトリツ
クスを構成するキーマトリツクス回路において、
キーソース信号がアクテイブのとき信号源をロー
インピーダンスとし、ノンアクテイブのときハイ
インピーダンス状態となる出力回路を有すること
を特徴とするキーマトリツクス回路。
In a key matrix circuit that configures a matrix with key source signals and key return signals,
1. A key matrix circuit comprising an output circuit that sets a signal source to a low impedance state when the key source signal is active and to a high impedance state when the key source signal is non-active.
JP1987166232U 1987-10-29 1987-10-29 Pending JPH0170428U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987166232U JPH0170428U (en) 1987-10-29 1987-10-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987166232U JPH0170428U (en) 1987-10-29 1987-10-29

Publications (1)

Publication Number Publication Date
JPH0170428U true JPH0170428U (en) 1989-05-10

Family

ID=31453436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987166232U Pending JPH0170428U (en) 1987-10-29 1987-10-29

Country Status (1)

Country Link
JP (1) JPH0170428U (en)

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