JPS63204454A - Microcomputer - Google Patents

Abstract

PURPOSE:To synthesize and to output the element pulses of an optional waveform at an optional time interval by setting a start address of the waveform data and the start address of the data at the generating interval of each element pulse forming a pulse signal. CONSTITUTION:A CPU sets the start addresses at a generating interval data start address register 5 and a waveform data start address register 7 respectively. The generating interval data on a RAM 1 corresponding to the address set at the register 5 is held by a timer register 43. When a counting job is through with a reloading timer 4, the addresses are successively produced from a generating interval data address counter 6. Then the generating interval data on the RAM 1 is sent again to the register 43 and held there. While a waveform address counter 8 produces successively addresses at and after the address set at the register 7 every time the timer 4 finishes its counting action. Thus the corresponding waveform data on the RAM 1 is given to a pulse signal generating circuit 11 and the element pulse signals can be synthesized and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more specifically, to a microcomputer having a function of generating pulse signals such as pulses for driving a pulse motor.

[Prior art]

Conventionally, when a microcomputer generates a pulse signal for the purpose of driving a pulse motor, for example, the pulse signal is processed by software processing of the CPU, specifically, the waveform of each elementary pulse that makes up the pulse signal is Controls synthesis and its generation interval.

[Problems to be solved by invention C] However, for example, when rotating a pulse motor at high speed, it is necessary to perform waveform synthesis of elementary pulses very frequently and also to control the generation timing and output it. Become. Therefore, the CPU has little room to perform other software processing.

Therefore, even if there is an extremely urgent interrupt request, it will not be possible to respond immediately to it, and so-called real-time responsiveness will deteriorate.

The present invention was made in view of these circumstances, and
The purpose of the present invention is to propose a microcomputer that can generate pulse signals by synthesizing and outputting elementary pulses of arbitrary waveforms at arbitrary time intervals without performing almost any software processing by CPt1.

[Means for solving problems]

The microcomputer of the present invention stores in memory in advance data strings of various patterns of occurrence intervals of each elementary pulse constituting a pulse signal and data strings of various patterns of waveforms, and sequentially stores data strings of various patterns of waveforms from a set start address. Data on the generation interval is given to a timer and time is elapsed, and each time the time elapses, waveform data is sequentially read out from a set start address and elementary pulses are synthesized and output.

The present invention provides a microcomputer that outputs a pulse signal, including a memory storing waveform data of elementary pulses constituting the pulse signal and a series of generation interval data defining the generation interval thereof, and a first register in which an arbitrary start address in the memory is set; a first address counter that sequentially generates addresses from the start address set in the first register; and an arbitrary start address in the memory for the waveform data. a second register in which a start address is set; a second address counter that sequentially generates addresses from the start address set in the second register; and an interval at which addresses are generated by the first address counter. a timer register in which data is set; a timer that generates the next address in the first address counter and the second address counter upon completion of counting the set value of the timer register; and a pulse signal from the given waveform data. The pulse signal generation circuit is characterized in that it includes a pulse signal generation circuit that generates and outputs the pulse signal generation circuit, and a dedicated bus that transfers waveform data of the address generated by the second address counter from the memory to the pulse signal generation circuit.

[Effect]

In the microcomputer of the present invention, elementary pulses of arbitrary waveforms are synthesized at arbitrary time intervals by setting the start address of the data of the generation interval of each elementary pulse making up the pulse signal and the start address of the waveform data. It is possible to output and generate a pulse signal.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to figures showing embodiments thereof.

The figure is a block diagram showing the configuration of main parts of a microcomputer according to the present invention.

In the figure, reference numeral 1 denotes a memory for storing waveform data sequences of elementary pulses and their generation interval data sequences for driving a pulse motor, specifically, I? It is AM.

The waveform data string and generation interval data string are, for example, the waveform and generation of each elementary pulse of a series of pulse signal patterns corresponding to various situations such as when the pulse motor starts, stops, operates at constant speed, changes speed, etc. This is a data string of intervals. Therefore, various patterns of drive control are possible by appropriately combining the two according to the operating conditions of the pulse motor.

The RAMI is connected to, for example, CPt1 via an internal bus (not shown), so that data can be rewritten as needed, and it is also connected to a real-time bus 2 dedicated to the pulse signal generation function, so that waveform data and Occurrence interval data is sent to this real-time bus 2.

Again? An address register 3 is attached to AM1. This RAM address register 3 is connected to a generation interval data address counter 6 via a real-time bus 2.
and RA given from waveform data address counter 8
By accessing the RAMI address stored in the R static address register 3, data at the corresponding address is sent from the RAMI to the real-time bus 2. .

4 in the figure is a load timer, and a system clock generation circuit 41. Up counter 42. It is composed of a timer register 43 and the like. The reload timer 4 uses an up counter 42 to count the system clock generated by the system clock generation circuit 41, and when this counted value matches the value set in the timer register 43, the amplifier counter 42 outputs a timing end signal. EC is output. This time measurement end signal EC is sent to the generation interval data address counter 6, timer register 43, and up counter 4 described in 1.
2 and a gate 44 interposed between the two.

Note that the gate 44 is opened by the clock end signal EC and sets the set value of the timer register 43 to the up counter 42.

In the figure, 5 is the first register, the generation interval data start address register, which is used to set the start address in the CPU as one of the addresses of the generation interval data strings marked ↑ and Q in the RAMI. be. Further, the start address of the generation interval data set in the generation interval data start address register 5 is applied via the gate 51 to the generation interval data address counter 6, which is a first address counter.

The generation interval data address counter 6 sequentially generates the addresses of the generation interval data from the start address of the generation interval data given from the generation interval data start address register 5 as described above.

Address generation by the generation interval data address counter 6 is performed every time a signal is applied from the amplifier counter 42 mentioned above, and is sent to the real-time bus 2. The address of the occurrence interval data sent from the occurrence interval data address counter 6 to the real-time bus 2 is temporarily held in the RAM address register 3.

Therefore, first, the start address of the generation interval data set in the generation interval data start address register 5 is input from the generation interval data address counter 6 via the real-time bus 2 to l? The generation interval data held in the AM address register 3 and written (, 1) in the RAMI corresponding to this address is read out and stored in the timer register 4.
3. Then, time is counted by the load timer 4 corresponding to the occurrence interval data held in the timer register 43, and when this time measurement ends,
Occurrence interval data Address counter 6 Up counter 4
2, the generation interval data address counter 6 generates the address of the next generation interval data.

By repeating such processing, each time the time interval determined by each occurrence interval data elapses starting from the occurrence interval data corresponding to the start address set in the occurrence interval data start address register 5, Sequential occurrence interval data is read from RAMI.

In the figure, 7 is a waveform data start address register which is a second register, and the start address of waveform data is set by the CPU. The start address of the waveform data set in the waveform data start address register 7 is applied via a gate 81 to a waveform data address counter 8 which is a second address counter.

The waveform data address counter 8 sequentially generates waveform data addresses from the waveform data start address set in the waveform data start address register 7 described above and sends them to the real-time bus 2. The address of the waveform data sent to the real-time bus 2 is temporarily held in the RAM address register 3, and the waveform data at the corresponding RAMI address is transferred to the real-time bus 2.
will be sent to.

9 is a waveform data output sofa, which outputs I? through real-time bus 2. This is a buffer memory that temporarily stores waveform data sent from AM1. The waveform data recorded in waveform data output buffer 9 (f, 17) is applied to waveform data output register 10 via gate 91. Note that the gate 91 is controlled to open and close by a timing end signal EC output from the up counter 42.

The waveform data output register 10 receives the waveform data α written in the waveform data output bannofer 9 through the gate 91 at the timing when the counter 42 outputs the clock end signal EC, and further pulses the data. It is applied to the signal generation circuit 11.

The pulse signal generation circuit 11 has a waveform data output register 10.
The digital waveform data provided by the controller is synthesized into an analog elementary pulse signal and output to the outside, for example, to a pulse motor control circuit.

Therefore, when the elapse of time corresponding to one generation interval data by the reload timer 4 ends, the up counter 42 sends a timing end signal I to the waveform data address counter 8.
EC is applied, and the waveform data address counter 8 generates the address of the next waveform data. The address of the waveform data generated by this waveform data address counter 8 is temporarily stored in the RAM address register 3 via the real-time bus 2, and the corresponding RAM
The waveform data at the address I is sent to the real-time bus 2. The waveform data sent to the real-time bus 2 is stored in the waveform data output register 9, and is then stored in the waveform data output register 10 by opening the gate 91 when the up counter 42 outputs the timing end signal EC. given and remembered. Thereby, the waveform data as digital data stored in the waveform data output register 10 is given to the pulse signal generation circuit 11 and outputted to the outside as an analog elementary pulse signal.

12 in the figure is a real-time bus control circuit, which controls the transfer of various signals by the real-time bus 2.

The operation of the microcomputer of the present invention configured as described above will be explained below.

First, the CPU sets start addresses in the generation interval data start address register 5 and the waveform data start address register 7, respectively. Both stars
- The address indicates the current operating state of the pulse motor being controlled (stopped, accelerating, decelerating, constant speed operation, etc.)
, are set according to the desired state and the time required to achieve that state.

Then, l? corresponding to the start address of the occurrence interval data set in the occurrence interval data scud address register 5? The occurrence interval data of AM1 is held in the timer register 43, and the time determined by this occurrence interval data is measured by the reload timer 4. Upon completion of this time measurement, the generation interval data address counter 6 generates the next address, and the corresponding RAMI generation interval data is again sent to the timer register 43 and held there.

On the other hand, each time the reload timer 4 finishes counting, the waveform data address counter 8 sequentially generates waveform data addresses starting from the waveform data start address set in the waveform data start address register 7. As a result, the IIA old waveform data corresponding to each waveform data is read out, provided to the pulse signal generation circuit 11 via the waveform data output cover sofa 9 and the waveform data output register O, and output as an analog elementary pulse signal. Ru.

In this way, in the microcomputer of the present invention, the time interval determined by the generation interval data is counted by the reload timer 4, and each time each time measurement ends, the waveform data is sequentially read from the RAMI and the elementary pulses are synthesized and output. Therefore, the RAMI stores various Bakun generation interval data and waveform data, and each start address set in the generation interval data scud address register 5 and the waveform data start address register 7 is stored in the RAMI. By appropriately selecting and setting, it is possible to generate pulse signals for pulse motor control in response to various situations.

In the above embodiment, an example in which a pulse signal for driving a pulse motor is generated and outputted is described in detail, but this is just an example, and various control objects that are controlled in a pulse manner by a pulse signal are described in detail. The microcomputer of the present invention can be used in

〔effect〕

As described above, according to the microcomputer of the present invention,
Since it becomes possible to generate pulse signals with arbitrary waveforms and arbitrary generation intervals to drive pulse motors etc. with almost no software processing using Crtl, the burden on the software of the CPU is reduced. It also becomes possible to immediately respond to interrupt requests with a high degree of urgency.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of main parts of a microcomputer according to the present invention. 1...l? AI'l 2... Real Quim Has 4... Reload Quim 5... Occurrence Interval Data Screen-1-Address Register 6... Occurrence Interval Data Address Counter 7... Waveform Data Scoot Atlas Register 8... Waveform Data address counter 11...pulse signal generation circuit

Claims (1)

[Scope of Claims] 1. A microcomputer that outputs a pulse signal, comprising: a memory storing waveform data of elementary pulses constituting the pulse signal and a series of generation interval data defining their generation intervals; and a memory storing the series of generation interval data. a first register in which an arbitrary start address of the interval data in the memory is set; a first address counter that sequentially generates addresses from the start address set in the first register; and a first address counter that sequentially generates addresses from the start address set in the first register; a second register in which an arbitrary start address in the memory is set; a second address counter that sequentially generates addresses from the start address set in the second register; and the first address counter. a timer register in which address generation interval data is set; and a timer that generates the next address in the first address counter and the second address counter upon completion of counting the set value of the timer register. A pulse signal generation circuit that generates and outputs a pulse signal from waveform data, and a dedicated bus that transfers waveform data of an address generated by the second address counter from the memory to the pulse signal generation circuit. microcomputer.