RU1805450C - Multichannel device for numeric control of stepping motors - Google Patents

Abstract

The invention relates to automatic controls and can be used to programmatically control virtually any stepper motor. The purpose of the invention is to simplify the device and expand its functionality. The device comprises a program unit, a bus interface, control channels, a control register. The proposed device at the minimum hardware level implements any laws of control of stepper motors, allows controlling several drives operating simultaneously from one control channel. 3 ill.

Description

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The invention relates to automatic controls and can be used to programmatically control virtually any stepper motor.

The purpose of the invention is to simplify the device and expand its functionality.

In FIG. 1 illustrates an example functional block diagram of a multi-channel device for programmatically controlling stepper motors for four control channels; in FIG. 2 is a functional block diagram of a software task; Fig. 3 is a functional diagram of one of the control channels.

The multi-channel device 1 for controlling the stepper motors comprises a program unit 2,

bus interface 3, control channels 4, control register 5. The outputs of control channels 4 and control register 5 are the outputs of the device.

The block of program task 2 (Fig. 2) consists of a command input / output device (I / O) 6 combined in RAM, a central processor 7, a read-only memory device (ROM) 8 with an operation algorithm, a clock generator 9, an address selector 10, a controller interrupts 11, address bus 12, data bus 13, read signal bus 14, write signal bus 15, bus 16 — interrupt input of the central processor 7, bus 17 — outputs of the clock generator 9, bus 18–21 — outputs of the controller 11 interrupt, bus 22 read permissions from ROM 8, read enable buses 23 with

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write to the air-blast RAM 6, enable buses 24, 26, 28, 30 to enable start triggers 33, enable buses 25, 27, 29, 31 to write the division factor into the register number 34, enable buses 32 to write to the control register 5.

Each control channel 4 consists of a start trigger 33, a number register 34, a frequency divider 35, a bus 37, which is the installation input of a frequency divider 36, a device output bus 38.

In ROM 8 recorded the algorithm of the device. The algorithm includes:

exchange of commands with the main processor connected via bus interface 3;

trigger trigger control;

load control of the register of the number 34 of each channel upon receipt of an appropriate interrupt;

load control of control register 5.

Through the input / output device 6, information is input, for each channel separately, about the number of steps, direction of movement, initial speed of movement, maximum speed, accelerations, current level in the motor windings and user control commands (necessary for the drive).

The speed of the engine is determined by the frequency of the pulses supplied to the step drive of the STEP bus 38, the remaining signals are fed to the step drive of the control register 5.

The device operates as follows.

The operation of all the component parts of the device is controlled by the central processor 7. The synchronization of the processor 7 is carried out by a generator 9, which also generates clock pulses for the control channels.

The operation algorithm is implemented by the processor 7 reading instructions from the ROM 8 and executing them. The executive action of the CPU 7 is to read or write information that is transmitted via the data bus 13. Reading or writing is carried out as follows;

The CPU 7 on the address bus 12 (A) sets the device address;

an address selector 10 on one of the outputs 22 ... 32 sets an enable signal;

on the data bus 13 when writing the CPU, and when reading the selected device data is set,

data reading occurs on a signal on bus 14, recording - on a signal on bus 15.

After power-up, the CPU 7 writes readiness messages to the air-blast RAM 6

drives. After that, the main processor enters into the air-blast RAM 6 commands for controlling each channel separately. The channels are independently controlled. At

Upon receipt of the start command, the program unit 2 writes the corresponding control signals for the stepper drives to the control register 5. The start of control channels 4 is carried out by the unit

program task 2. On the information buses 13, 25, 15 in the register number 34 of one of the channels is written the code for dividing the frequency, which is transmitted via bus 37 to the installation inputs of the frequency divider

35. Pulses are sent to the information input of the frequency divider 35 via a bus 17 from a pulse generator 9.

On the information buses 13,24,15 in the start trigger 33, the start command of the frequency motor 35 is recorded, on the bus 36, the start signal is supplied to the control input of the frequency divider. The divider 35 outputs. (Bus 38) pulses, the period of which depends on the number of the division coefficient recorded in the number register. The signal from the output of the frequency divider 35 is also sent via bus 18 (for channel 0) to the interrupt controller 11. Upon receipt of a positive difference, the signal to one of the inputs of the interrupt controller 11 sends an interrupt signal to CPU 7 via bus 16, and via data bus 13 the interrupt vector, thereby reporting on which channel the interrupt occurred. Immediately after that in the number register

34 channels where the interruption occurred, a new number is recorded. If a frequency change is not required for uniform movement, then a new number is not recorded. When an interrupt arrives, steps are also counted, acceleration steps are counted, the current speed is compared with a given maximum, the next number is calculated to be written in the register, the number of braking steps is compared with the remaining number of steps. At the same time, task block 2 monitors commands from the main processor .:

After the control channel 4 gives a predetermined number of steps, or by a command from the main processor via the information buses 13, 24, 15, the stop command of the frequency divider 35 is written to the start trigger 33. After that, the supply of control pulses to the bus 38 is possible only after a restart .

The maximum frequency of the output pulses of the control channels is determined by the total maximum interrupt service time and the time required to monitor the commands of the main processor.

The proposed device implements almost any laws of control of pre-engine. Since the control is at the program level, the program unit does not require any changes when connected to various drives. Due to the control register 5, STEP outputs 38 can be multiplexed, thereby controlling several drives that do not work simultaneously from one control channel.

The proposed device allows for mutually coordinated movement of the drives.

Claims (1)

SUMMARY OF THE INVENTION A multi-channel device for programmatically controlling stepper motors, comprising a program unit and, according to the number of stepper motors controlled, control channels, each of which contains a number register, a frequency divider, the group of installation inputs of which are connected to the group of information outputs of the number register , and the information input - with the synchronization output of the program unit, as well as the start trigger, the output of which is connected to the control division by the input of the frequency divider, which differs in order to simplify the device and expand the scope of application, a control register is inserted into it, the recording input of which is connected to the write control output of the program unit, the group of information inputs to the data bus of the program unit, and the recording permission input is connected to the permission output records of the program unit, the bit outputs of the control register are connected to the first group of information outputs of the device, the second group of information outputs of which are outputs of the control channels each of which has a recording input, setup enable input and start trigger information input is connected to the write control output, setup enable output and output of the corresponding data bit of the program unit, respectively, the group of information inputs of the number register is connected to the data bus, write input -with the write control output of the program unit, respectively, whose resolution enable recording is the division factor of which is connected to the enable register input of the number, the output of the divider is often s channel each coupled to a corresponding input of the interrupt program specifying unit. FIG. 2 -B J4 Iro At 35 STEP O 38 Fig.Z