JPS59116829A - Microcomputer - Google Patents

Abstract

PURPOSE:To generate easily a signal with a fast repetition speed by providing a storage means for storing a signal with a desired pattern and a means for outputting the signal with the desired pattern independently of the operation of a CPU in the same chip. CONSTITUTION:The pattern is started according to an indication from the side of a CPU10 or, for example, a carry signal from a timer/counter 16 which are sent through an OR gate 28. Then, a pattern selected synchronously with a clock sent from a multiplexer 22 is outputted from a memory 18 in sequence for pattern storage through a line 32. The multiplexer 22 selects a clock indicated from the CPU10 to a register 26 among plural kinds of clock from the counter 16 and uses it for pattern generation. In this constitution, the counter 16, memory 18, multiplexers 22 and 32, register 26, gate 28, etc., are provided on the same chip as in the case of the CPU10.

Description

[Detailed description of the invention] (1) Technical field of the invention The present invention relates to a one-chip type microcomputer.

(Mackerel) Conventional technology and problems When it was necessary to output an irregular pattern of %1'1%O1 signals from a microcomputer, conventionally that signal was created using software, but program There was a complicated problem. In addition, it is impossible to create a signal with a pulse width of about 1 to 2 μm, such as a signal that repeatedly inverts at an extremely high speed, and in such cases, it is difficult to create a signal with an arbitrary pattern separately. However, providing such an oscillator separately from the microcomputer and controlling it from the microcomputer side would lead to an increase in the number of terminals on the microcomputer.
I'm impressed by the increase in ifc comments.

(3) Purpose of the Invention Therefore, the present invention solves the above-mentioned problems of the prior art, and the purpose of the present invention is to provide a microcomputer that can output a signal with a desired pattern at a high repetition rate. It's about doing.

(4) Structure of the Invention A feature of the present invention that achieves the above-mentioned object is that a micro combiator in which a central processing unit, a storage device, and a clock generation circuit are provided on a single chip can have at least one type of desired pattern. a storage means for storing data; and a storage means for sequentially reading data of at least one type of desired pattern on the storage means in accordance with a clock from the clock generation circuit independently of the operation of the central processing unit, and generating a clock of the desired pattern. A means for outputting a signal to the outside is provided on the chip.

(5) Examples of the invention The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram representing a disaster embodiment of the present invention.
Like a normal one-chip microcomputer, it has a central processing bag [il (CPU) 1o, read-only memory (ROM) 12. Random access memory (RAM)
] 4. Furthermore, a timer/counter 16 is formed on one chip. In this embodiment, the pattern storage memory 18. Multiplexers 20 and 22, register 2
A pattern generator consisting of MPU 4 and 26, an OR gate 28, etc. is provided on the same chip as MPU10.

(3) In this embodiment, the pattern storage memory 18 is configured by a key, and stores one or more types of arbitrary pattern data given from the CPU 1O side via the bus 3 (1-). That is, when the instruction value of the pattern to be selected is sent to the register 24 via the bus 30, it is decoded and the multiplexer 20 selects the corresponding pattern.

The actual activation of the pattern is via Or Game) 28'e,
This is performed in response to an instruction given from the CPU10 side or, for example, a carry signal from a timer/counter.

When activation is performed, the selected pattern is sequentially output to the outside via the line 32t- in synchronization with the clock sent from the multiplexer 22. 8-bit pattern 1 shown in pattern storage memory 58 in Figure 111
If 03010101 is selected, the output will be as shown in Figure 2, and if '%00100(110'' (4)) is selected, the output will be as shown in Figure 2 FBI.

The multiplexer 22 is a timer/counter] 6, and among the multiple types of clocks from the register 2 from the CP'U 10 side.
The clock designated by 6 is selected as the clock for pattern generation.

As mentioned above, according to this embodiment, a fast repetitive signal (for example, a pulse width of the turtle 1 level in FIG. 2 (2) It is possible to easily generate signals with irregular patterns (such as 1μ crown) without any burden on the software.Therefore, the burden on the software can be reduced, and high-speed pattern signals can be easily generated. This opens up new application areas.

In the above embodiment, RAM& is used as the memory for pattern storage, but this may be a shift register, or may be a ROM if the pattern is fixed from the beginning. The number is not limited to 8 bits, but may be more than or equal to 8 bits, and the pattern generator may have a plurality of outputs.

Further, in order to permanently repeat and generate a predetermined pattern, the pattern generator of the embodiment shown in FIG. 3 is employed.

An instruction is sent to the permanent generation mode register 34 from the MPU10 side, and when the output becomes 11'', the AND gate 36
is opened, and the most significant bit of the shift register 3-8, ie, the generated pattern output, is returned to its least significant bit, so that the same pattern is repeatedly generated.

As shown in FIG. 4, by switching the clock pulse according to the pattern output from the shift register 40, patterns with different duty ratios of 1%l and 2%0 can be obtained. Now, assuming that the clock CK sent through the line 42 has a shorter pulse width than the clock CKo sent through the line 44, if the output of the shift register 40 is ml'', the gate 46 opens and the clock When Vjli is CK, 0, the gate 1-48 is opened and the clock CK2 becomes the clock for the shift register 40, respectively. Therefore, the pattern output of the shift register 46, ie, the output of the pattern generator, is as shown in FIG. 2 (CI).

In order to be able to arbitrarily set the level value to %' or %0' when the pattern generator is not activated as described above, the configuration is as shown in Figure 5. In the figure, 50 is the pattern generator. , 52 is the CPU
A level register 54, which allows the user to set a level power from the l0 side or by other means, is set when the pattern generator 50 is activated and reset when it is stopped. It's a flip-flop. When the pattern generator 50 is activated, the gate 56 is turned on by the output of the flip-flop 54, so the output of the pattern generator 50 is directly output to the outside of the trench. When the pattern generator 50 is stopped, the gate 58 opens, and the level set in the level register 52 is output to the outside.

(7) The present invention includes the modifications shown in FIGS. 3 to 5 above.

(6) Effects of the Invention As explained in detail above, according to the present invention, there is a storage means for storing at least one type of desired pattern of signals, and a method for storing the desired pattern of signals independently of the operation of the central processing device. The means for sequentially outputting data according to the clock in the microcomputer is the same as the central processing bag. Because it is set in 3.

Signals with high repetition rates and irregular patterns can be generated very easily. Therefore, the entire range of new applications for microcomputers can be exploited, and the burden on software can be reduced.

Furthermore, since it is configured as a single chip, it is possible to significantly reduce costs and reduce the number of terminals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of a generation pattern, and FIGS. 3, 4, and 5 are a block diagram of another embodiment of the present invention. (8) It is a block diagram of the section. ]0...CPU, 12...ROM, 1
4...RAM, l 6...Timer/counter, J8...Memory for pattern storage, 20
．． 22...Multiplexer, 24, 26.34
・・・・・・Register%28・・・・・・OR gate, 3
0...Bus, 36...And Gate,
38.40...Shift register, 46.48°56.58...Gate, 50...Pattern generator, 52...Level register,
54...Flip-flop. Patent Applicant Fujitsu Limited Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney Yukio Uchiyama Patent Attorney Akira Yamaguchi (9) -155 Arrogance -156- 4

Claims (1)

[Claims] (2) In a microcomputer in which a central processing unit, a storage device, and a clock generation circuit are provided on one chip, a storage means for storing data of at least one type of desired pattern is independent of the operation of the central processing unit. means for sequentially reading data of at least V types of desired patterns from the storage means in response to a clock from the clock generating circuit and outputting a clock signal of the desired pattern to the outside; and means provided on all of the chips. Features a microcomputer.