JPH09134587A - Register apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To refer to contents stored in a register immediately after a power source is turned on, by storing set data in a register specified by an address signal or initialization data in each register upon receipt of a data-setting command or an initialization command. SOLUTION: A conversion means 1 S/P converts setting data (DT) and outputs to a signal line 2. A data-setting command means 3 outputs a data- setting command (ACLK) to a signal line 4. When receiving a reset signal RST, an initialization command circuit 11 outputs an initialization command (ILAT) to each register 5a-5h. When a data-setting means 12 receives the ACLK from the means 3, the means 12 stores the DT in a register specified by an address signal A0-A2. When the means 12 receives the ILAT from the circuit 11, the means stores initialization data in each register 5a-5h. Contents stored in each register can be referred to immediately when a power source is turned on, without a process of storing the setting data for every register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register device for storing setting data referred to when executing a microcomputer or the like.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a conventional register device. In the figure, when the setting data DT to be stored in a register is inputted as serial data, the setting data DT is converted into 8-bit parallel data. A shift register for converting into a parallel signal line, 2 is a parallel signal line for transmitting setting data DT which is 8-bit parallel data, 3 is an address signal A0 for specifying a register for storing the setting data DT,
When A1 and A2 are input, the address signals A0 and A
1, an address decoder that outputs a data setting command ACLK indicating that the setting data DT should be stored in a register specified by A2, 4 is a signal line for transmitting the data setting command ACLK, and 5a to 5h are referred to by a microcomputer or the like. The register 5a to 5h is a register for storing the setting data DT to be set.
When receiving CLK, the setting data DT output from the shift register 1 is stored.

Next, the operation will be described. When storing the setting data DT in each of the registers 5a to 5h of the register device, first, a microcomputer (not shown) or the like sets the setting data DT.
The (serial data) and the serial clock SCK are output to the shift register 1. This allows the shift register 1
Is set data DT (serial data) in synchronization with the falling edge of the serial clock SCK as shown in FIG.
Enter Then, the shift register 1 converts the setting data DT into parallel data and outputs it from the Q terminal.

On the other hand, since a microcomputer (not shown) or the like needs to instruct which register should store the setting data DT output to the shift register 1, the address signal A0, which specifies the register storing the setting data DT, A1,
The A2 and the data latch clock LAT are output to the address decoder 3. As a result, the address decoder 3 operates as shown in FIG.
As shown in, the address signals A0, A1, A2 are input in synchronization with the falling edge of the data latch clock LAT. Then, the address decoder 3 outputs the address signal A
The register for storing the setting data DT is recognized based on 0, A1, A2, and the data setting command ACLK is output to the register.

That is, the address signals A0, A1 and A2 are
Since it is sent as a signal of "0" or "1", a 3-bit binary expression (A0 is the least significant bit, A1 is the intermediate bit,
A2 is regarded as the most significant bit), and address signals A0, A
The register for storing the setting data DT is recognized according to the signal states of 1 and A2 (see FIG. 9). For example, when A0 is “1” and A1 and A2 are “0”, the register 5
The setting data DT will be stored in b.

Of the registers 5a to 5h, the register receiving the data setting command ACLK outputs the setting data DT output from the shift register 1 in synchronization with the falling edge of the data setting command ACLK as shown in FIG. Enter and store. As a result, the microcomputer (not shown) or the like can refer to the setting data stored in the register in the subsequent execution. In the case of FIG. 7, since eight registers are prepared, if the setting data needs to be stored in all of the registers 5a to 5h, the above operation is performed.
Need to be repeated times.

[0007]

Since the conventional register device is constructed as described above, each of the registers 5a-5
If the setting data DT is stored in h, the microcomputer or the like can refer to the setting data DT from the registers 5a to 5h at the time of execution, but in order to store the setting data DT in the registers 5a to 5h. Requires a microcomputer to transmit the setting data DT, which is serial data, to the shift register 1 and store the setting data DT in each of the registers 5a to 5h. Therefore, it takes time to store the setting data DT, Even if it is necessary for the microcomputer or the like to refer to the setting data DT immediately after turning on, there is a problem that it cannot be referred immediately.

The present invention has been made to solve the above problems, and an object thereof is to obtain a register device in which a microcomputer or the like can refer to the stored contents of a register immediately after power is turned on. .

[0009]

When receiving a data setting command from the data setting command means, the register device according to the first aspect of the invention stores the setting data in the register specified by the address signal, while the initialization command is issued. Upon receiving the initialization command from the means, the initial data is stored in each register.

In the register device according to the second aspect of the present invention, the first flip-flop outputs the H level signal from the output terminal, and the second flip-flop outputs the H level signal from the second output terminal. Is output, an initialization command is output.

According to another aspect of the register device of the present invention, the first flip-flop outputs an H-level signal from the second output terminal, and the second flip-flop outputs an H-level signal from the output terminal. Is output, an initialization command is output.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. 1 is a block diagram showing a register device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an 8-bit parallel setting data when the setting data DT stored in the register is input as serial data. A shift register (conversion means) for converting into data, 2 is a parallel signal line for transmitting setting data DT which is 8-bit parallel data, and 3 is an address signal A0, A1, A2 for specifying a register for storing the setting data DT. When input, an address decoder (data setting command means) 4 for outputting a data setting command ACLK indicating that the setting data DT should be stored in a register specified by the address signals A0, A1, A2 is data setting. Command ACLK
Is a register for storing the setting data DT referred to by a microcomputer or the like.

When a reset signal RST is input, an initialization command circuit (initializing circuit 11) outputs an initialization command ILAT indicating that preset initial data should be stored in each of the registers 5a to 5h. When receiving the data setting instruction ACLK from the address decoder 3, the initialization instruction circuit 12 stores the setting data DT in the register specified by the address signals A0, A1, A2, while the initialization instruction circuit 11
When the initialization command ILAT is received from each register 5a ...
Data setting means for storing initial data in 5h, 12a to
12h is a data setting circuit which constitutes the data setting means 12.

FIG. 2 is a block diagram showing the initialization command circuit 11. In the figure, 13 is a power supply for outputting an H level signal, and 14 is an L level signal when the reset signal RST is input. On the other hand, when the clock signal CLK is input from the output terminal), a flip-flop (first flip-flop) that outputs an H level signal from the Q terminal in synchronization with the clock signal CLK, and 15 is the reset signal RST When input, it outputs an H level signal from the QC terminal (second output terminal), while the clock signal C
When LK is input, a signal of the same level as the signal output from the Q terminal of the flip-flop 14 is output from the Q terminal (first output terminal) in synchronization with the clock signal CLK, and a signal of the opposite level. Is a flip-flop (second flip-flop) that outputs from the QC terminal.

A NAND circuit (logic 16) outputs an initialization command ILAT when the flip-flop 14 outputs an H-level signal from the Q terminal and the flip-flop 15 outputs an H-level signal from the QC terminal. Elements 17 output the L level signal from the Q terminal when the reset signal RST is input, while the clock signal CL
When K is input, in synchronization with the clock signal CLK,
It is a flip-flop that outputs a signal of the same level as the signal output from the Q terminal of the flip-flop 15 as a logical signal IDAT from the Q terminal.

FIG. 3 is a block diagram showing the data setting circuits 12a to 12h. In the figure, 18 is a data setting command ACLK or initialization command circuit 1 from the address decoder 3.
When the initialization command ILAT is received from 1, the write command LOUT
AND circuit 19 for outputting the signal, 19 is a NOT circuit for inverting the logic signal IDAT output from the initialization command circuit 11, 2
0 to 23 are OR circuits, and 24 to 27 are AND circuits.

Next, the operation will be described. First, the basic operation of the register device will be briefly described. When the reset signal RST is output from the microcomputer or the like after power is first turned on, preset initial data (for example, "11000101" in binary number) is stored in the registers 5a to 5h. Then, when it becomes necessary to change the stored contents of the registers 5a to 5h after that, new setting data DT is transmitted from the microcomputer or the like to the shift register 1, and the address signal A0 for specifying the register related to the change,
When A1 and A2 are output to the address decoder 3, the new setting data DT is stored in the register related to the change.

The operation of the register device will be specifically described below. First, when the power is turned on, the reset signal RS
When T becomes L level, as shown in FIG. 4, the flip-flops 14, 15, 17 of the initialization command circuit 11 are reset respectively, so that the flip-flops 14, 15,
17 outputs an L level signal from the Q terminal,
The flip-flop 15 outputs an H level signal from the QC terminal.

Therefore, in this case, the L-level signal output from the Q terminal of the flip-flop 14 and the H-level signal output from the QC terminal of the flip-flop 15 are input to the input terminals of the NAND circuit 16. Because it is done
The output of the NAND circuit 16 becomes H level. For this reason,
In this case, the initialization command ILAT is not output to the data setting circuits 12a to 12h. Incidentally, the transition of the output of the NAND circuit 16 from the H level to the L level corresponds to the initialization command ILAT.

Next, the reset signal RST changes from the L level to the H level, and the clock signal CLK is sent from the microcomputer or the like.
1 pulse is output, the flip-flops 14, 15 and 17 of the initialization command circuit 11 output a signal of the same level as the signal input to the D terminal from the Q terminal in synchronization with the clock signal CLK. .

That is, since the H-level signal is always input from the power source 13 to the D terminal of the flip-flop 14, the flip-flop 14 outputs the H-level signal from the Q terminal. Further, the D terminal of the flip-flop 15 is connected to the Q terminal of the flip-flop 14, and before outputting one pulse of the clock signal CLK, as described above, the L-level signal is output from the Q terminal of the flip-flop 14. Therefore, the flip-flop 15 outputs an L level signal from the Q terminal and an H level signal from the QC terminal. Further, the D terminal of the flip-flop 17 is connected to the Q terminal of the flip-flop 15, and before outputting one pulse of the clock signal CLK, an L-level signal is output from the Q terminal of the flip-flop 15 as described above. Therefore, the flip-flop 17 outputs an L level signal from the Q terminal.

Therefore, in this case, the H-level signal output from the Q terminal of the flip-flop 14 and the H-level signal output from the QC terminal of the flip-flop 15 are input to the input terminals of the NAND circuit 16. Because it is done
The output of the NAND circuit 16 becomes L level. For this reason,
In this case, the initialization command ILAT is output to each of the data setting circuits 12a to 12h.

In this way, the N of the initialization command circuit 11 is
When the initialization instruction ILAT is output from the AND circuit 16 to each of the data setting circuits 12a to 12h, the initialization instruction ILAT is input to the AND circuit 18 of each of the data setting circuits 12a to 12h, as shown in FIG. It And AN
The D circuit 18 receives the initialization command ILA from the initialization command circuit 11.
When T or the data setting command ACLK is received from the address decoder 3, the write command LOUT is output to the corresponding register, and the initial data (for example, “11000101” in binary) or new setting data is output. Command to store DT.

The logical signal ID output from the Q terminal of the flip-flop 17 in the initialization command circuit 11
As shown in FIG. 4, AT becomes an L level signal from the time when the initialization instruction ILAT is output from the NAND circuit 16, so that A in each of the data setting circuits 12a to 12h.
An L level signal is input to one of the input terminals of the ND circuits 24 to 27. When an L level signal is input to one of the input terminals of the AND circuits 24 to 27, AND
The outputs of the circuits 24 to 27 are not affected by the signal level input to the other input terminal (even if the setting data DT is output from the shift register 1, it is ignored).
The circuits 24 to 27 will always output an L level signal. That is, the NAND circuit 16 sends the initialization command ILAT
Is output, the AND circuits 24-27 always output an L level signal.

At this time, each data setting circuit 12a
Since the output of the NOT circuit 19 is input to one input terminal of each of the OR circuits 20 to 23 in 12h, an H level signal is input. When an H level signal is input to one of the input terminals of the OR circuits 20 to 23, O
The outputs of the R circuits 20 to 23 are not affected by the signal level input to the other input terminal (ignored even if the setting data DT is output from the shift register 1).
The circuits 20 to 23 always output the H level signal. That is, the NAND circuit 16 sends the initialization command ILAT
Is output, the OR circuits 20 to 23 always output an H level signal.

Therefore, by properly combining the AND circuit and the OR circuit, the initial data composed of 8-bit binary numbers can be arbitrarily created, and as shown in FIG. 3, the AND circuits 24-27 and the OR circuits 20-23. When combined, the initial data of “11000101” is created. Therefore, in this case, the initial data of "11000101" is stored in each of the registers 5a to 5h. Needless to say, different initial data can be set for each of the registers 5a to 5h by changing the combination of the AND circuit and the OR circuit for each of the data setting circuits 12a to 12h.

Thus, when the clock signal CLK is output by one pulse after the reset signal RST is output after the power is turned on, the initial data is stored in each of the registers 5a to 5h. Is the clock signal CLK
Although the initial data stored in the registers 5a to 5h can be referred to from the second pulse of, the initial data stored in the registers 5a to 5h needs to be changed after the initial data is stored. In some cases, the operation in that case will be described below.

When it is necessary to change the initial data stored in each of the registers 5a to 5h to new setting data DT, the microcomputer or the like sets the setting data DT (serial data).
And the serial clock SCK are output to the shift register 1, the shift register 1 inputs the setting data DT (serial data) in synchronization with the falling edge of the serial clock SCK as shown in FIG.
T is converted to parallel data and output from the Q terminal.

At this time, the microcomputer or the like needs to instruct which register should store the setting data DT output to the shift register 1.
Address signals A0, A for specifying the register storing
1, A2 and the data latch clock LAT are output to the address decoder 3. As a result, the address decoder 3 inputs the address signals A0, A1, A2 in synchronization with the falling edge of the data latch clock LAT as shown in FIG. 8, and the address signals A0, A1, A2.
The register for storing the setting data DT is recognized based on the above, and the data setting command ACLK is output to the data setting circuit corresponding to the register.

Incidentally, the address signals A0, A1 and A2 are
Since it is sent as a signal of "0" or "1", a 3-bit binary expression (A0 is the least significant bit, A1 is the intermediate bit,
A2 is regarded as the most significant bit), and address signals A0, A
The register for storing the setting data DT is recognized according to the signal states of 1 and A2 (see FIG. 9). For example, when A0 is “1” and A1 and A2 are “0”, the register 5
The setting data DT will be stored in b.

In this way, when the address decoder 3 outputs the data setting command ACLK to the data setting circuit corresponding to the register related to the change, as shown in FIG. 3, the AND circuit 18 of the data setting circuit. The data setting command ACLK is input to. Then, the AND circuit 18
As described above, when receiving the initialization command ILAT from the initialization command circuit 11 or the data setting command ACLK from the address decoder 3, the write command LOUT is output to the corresponding register to output the initial data or Instruct to store new setting data DT.

Then, the logic signal ID output from the Q terminal of the flip-flop 17 in the initialization command circuit 11
As shown in FIG. 4, the AT becomes an H level signal when the initialization command ILAT is not output from the NAND circuit 16, so that it is input to one of the input terminals of the AND circuits 24 to 27 in the data setting circuit. Is input with an H level signal. When an H level signal is input to one of the input terminals of the AND circuits 24 to 27, the AND circuit 2
The outputs of 4-27 follow the signal level input to the other input terminal, so that the AND circuits 24-27 always output the bit signal [D of the setting data DT output from the shift register 1].
(1), D (3), D (4), D (5)] will be output. That is, the initialization instruction IL from the NAND circuit 16
When AT is not output, AND circuits 24 to 27
Is always the setting data DT output from the shift register 1.
Bit signals [D (1), D (3), D (4), D
(5)] will be output.

Further, at this time, NOT is applied to one input terminal of each of the OR circuits 20 to 23 in the data setting circuit.
Since the output of the circuit 19 is input, an L level signal is input. When an L level signal is input to one of the input terminals of the OR circuits 20 to 23, the OR circuits 20 to
Since the output of 23 follows the signal level input to the other input terminal, the OR circuits 20 to 23 always operate in the shift register 1
Bit signal [D of the setting data DT output from
(0), D (2), D (6), D (7)] will be output. That is, the initialization instruction IL from the NAND circuit 16
When AT is not output, the OR circuits 20 to 23 always output the bit signals [D (0), D (2), D (6), D of the setting data DT output from the shift register 1.
(7)] will be output.

As a result, when the microcomputer or the like outputs arbitrary setting data DT or the like to the shift register 1 and the address signals A0, A1 and A2 to the address decoder 3,
The stored contents of the register specified by the address signals A0, A1, A2 can be changed to arbitrary setting data DT.

As is clear from the above, according to the first embodiment, when the power is turned on and the reset signal is received, the initialization command circuit 11 causes the data setting circuits 12a-12.
The initialization command ILAT is output to h and each register 5a ...
Since the initial data is stored in 5h, after the power is turned on, each register 5a to 5h can be processed without receiving the setting data DT from the microcomputer or the like for each register 5a to 5h. As a result, the initial data is stored in, and as a result, the microcomputer or the like can refer to the stored contents of the registers 5a to 5h immediately after the power is turned on.

Further, according to the first embodiment, D
An H level signal is output from the Q terminal of the flip-flop 14 to which an H level signal is input, and
Since the initialization command ILAT is output when the H-level signal is output from the QC terminal of the flip-flop 15 whose D terminal is connected to the Q terminal of the flip-flop 14, the reset signal RST is input. After that, when one pulse of the clock signal CLK is input, the initial data is stored in the registers 5a to 5h, and the microcomputer or the like starts to register each register 5 from the second pulse of the clock signal CLK.
It is possible to refer to the stored contents of a to 5h.

Embodiment 2 FIG. 5 is a configuration diagram showing an initialization command circuit 11 of a register device according to a second embodiment of the present invention. In the figure, 31 is a ground, and 32 is an H level signal when a reset signal RST is input to a Q terminal. While outputting from the (first output terminal) and an L level signal from the QC terminal (second output terminal),
When the clock signal CLK is input, the clock signal C
A flip-flop (first flip-flop) 33 that outputs an L-level signal from the Q terminal and an H-level signal from the QC terminal in synchronization with LK, and 33 is an H-level signal when the reset signal RST is input. While the signal is output from the Q terminal (output terminal), when the clock signal CLK is input, a signal having the same level as the signal output from the Q terminal of the flip-flop 32 is output from the Q terminal in synchronization with the clock signal CLK. It is a flip-flop (second flip-flop) for outputting.

The flip-flop 32 is QC.
A NAND circuit that outputs an initialization command ILAT when the H-level signal is output from the terminal and the flip-flop 33 outputs an H-level signal from the Q terminal, and 35 is an L level signal when the reset signal RST is input. While the signal is output from the QC terminal, when the clock signal CLK is input, a signal having a level opposite to the signal output from the Q terminal of the flip-flop 33 is output from the QC terminal as a logical signal IDAT in synchronization with the clock signal CLK. It is a flip-flop that outputs.

Next, the operation will be described. Since the configuration is the same as that of the first embodiment except the configuration of the initialization command circuit 11, only the operation of the initialization command circuit 11 will be described.
First, when the reset signal RST becomes L level due to power-on or the like, the flip-flops 32, 33, 35 of the initialization command circuit 11 are respectively reset as shown in FIG. The flip-flops 32 and 35 output an L level signal from the QC terminal while outputting an H level signal from the Q terminal.

Therefore, in this case, the L-level signal output from the QC terminal of the flip-flop 32 and the H-level signal output from the Q terminal of the flip-flop 33 are input to the input terminals of the NAND circuit 34. Because it is done
The output of the NAND circuit 34 becomes H level. For this reason,
In this case, the initialization command ILAT is not output to the data setting circuits 12a to 12h. Incidentally, the transition of the output of the NAND circuit 34 from the H level to the L level corresponds to the initialization command ILAT.

Next, the reset signal RST changes from the L level to the H level, and the clock signal CLK is sent from the microcomputer or the like.
1 pulse is output, the flip-flops 32, 33, 35 of the initialization command circuit 11 output a signal of the same level as the signal input to the D terminal from the Q terminal in synchronization with the clock signal CLK. At the same time, an opposite level signal is output from the QC terminal.

That is, since the L-level signal is always input to the D terminal of the flip-flop 32, the flip-flop 32 outputs the L-level signal from the Q terminal and the H-level signal from the QC terminal. Output. Further, the D terminal of the flip-flop 33 is connected to the Q terminal of the flip-flop 32, and before outputting one pulse of the clock signal CLK, the H-level signal is output from the Q terminal of the flip-flop 32 as described above. Therefore, the flip-flop 33 outputs an H level signal from the Q terminal. Further, the D terminal of the flip-flop 35 is connected to the Q terminal of the flip-flop 33, and before outputting one pulse of the clock signal CLK, an H-level signal is output from the Q terminal of the flip-flop 33 as described above. The flip-flop 35 is QC
The L level signal is output from the terminal.

Therefore, in this case, the H-level signal output from the QC terminal of the flip-flop 32 and the H-level signal output from the Q terminal of the flip-flop 33 are input to the input terminals of the NAND circuit 34. Because it is done
The output of the NAND circuit 34 becomes L level. For this reason,
In this case, the initialization command ILAT is output to each of the data setting circuits 12a to 12h.

In this way, the N of the initialization command circuit 11 is
When the initialization instruction ILAT is output from the AND circuit 34 to each of the data setting circuits 12a to 12h, the initial data is transferred to each of the registers 5a to 5 in the same manner as in the first embodiment.
will be stored in h.

As described above, according to the second embodiment, the H-level signal is output from the QC terminal of the flip-flop 32 in which the L-level signal is always input to the D terminal.
Moreover, when the H-level signal is output from the Q terminal of the flip-flop 33 whose D terminal is connected to the Q terminal of the flip-flop 32, the reset command RST is input because the initialization command ILAT is output. After being
When one pulse of the clock signal CLK is input, initial data is stored in the registers 5a to 5h, and the microcomputer or the like can refer to the stored contents of the registers 5a to 5h from the second pulse of the clock signal CLK. There is an effect that can be done.

[0046]

As described above, according to the first aspect of the present invention, when the data setting command is received from the data setting command means, the setting data is stored in the register specified by the address signal, while the initialization command means. When the initialization command is received from, it is configured to store the initial data in each register.Therefore, after the power is turned on, it is not necessary to receive the setting data from the microcomputer etc. for each register and store it. , The initial data will be stored in each register,
As a result, the microcomputer or the like can refer to the stored contents of each register immediately after the power is turned on.

According to the second aspect of the present invention, the first flip-flop outputs the H level signal from the output terminal,
Moreover, the second flip-flop is at the H level from the second output terminal.
When the level signal is output, the initialization command is output. Therefore, when one pulse of the clock signal is input after the reset signal is input, the initial data is stored in each register. Etc. has an effect that the stored contents of each register can be referred to from the second pulse of the clock signal.

According to the third aspect of the present invention, the first flip-flop outputs the H level signal from the second output terminal, and the second flip-flop outputs the H level signal from the output terminal.
When the level signal is output, the initialization command is output. Therefore, when one pulse of the clock signal is input after the reset signal is input, the initial data is stored in each register. Etc. has an effect that the stored contents of each register can be referred to from the second pulse of the clock signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a register device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an initialization command circuit of the register device according to the first embodiment.

FIG. 3 is a configuration diagram showing a data setting circuit of the register device according to the first embodiment.

FIG. 4 is a timing chart of signals in the initialization command circuit.

FIG. 5 is a configuration diagram showing an initialization command circuit of a register device according to a second embodiment of the present invention.

FIG. 6 is a timing chart of signals in the initialization command circuit.

FIG. 7 is a configuration diagram showing a conventional register device.

FIG. 8 is a timing chart of signals in the register device.

FIG. 9 is a table showing a register specified by an address signal.

[Explanation of symbols]

1 shift register (conversion means), 3 address decoder (data setting command means), 5a to 5h registers, 1
1 initialization command circuit (initialization command means), 12 data setting means, 14, 32 flip-flops (first flip-flops), 15, 33 flip-flops (second flip-flops), 16, 34 NAND circuits (logic) element).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Inada 3-1-1 Chuo, Itami City, Hyogo Prefecture Mitsubishi Electric Semiconductor Software Co., Ltd. (72) Inventor Miki Nishimoto 3-Chuo, Itami City, Hyogo Prefecture No. 17 Mitsubishi Electric Semiconductor Software Co., Ltd.

Claims (3)

[Claims] 1. When the setting data to be stored in the register is input as serial data, a conversion means for converting the setting data to parallel data and an address signal for specifying the register to store the setting data are input. ,
When a reset signal is input, and a data setting command unit that outputs a data setting command indicating that the setting data should be stored in the register specified by the address signal,
Initialization command means for outputting an initialization command indicating that initial data set in advance for each register should be stored;
When receiving the data setting instruction from the data setting instruction means, the setting data is stored in the register specified by the address signal, while when receiving the initialization instruction from the initialization instruction means, the initial data is stored in each register. And a register device having data setting means for performing. 2. The initialization command means outputs an L level signal from an output terminal when a reset signal is input,
When a clock signal is input, a first flip-flop that outputs an H level signal from an output terminal in synchronization with the clock signal, and when a reset signal is input, an H level signal is output from a second output terminal On the other hand, when a clock signal is input, the first signal is input in synchronization with the clock signal.
A second signal which outputs a signal of the same level as the signal output from the output terminal of the flip-flop of the first output terminal from the first output terminal and outputs a signal of the opposite level from the second output terminal
And the first flip-flop outputs an H-level signal from the output terminal, and the second flip-flop
2. The register device according to claim 1, further comprising: a logic element that outputs an initialization command when the flip-flop outputs a signal of H level from the second output terminal. 3. The initialization command means outputs a signal of H level from the first output terminal and a signal of L level from the second output terminal when the reset signal is input, and the clock signal. Is input, a first flip-flop that outputs an L level signal from the first output terminal and an H level signal from the second output terminal in synchronization with the clock signal, and a reset signal When is input, an H-level signal is output from the output terminal,
A second flip-flop that outputs a signal at the same level as the signal output from the first output terminal of the first flip-flop in synchronization with the clock signal when the clock signal is input, The first flip-flop outputs an H level signal from the second output terminal,
The register device according to claim 1, further comprising a logic element that outputs an initialization command when the second flip-flop outputs an H level signal from an output terminal.