JPS5833578B2 - Digital circuit testing methods - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing digital circuits such as IC memories.

In digital circuits, l l jl , ! of digital signals that are processed as a single unit. 1 Q
If the state of $1 changes, it may have an adverse effect on other circuit parts.

In the following, an IC memory (a memory element based on an integrated circuit) will be described as an example.

As is well known, when an address signal applied to an address input terminal of an IC memory undergoes a certain change, interference may occur in the internal circuit of the IC memory, resulting in malfunction.

Conventionally, one method for detecting such abnormalities is to generate a pattern signal (address signal) called an address combination pattern, as shown in Figure 1, and sequentially apply it to the address input terminals of the IC memory. be.

That is, the purpose of this method is to invert more + l jl , II Q'' of data input to each address terminal of the IC memory over time, thereby making interference between bits more likely to occur.

However, as shown by the rectangle in Figure 1, there are many bits that do not change in the conventional address combination pattern, and the number of changes for bits b1 and b4, for example, is different, which is sufficient to satisfy the above purpose. The drawback was that it could not be completed.

The present invention was made in order to solve the above-mentioned drawbacks of the prior art, and it generates a pattern signal in which each bit changes frequently over time and includes all required digital signal combinations. An object of the present invention is to provide a method of using the pattern signal for testing a digital circuit.

Hereinafter, the content of the present invention will be explained in detail.

FIG. 2 shows the order of words when the present invention is applied to parallel 4-bit signals.

In the figure, T is the test address, T (n3 is 1 u of bits other than the n-th bit of the test address T,
It shows that it is the inversion of "n □".

Note that n-0 means that all bits are inverted.

This address order (address signal) is the test address T
This includes all combinations of inversions of all bits and inversions other than the one bit of interest (test bit).

An embodiment of a circuit for generating the address sequence shown in FIG. 2 is shown in FIG.

In FIG. 3, 1 is a test address input terminal, 2 is a register circuit, 3 is an exclusive OR circuit, 4 is an address signal output terminal, and 5 is an external clock input terminal.

The register circuit 2 has a 10-stage configuration, each stage consisting of a 4-bit circular shift memory, and each time an external clock is applied to the terminal 5, the data in each stage is shifted 4 bits in parallel in the order of the arrows, and is enclosed in a rectangle. Data of a certain stage is read.

The data generated in this register circuit 2 alternates between a case where all bits are 091 and a case where all bits are 1'' or all bits except 1 bit are ``1'', as shown in Figure 3. appears in

In the latter case, the bit position corresponding to "+I Q +" changes in order, and includes all possible combinations.

Now, in order to operate the circuit shown in FIG. 3, test address data is applied to the test address input terminal 1, and clocks are sequentially applied to the external clock input terminal 5 at a fixed timing.

As a result, the pattern data shown in FIG. The logical OR circuit 3 takes the result, and the result appears at the address signal output terminal 4.

The data configuration of the register circuit 2 goes through one cycle every time 10 clocks are applied to the external clock input terminal 5.

Therefore, each time the data configuration of the register circuit 2 goes through one cycle, the test address data to be applied to the test address input terminal 1 is changed to "oooo", "0001", . . . 1111.
2, the address signals shown in FIG. 2 can be sequentially obtained from the address signal output terminal 4 at the timing of the clock applied to the external clock input terminal 5.

The pattern signal obtained at address signal output terminal 4 is
It is applied to the address terminal of the memory to test whether or not the IC memory is malfunctioning.

FIG. 4 shows another embodiment in which the register circuit 2 of FIG. 3 is replaced with a shift register having a serial bit configuration.

In FIG. 4, numeral 6 is a shift register, and its initial data is alternately set to 0'' and '1'' from the left end, and O'' at the right end, as shown in the figure.

To operate this circuit, test address data is applied to the test address input terminal 1 and a clock is applied to the external clock input terminal 5, as in FIG.

As a result, the contents of the shift register 6 are circularly shifted to the left every time a clock is applied to the external clock input terminal 5, and the 4-bit parallel data taken out from the predetermined bit position is used as the test signal at the test address input terminal 1. The address data and the exclusive OR circuit 3 perform exclusive OR on a bit-by-bit basis, and appear at the address signal output terminal 4.

Generally, when the circuit format shown in FIG. 4 is applied to an IC memory whose address consists of N bits, the test address input terminal 1, exclusive OR circuit 3, and address output terminal 4 are
The shift register 6 requires 2(N+1) bits.

In this case, the initial data of the shift register 6 is 1” and On.
and alternately.

However, only 1 bit is changed from 1" to "0".

The output from the shift register 6 to the exclusive OR circuit 3 is 1.
Take out every bit.

In such a circuit, by using 2 (N+1) external clocks, the combination of address signals shown in FIG. 2 can be generated for one test address data.

As explained above, in the present invention, in two temporally adjacent words, the ``1'' ?I Q !+ of each bit is not inverted for at most one bit, and under this condition, contains all word change combinations.

Therefore, by applying the obtained word to the target digital circuit, it is possible to effectively test whether a change of 1" or "0" in a certain bit has an adverse effect on other bits. Moreover, it is realized by a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of conventionally implemented digital circuit test signals, FIG. 2 is a diagram showing the order of signals generated in the present invention, and FIG. 3 is a signal generation circuit used in the present invention. FIG. 4 is a diagram showing another embodiment of the signal generating circuit used in the present invention. 1...Test address input terminal, 2...
・Register circuit, 3...Exclusive OR circuit, 4
...Address signal output terminal, 5...External clock input terminal, 6...Shift register.

Claims (1)

[Claims] 1 A register that alternately outputs data in which all bits are in the first state and data in which all bits are in the second state or all other bits except one bit are in the two states in sequence, every time a clock is applied. and an exclusive OR circuit which inputs output data of the register circuit and data consisting of a predetermined bit pattern, and the exclusive OR circuit receives any two temporally consecutive patterns. generating pattern data that includes all cases of change in which no more than one bit changes between the data;
1. A method for testing a digital circuit, which comprises applying the pattern data to a digital circuit under test and testing the presence or absence of malfunction.