JPH0253295A - Address generation circuit - Google Patents

Abstract

PURPOSE:To shorten address setting time on a memory by generating a word line and a Y selector signal from the output of a shift register on which an initial value can be set. CONSTITUTION:The initial values of the shift registers S0-S7 are set by signals A0-A7, respectively. The Y selector signals Y0-Y3, the word lines W0-W3 are connected to the Y selector signal of a memory with the output signals of the shift registers S0-S7, respectively, and the Y selector signals Y1-Y3 to the Y selector signal of the memory, and the word lines W0-W3 to the word line of the memory. In such a way, it is possible to set the address of the memory M from an input clock signal theta with the delay of the maximum two stages of the shift register, which shortens the address setting time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an address generation circuit.

[Conventional technology]

Conventionally, when sequentially selecting memory cells, an address generation circuit has a configuration shown in FIG.

In this figure, for convenience, the memory size is assumed to be 16 bits, and a circuit for reading data bit by bit is shown.

The counter is a human pulse signal, A10, All, A1.
2. A13 is an initial address setting signal, A14. A15.
A16. Al1 is a counter output signal, B1 is a counter, B2 is a Y decoder, B3 is an X decoder, YO, Yl,
Y2. Y3 is a Y selector signal, WO, Wl, W2 . W3
is a word line, D is a memory output signal, To, Tl.

T2. T3 is a transfer gate, MO, Ml.

M2. M3. M4. M5. M6. M7. M8. M9, M
IO, Mll, Ml2. Ml3. Ml4°Ml5 are memory cells.

Next, the operation of this circuit will be explained. After setting the initial address in the counter B1, the counter counts the input pulse signals, and the address signals A14, A15 . A16.
A17 is generated. This address signal is sent to Y decoder B2.
and decoded by X decoder B3, Y selector signal Y
O, Yl, Y2, Y3 and word lines WO, Wl, W2. W
3 signals were generated.

[Problem to be solved by the invention]

In the conventional address generation circuit described above, there is a maximum of four stages of delay from the input pulse signal to the counter output, and there is also a delay in the decoder, so there is a drawback that it takes a long time to set the memory address.

[Means to solve the problem]

The address generation circuit of the present invention includes, on a single semiconductor substrate, a word line, a memory cell whose address is specified by a Y selector signal, and a shift register in which an initial value can be set, and from which the output of the shift register is connected to the Generate word line and Y selector signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 and 2 are block diagrams and timing diagrams of one embodiment of the present invention.

For convenience, the memory capacity is assumed to be 16 bits, and the operation of sequentially reading data from the memory one bit at a time will be described. Φ is a clock signal that advances the address one by one, AO,
Al, A2. A3. A4゜A5. A6. A7 is a memory initial address setting signal, YO, Yl, Y2 . Y3 is a Y selector signal, WO, Wl, W2 . W3 is a memory word line, D is a memory output signal, So, SL, S2°S3. S4. S5. SS, S7 are shift registers, To
, Tl, T2. T3 is a transfer gate, Ml, M
2. M3. M4. M5. M6. M7. M8, M9. M.I.
O, Mll, Ml2. Ml3. M14 and M15 are memory cells.

Next, with reference to FIGS. 1 and 2, the operations of shift registers So, SL, S2, . S3゜S4. S5. S
6. S7 are the signals AO, A1, A2 . A3. A4
．． A5. A6. The initial value is set by A7. Y selector signals YO, Yl.

Y2. Y3. Word lines WO, Wl, W2. W3 are shift registers So, SL, S2 . S3゜S4. S5
．． S6. This is the output signal of S7, and the Y selector signal Yl,
Yl, Y2. Y3 is connected to the Y selector signal of the memory, and word lines WO, Wl, W2°W3 are connected to the word lines of the memory. In FIG. 2, SO and 84 are at high level - 8L, S2, S3 . S5, 36. This shows a case where S7 is initially set to low level.

Shift registers SO, Sl, S2. S3 is the falling edge of the clock signal Φ, and the shift registers S3 . So.

The levels of SL and S2 are determined by Y selector signals YO and Yl.

Y2. Output to Y3. Similarly, shift register S5.
S6. S7 is at the falling edge of the Y selector signal Y3, and the shift registers 84 . S5. The level of S6 is set to word lines Wl, W2 . W
Output to 3. The output of the word line WO is always at a low level after the fall of the Y selector signal Y3 because the input of the shift register S4 is always set at a low level6.
The value read from memory is a signal. In the initial state of FIG. 2, that is, when the Y selector signal YO and the word line WO are at high level, the transfer gate TO is conductive and the word line is connected to the memory cells MO, M1, M2, .
Since M3 is selected, the value of the memory cell MO is output as the memory output signal. At the falling edge of the clock signal Φ, the Y selector signal YO changes from a high level to a low level, and the Y selector signal Y1 changes from a low level to a high level. The value of M1 is output.

In this way, at the falling edge of the clock signal Φ, the memory output signal changes from the memory cell MO to the memory cell M15.
The memory values up to the point are output sequentially. At this time, the delay of the address generation circuit is only the delay of the shift register.

FIGS. 3 and 4 are block diagrams and timing diagrams of other embodiments of the present invention. The changes in FIG. 3 from the embodiment in FIG. 1 include shift register S4. S5゜S6. S7 clock signal, shift register 5O2SL, S2. The clock signal of S3 is Φ, respectively.

The input signal of shift register SO is fixed at low and low levels, and the input of S4 is connected to word line W3.
This is why I gave it a 3.

In this embodiment, when the initial values of shift register SO and shift register S4 are set to high level and the initial values of other shift registers are set to low level, the memory output signal R is set as shown in FIG. settings and the output and order of FIG. 2 can be changed.

〔Effect of the invention〕

As described above, the present invention has the effect that by configuring the address generation circuit with a shift register, the memory address can be set from the input clock signal with a maximum delay of two stages of shift registers, and the address setting time can be shortened.

A4. A5. A6. A7...Initial address setting signal,
YO, Yl, Y2. Y3. Y4--Y selector signal,
WO, Wl, W2. W3...word line, D...memory output signal, So, SL, S2. S3. S4. S5,
S6. S7...Shift register, MO, Ml.

M2. M3. M4. M5. M6. M7. M8. M9, M
IO, Mll, Ml2. Ml3. Ml4゜Ml5...
Memory cell, To, TI, T2. T3...Transfer gate.

Claims (1)

[Claims] A single semiconductor substrate includes a word line, a memory cell whose address is specified by a Y selector signal, and a shift register in which an initial value can be set, and the word line and Y selector signal are generated from the output of the shift register. address generation circuit.