JPS63202962A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve a current amplification factor, by applying one conductivity type silicon carbide (SiC) layer to an emitter region, applying the other conductivity type semiconductor layer to a base region, and applying one conductivity type region to a collector region. CONSTITUTION:A p-Si layer 2 serving as a base region is stacked on an n-SiC layer 1A serving as an emitter region. From the surface of the p-Si layer 2, n-type impurity is introduced, and a plurality of n<+> Si regions 3 as collector regions are formed. Similarly, p-type impurity is introduced and a p<+> Si region 4 as a base contact region is formed. In the p-Si layer 2, n-type impurity is introduced so as to reach the n-SiC layer 1A, and an n<+> Si region 5 is formed as a collector contact region. Apertures are made in an SiO2 layer grown on the substrate, and collector electrodes C1-C3 and a base electrode B are formed on the p<+> Si region 4 and on the n<+> Si region 5, respectively. By applying beta-SiC to a wide-gap emitter layer, the current amplification factor beta of a multi- collector bipolar transistor can be improved.

Description

[Detailed Description of the Invention] [Summary] A collector layer and a base layer are formed using a conventional semiconductor layer such as silicon (Si), and a layer having a forbidden band width (gap) larger than that of the semiconductor layer (E9=2) is formed on top of the collector layer and base layer. .2 eV) Silicon carbide (SiC
) layer and using this layer as an emitter, a wide-gap emitter bipolar transistor is used as a high-gain, high-power device. Therefore, since the multi-collector bipolar transistor used in I2L integrated circuits has a low β, we propose a new structure and manufacturing method that employs a wide gap emitter to obtain high gain.

[Industrial application field]

The present invention relates to a multi-collector bipolar transistor using SiC as a wide gap emitter and a manufacturing method.

A heterojunction bipolar transistor (01BT) is being considered as a device for the next generation of high-speed bipolar large-scale integrated circuits (VLSI).

Compared to ordinary homojunction bipolar transistors, 118T can sufficiently increase emitter injection efficiency without doping the emitter to a high concentration.

Ordinary HBTs use a mixed crystal semiconductor and are formed by controlling the gap by changing the mix crystal ratio of each layer, or the maximum operating temperature of mixed crystal HBTs is lower than that of Si, so they are not suitable for high power applications. Ta.

On the other hand, there is a wide gap emitter transistor in which the emitter of a conventional silicon (St) element is made of SiC that can withstand high temperatures.

The main advantages of wide-gap emitters are that they can increase emitter injection efficiency and lower base resistance.

[Conventional technology]

FIG. 4 is a sectional view of a conventional multi-collector bipolar transistor.

In the figure, on the n-3i substrate 1 which becomes the emitter region,
A p-5i layer 2 serving as a base region is epitaxially grown.

N-type impurities are diffused from the surface of the p-3i layer 2 to form a plurality of n'-S i regions 3 as collector regions, and p-type impurities are diffused to form p''-S i regions 3 as base contact regions.
5i region 4 is formed.

An n-type impurity is diffused into the p-3i layer 2 so as to reach the n-3i substrate 1 to form an n-type impurity as a collector contact region.
-S i 1iJj region 5 is formed.

The silicon dioxide (SiO□) layer 6 grown on the substrate is opened, and a collector electrode C1 is formed on each n''-3i region 3.
, C2, and C3, the base electrode B is on the p''-3t region 4.
, n・-3i? A collector electrode C is formed on the iJj region 5.

[Problem that the invention seeks to solve]

In the multi-collector bipolar transistor having the above structure, a current amplification factor β of only about 2 to 5 can be obtained.

[Means for solving problems]

The above problem can be solved by laminating a semiconductor layer of another conductivity type on a silicon carbide layer of one conductivity type, and forming a plurality of regions of one conductivity type on the surface of the semiconductor layer of another conductivity type. A bipolar transistor in which the silicon carbide layer is an emitter region, the other conductivity type semiconductor layer is a base region, and the one conductivity type region is a collector region; a semiconductor layer of the other conductivity type, forming a semiconductor layer of the other conductivity type by thinning the semiconductor substrate of the other conductivity type, and forming a plurality of regions of one conductivity type and regions of the other conductivity type on the surface of the semiconductor layer of the other conductivity type. This is achieved by a method of manufacturing a bipolar transistor including.

[Effect]

The present invention uses β-5iC as a wide gear tube emitter layer to improve device characteristics.

SiC consists of hexagonal system α-3iC and cubic system β-3
iC, but S is used for wide gap emitter layer formation.
β-3iC, which is the same product as i, is used.

Crystal growth of SiC generally requires high-temperature growth and is difficult, but the applicant has developed a technique for growing single-crystal SiC in a vapor phase at about 1000°C and under a reduced pressure of about 200 Pa.

In addition, the applicant has also developed a single-crystal SiC hall (Hall).
) It was experimentally confirmed that the mobility is the same as or higher than that of Si, and that the rectification ratio of the SiC/St heterojunction is large, and that the diffusion current mainly flows through the junction.

From these results, it was found that the single crystal β-3iC emitter bipolar transistor has high emitter efficiency, in other words, low base resistance, and is suitable as a high-speed bipolar transistor for VLSI.

FIG. 3 is a diagram showing the energy hand structure of a SiC wide emitter bipolar transistor.

In the figure, Ec, EV, and EF indicate the lower end of the conduction band, the upper end of the valence band, and the Fermi level, respectively, and the flow of electrons indicated by black circles and holes indicated by white circles are indicated by arrows.

The arrows schematically show how holes are difficult to be injected into the emitter due to the barrier caused by the wide gap in the emitter region.

As a result, the base current is reduced and the emitter injection efficiency is increased.

The present invention proposes a structure in which the above-mentioned wide emitter can be adapted to a multi-collector transistor, and aims to increase the gain.

〔Example〕

FIG. 1 is a cross-sectional view of a multi-collector bipolar transistor according to the present invention.

The figure shows an example of an npn transistor.

In the figure, a p-3i layer 2, which will become a base region, is laminated on an n-5i CJILA, which will become an emitter region.

N-type impurities are introduced from the surface of the p-5i layer 2 to form a plurality of n''-3i regions 3 as collector regions, and n-type impurities are introduced to form p+-3t regions 4 as base contact regions. .

p-5i layer 2, n-5i (: n so as to reach layer IA)
type impurities are introduced to form the collector contact region.
”-3t region 5 is formed.

The Si03 layer 6 grown on the substrate is opened, collector electrodes CI, C2, and C3 are placed on the n''-3i region 3, base electrode B is placed on the p''-3i region 4, and a base electrode B is placed on the n''-5i region 4.
A collector electrode C is formed on the region 5.

FIGS. 2(1) and 2(2) are cross-sectional views illustrating the manufacturing process of a multi-collector bipolar transistor according to the present invention.

In Figure 2 (1), boron (B) is 5E17 to 5B1
On the 8cm-3 doped p-3i substrate 2', a 0.3 μm thick n-
A 3iC layer 18 and a sufficiently thick polycrystalline silicon (poly-Si) layer 7 of high concentration n-type are successively grown by the usual CVD method.

The LPCVD conditions for β-5iC include trichlorosilane (SiHCL+) and propane (C311o) as source gases.
Using hydrogen (+12) as a carrier gas, these
Freeze pressure is applied to 00 Pa and thermal decomposition is performed at 1000°C.

Note that the n-5iC layer IA is doped with phosphorus (P) at lB17 to IE18 cm-' during growth or by ion implantation after growth to make it n-type.

In FIG. 2 (2), the p-5i substrate 2' is polished and etched to form a p-5i substrate 2' with a thickness of 0.5 to 1.0 pm.
Formed in i-layer 2.

Next, resist 1 ~ ion implantation masking the pattern,
Alternatively, by doping P with IE17 to IE18 cm-3, the p-3i layer 2 is doped with n' to a depth of 0.3 to 0.5 pm.
-5i region 3 and n' at a depth reaching the n-3iC layer IA.
-5i region 5 is formed.

Next, a SiO□ layer 6 with a thickness of 4000 layers is grown on the entire surface of the p-3i layer 2, and this layer is opened to form an n"-5i
Collector electrodes C2 and C3 are on region 3, base electrode B is on p+-5i region 4, and n''-
A collector electrode C is formed on the S i region 5 .

〔Effect of the invention〕

As explained in detail above, according to the present invention, the current amplification factor β of the multi-collector bipolar transistor is 2
Although only about ~5 was obtained, it can be increased by 10 to 100 times.

Furthermore, an effect similar to that of a normal β-5iC wide gap emitter high polar transistor can be obtained.

That is, the action of the wide gear tube emitter makes it possible to reduce the operating current.

In addition, the current density flowing through the aluminum (AI) wiring can be reduced by lowering the operating current.

Therefore, the A1 layer can be made thinner and the step difference on the substrate surface can be reduced, so that the requirements for the interlayer insulating layer are relaxed and it is suitable for high integration.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a multi-collector bipolar transistor according to the present invention, Fig. 2 (1) and (2) are cross-sectional views explaining the manufacturing process of a multi-collector bipolar transistor according to the present invention, and Fig. 3 is a SiC wide FIG. 4 is a cross-sectional view of a conventional multi-collector bipolar transistor. In the figure, 1 is a silicon carbide layer of one conductivity type, which is an n-5iC layer (emitter region), 2 is a semiconductor layer of another conductivity type, which is a p-5i layer (base region), and 3 is a semiconductor layer of one conductivity type, which is an n''-3T layer. region (collector region), 4 is a base contact region, p'''-5i region 5 is a collector contact region, n''-3i region, 6 is a SiO□ layer, 7 is a polySt layer

Claims (2)

[Claims] (1) A semiconductor layer of another conductivity type is laminated on a silicon carbide layer of one conductivity type, and a plurality of regions of one conductivity type are formed on the surface of the semiconductor layer of one conductivity type, and the silicon carbide layer of one conductivity type is laminated. A bipolar transistor comprising an emitter region, a semiconductor layer of another conductivity type as a base region, and a region of one conductivity type as a collector region. (2) A silicon carbide layer of one conductivity type and a polycrystalline silicon layer of one conductivity type are sequentially grown on a semiconductor substrate of another conductivity type, and the semiconductor substrate of the other conductivity type is thinned to form a semiconductor layer of the other conductivity type; A method for manufacturing a bipolar transistor, comprising the step of forming a plurality of regions of one conductivity type and regions of another conductivity type on a surface of a conductivity type semiconductor layer.