JPS6041269A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS6041269A
JPS6041269A JP59051687A JP5168784A JPS6041269A JP S6041269 A JPS6041269 A JP S6041269A JP 59051687 A JP59051687 A JP 59051687A JP 5168784 A JP5168784 A JP 5168784A JP S6041269 A JPS6041269 A JP S6041269A
Authority
JP
Japan
Prior art keywords
semiconductor
junction
semiconductors
single crystal
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59051687A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP59051687A priority Critical patent/JPS6041269A/en
Publication of JPS6041269A publication Critical patent/JPS6041269A/en
Priority to JP4209437A priority patent/JPH05304308A/en
Priority to JP4345097A priority patent/JP2626653B2/en
Priority claimed from JP4345097A external-priority patent/JP2626653B2/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Photovoltaic Devices (AREA)
  • Photoreceptors In Electrophotography (AREA)

Abstract

PURPOSE:To obtain a continuous junction in a nonsingle crystal semiconductor device having a junction by adding carbon, nitrogen or oxygen to at least one of semiconductor layers. CONSTITUTION:A semiconductor device in which nonsingle crystal semiconductor layers made of silicon, germanium or silicon carbide and having 0.2-200atom% of hydrogen or halogen element are laminated, and PIN, PNP, NPN, NIN, or PIP junction is formed, carbon, nitrogen or oxygen is uniformly diffused and added to at least one of the layers. Since such an element is added, the semiconductor material has a wide energy band width, and a junction in which adjacent semiconductors are continued is composed.

Description

【発明の詳細な説明】 本発明は、−導電型を有する非単結晶、即ちアモルファ
スまたは多結晶の非単結晶半導体を三層積層し、このう
ちの少なくとも1つの、この半導体を構成する半導体材
料にエネルギーバンドを変更しろる添加物を添加し、か
つそれらの層によりPIN、 PNP、 NPN、 N
INまたはPIF接合を有せしめたアモルファスまたは
多結晶の如き非単結晶の半導体を設けることに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is characterized in that - non-single-crystal semiconductors having a conductivity type, that is, amorphous or polycrystalline semiconductors, are stacked in three layers, and at least one of them is a semiconductor material constituting this semiconductor. PIN, PNP, NPN, N
The present invention relates to providing non-monocrystalline semiconductors, such as amorphous or polycrystalline, with IN or PIF junctions.

本発明は珪素、ゲルマニューム、炭化珪素の如きアモル
ファスまたは多結晶の半導体と、炭素、窒素または酸素
を添加物として、半導体中に十分均等に分散させて添加
した非単結晶構造の半導体を設け、異なる導電型を有す
る半導体を互いに隣接させたこの境界またはその近傍に
おいて、少なくとも1つの非単結晶半導体がその隣の半
導体と(2) エネルギハンドを異ならしめ、かつそれぞれのエネルギ
ーバンド間の遷移を連続的に行わしめることに関する。
The present invention provides an amorphous or polycrystalline semiconductor such as silicon, germanium, or silicon carbide, and a non-single-crystalline semiconductor in which carbon, nitrogen, or oxygen is added as an additive sufficiently uniformly dispersed in the semiconductor. At or near this boundary where semiconductors having conductivity types are adjacent to each other, at least one non-single crystal semiconductor has (2) different energy hands from the adjacent semiconductor, and the transition between each energy band is continuous. Concerning what is done.

さらにこの境界またはその近傍にてPNまたはPIまた
はNIの接合部を設け、結果として本発明構造のPIN
、 PNP、 NPN、 NINまたはpH”接合を設
け、この接合部に光照射をすることにより、光起電力を
発生せしめることに関する。
Furthermore, a PN or PI or NI junction is provided at or near this boundary, resulting in a PIN of the structure of the present invention.
, PNP, NPN, NIN or pH" junction and irradiating this junction with light to generate a photovoltaic force.

従来、異なったエネルギーバンドを有する半導体の境界
を互いに接せしめた場合、その境界ではいわゆるヘテロ
接合(hetelo−junction)を構成してい
た。例えば、GaPとGaAsとを接合させた場合、共
にそれらは単結晶であるため、この2つのエネルギーギ
ャップまたはエネルギギャップ(以下Egという)の界
面には第1図に見られる如く不整合の階段型へテロ接合
ができてしまった。不整合のため、他の1列えばGa 
Al八へ (1)、GaAs (2)の接合には伝導帯
(8)にノツチ(3〉1価電子帯(9)に飛び(4)が
発生し、加えて境界では界面準位(5)が発生してしま
った。この界面準位(Interface 5tate
sともいう〉(以下Nsという)の(3) ためにこの接合部で電子またはホールのキャリアがこの
Nsを会して再結合をして消滅しまった。
Conventionally, when semiconductors having different energy bands are brought into contact with each other, a so-called heterojunction is formed at the boundary. For example, when GaP and GaAs are bonded together, since they are both single crystals, the interface between the two energy gaps or energy gaps (hereinafter referred to as Eg) has a mismatched step shape as seen in Figure 1. A heterojunction has been formed. Due to inconsistency, the other row is Ga
In the junction of Al8 (1) and GaAs (2), a notch (3) in the conduction band (8) and a jump (4) in the valence band (9) occur, and in addition, an interface state (5) occurs at the boundary. ) has occurred.This interface state (Interface 5tate
s (hereinafter referred to as Ns) (3) Therefore, electron or hole carriers meet this Ns at this junction, recombine, and disappear.

その結果、キャリアのライフタイムを減少させ、さらに
この接合を用いて特定の作用例えば光起電力を発生せし
めようとした場合、光励起された電荷が光起電力を発生
する前に消滅してしまうという大きな欠点があった。さ
らに半導体のPN接合ダイオードの特性を得んとしてし
まった場合、逆方向対性の耐圧が弱くソフトダイオード
になってしまった。第1図(A>は71−P接合の場合
であるが、N−N接合である第1図(B)においては、
スパイク(6)がNs(7)に加えて発生し、多数キャ
リアである電子の移動をさまたげてしまうおおきな欠点
があった。本発明はかかるノ・ノチ、飛び、スパイクの
発生を防止する。即ち、この接合部においてエネルギー
バンドが連続的に変化せしめることを大きな目的とする
。さらにこれまでヘテロ接合に必然的に界面での結晶格
子不整のために存在していた不対結合手、結晶欠陥に起
因するNsの発生を本発明は除去またはきわめて少なく
せ(4) しめたことを特徴とする。かかる構造即ち連続的な接合
をエネルギーバンド的な観点において有していることに
より、このエネルギーバンドの差を利用する新しい半導
体装置の展開がきわめて飛躍的に可能となった。
As a result, the lifetime of carriers is reduced, and when an attempt is made to use this junction to generate a specific effect, such as photovoltaic force, the photo-excited charge will disappear before generating photovoltaic force. There was a big drawback. Furthermore, when attempting to obtain the characteristics of a semiconductor PN junction diode, the reverse pairing breakdown voltage is weak and the diode becomes a soft diode. Figure 1 (A> is for a 71-P junction, but in Figure 1 (B) which is an N-N junction,
A major drawback was that spikes (6) were generated in addition to Ns (7), which hindered the movement of electrons, which were majority carriers. The present invention prevents the occurrence of such nicks, jumps, and spikes. That is, a major objective is to cause the energy band to change continuously at this junction. Furthermore, the present invention has eliminated or extremely reduced the generation of Ns caused by dangling bonds and crystal defects, which have conventionally existed in heterojunctions due to crystal lattice misalignment at the interface (4). It is characterized by By having such a structure, that is, a continuous junction from an energy band perspective, it has become possible to develop new semiconductor devices that make use of this energy band difference.

以下に本発明を実施例に基づいて説明する。The present invention will be explained below based on examples.

本発明は一導電型を有する珪素、ゲルマニューム、炭化
珪素のごときアモルファス(純粋のアモルファスまたは
5〜100人のショートレンジオーダーでの多結晶)ま
たは多結晶構造を有する半導体C以下これらを総称して
非単結晶半導体という)またはこれに炭素、酸素または
窒素などを均等に分散して添加せしめることを本発明の
基礎とする。
The present invention applies to semiconductors having amorphous (pure amorphous or polycrystalline in the order of 5 to 100 short range) or polycrystalline structures such as silicon, germanium, and silicon carbide having one conductivity type. The basis of the present invention is to uniformly disperse and add carbon, oxygen, nitrogen, etc.

また本発明における均等な分散とは、添加物の量子論的
な波動が互いに局部的に相互作用を生せしめる方向にな
ることをいう。
Furthermore, uniform dispersion in the present invention refers to a direction in which the quantum theoretical waves of the additives locally interact with each other.

金属、半導体または絶縁体さらにまたはガラスまたはセ
ラミックのごとき絶縁体−Fに金属膜等を一部または全
部に被膜化された複合の基板上に被膜を構成させた時、
半導体となる材料、例えば珪(5) 素をシラン、ジクロールシランその他の珪化物気体を用
いて被膜として形成せしめる。このため石英等の耐熱ガ
ラスまたはステンレスの反応炉の入り口側にシラン、ジ
クロールシランの如き珪化物気体と水素の如きキャリア
ガスと、さらにリン、ヒ素、ボロンの如き半導体中で導
電性を決める不純物をフォスヒン、アルシン、ジボラン
により導入できるようにした。加えてメタン、アンモニ
ア、酸素等の炭化物、窒化物、酸化物気体を混入できる
ようにした。また排気は真空ポンプを用い、反応炉内を
0.001torrまで真空引きができるようにした。
When a film is formed on a composite substrate partially or completely coated with a metal film, etc. on a metal, semiconductor, insulator, or insulator-F such as glass or ceramic,
A material to be a semiconductor, such as silicon (5) element, is formed as a film using silane, dichlorosilane, or other silicide gas. For this reason, a silicide gas such as silane or dichlorosilane and a carrier gas such as hydrogen are placed on the entrance side of a reactor made of heat-resistant glass such as quartz or stainless steel, and impurities that determine conductivity in the semiconductor such as phosphorus, arsenic, and boron. can be introduced using phoshine, arsine, and diborane. In addition, carbide, nitride, and oxide gases such as methane, ammonia, and oxygen can be mixed in. In addition, a vacuum pump was used for evacuation, so that the inside of the reactor could be evacuated to 0.001 torr.

反応炉内に基板をサセプターにて保持して入れ、反応炉
を0.1 =10torrに真空引きをし、その基板に
対し1〜50MHzの高周波加熱またはそれと輻射加熱
とを併用して加え、さらに反応性気体を励起または分解
した。これら反応性気体は基板上に被膜となって形成さ
れる。この際この被膜は基板の温度より室温−500℃
まではアモルファスが、また350℃−900℃では多
結晶構造となった。
The substrate is held in a susceptor and put into the reactor, the reactor is evacuated to 0.1 = 10 torr, and the substrate is subjected to high frequency heating of 1 to 50 MHz or a combination of it and radiation heating, and then Excited or decomposed a reactive gas. These reactive gases are formed as a film on the substrate. At this time, this film is kept at room temperature -500°C below the temperature of the substrate.
The structure was amorphous at temperatures up to 350° C. and polycrystalline at 350° C. to 900° C.

基板が単結晶を有し、またその上の被膜が900(6) ℃以上ではエピタキシャル成長される場合は単結晶にな
るが、実験的にこれらの単結晶半導体が本発明の構造を
有することは不可能であった。本発明は非単結晶の被膜
を用いることを第1の特徴としている。この非単結晶被
膜に対し、リン、ヒ素の如き半導体中でN型導電型を呈
する不純物を1014〜1022cm−3の濃度にフォ
スヒン(PH3>、アルシン(Asllt)を利用して
混入させると、いわゆるN型半導体が作られる。また他
方、ジボラン(B4■t )を同様の濃度用いて添加す
ると、P型の半導体になる。さらにこれらの不純物を全
く添加しないと、真性または装置のバンクグラウンドレ
ベルの不純物の混入によるいわゆる実質的に真性の半導
体になった。この非単結晶被膜には半導体を構成する材
料いわゆる珪素以外に水素、重水素または塩素の如きハ
ロゲン元素が0.2〜200原子%の濃度で添加されて
いる。
If the substrate has a single crystal and the film on it is epitaxially grown at 900(6)°C or higher, it will become a single crystal, but it has been experimentally proven that these single crystal semiconductors do not have the structure of the present invention. It was possible. The first feature of the present invention is the use of a non-single crystal coating. When impurities exhibiting N-type conductivity in semiconductors such as phosphorus and arsenic are mixed into this non-single crystal film at a concentration of 1014 to 1022 cm-3 using phosphin (PH3> and arsine (Asllt)), the so-called On the other hand, adding diborane (B4■t) at a similar concentration results in a P-type semiconductor.Furthermore, if these impurities are not added at all, the intrinsic or device bank ground level It has become a so-called essentially intrinsic semiconductor due to the mixing of impurities.This non-single-crystal film contains 0.2 to 200 at. It is added in concentration.

これらは珪素の不対結合手と結合して再結合中心の発生
を抑止し、電気的には中和(不活性)する作用を有する
。この水素またはハロゲン元素の(7) 半導体膜の形成と同時または被膜形成後の添加は本発明
を工業的に実用化するためのきわめて重要な要素であっ
た。本発明において、再結合中心中和用の不純物の添加
は電気的に反応性気体を活性化と同時に添加される水素
またはハロゲン元素を活性化することにより成就する方
法を用いた。さらに本発明の実施例においては、炭素、
窒素、酸素を均質に分散して半導体中に添加した。炭素
はCI、、C1■Cを用いた。窒素はアンモニア(NH
,)、ヒドラジン(Ni2)を、また酸素はHO,また
はOLとした。これら混合物としてはN、O,Not 
IcH,ORその他のアルコール類、C0LICO等を
水素等のキャリアガスを用いた反応炉内に導入し、さら
に添加物を窒素と酸素または炭素と酸素というように2
種類以上添加してもよい。酸素、窒素等を単結晶の半導
体被膜形成後、あとから添加しようとすると、酸化珪素
(Eg=8eV )または窒化珪素(Eg=5.5eV
)になってしまい、絶縁物でしかなかった。しかしこれ
らの添加物を珪素被膜作製と同時に電気的、または電気
と熱とを併用して実施することに(8) より添加すると、これらの添加物の化学量論比に応じて
半導体は1.1eVから3eV (SiC>、5.5e
V(Si1 N4 )、 8eV (Sift )の中
間の値を得ることができた。この被膜のEgはフォトル
ミネッセンスまたは光励起法により測定した。
These have the effect of binding to dangling bonds of silicon, suppressing the generation of recombination centers, and electrically neutralizing (inactivating) them. Addition of the hydrogen or halogen element (7) at the same time as the formation of the semiconductor film or after the film formation was an extremely important element for commercializing the present invention industrially. In the present invention, the addition of an impurity for neutralizing the recombination center is achieved by electrically activating a reactive gas and simultaneously activating the added hydrogen or halogen element. Further, in embodiments of the present invention, carbon,
Nitrogen and oxygen were uniformly dispersed and added to the semiconductor. The carbon used was CI, C1■C. Nitrogen is ammonia (NH
), hydrazine (Ni2), and oxygen was HO or OL. These mixtures include N, O, Not
IcH, OR, other alcohols, COLICO, etc. are introduced into a reactor using a carrier gas such as hydrogen, and additives are added such as nitrogen and oxygen or carbon and oxygen.
More than one type may be added. If you try to add oxygen, nitrogen, etc. after forming a single crystal semiconductor film, silicon oxide (Eg = 8eV) or silicon nitride (Eg = 5.5eV)
) and was nothing more than an insulator. However, if these additives are added electrically or using a combination of electricity and heat (8) at the same time as the silicon film is formed, the semiconductor becomes 1. 1eV to 3eV (SiC>, 5.5e
An intermediate value between V (Si1 N4 ) and 8 eV (Sift) could be obtained. The Eg of this film was measured by photoluminescence or optical excitation method.

このEgは2つの半導体において共に非単結晶構造を有
しているため、界面のみに単結晶のへテロ接合で知られ
る如き特定のNsが存在することがなく、さらにエネル
ギーバンドは伝導帯、価電子帯ともにある独立階段的な
連続性を、またはなめらかな連続性を有して形成させる
ことができた。
Since this Eg has a non-single-crystal structure in both semiconductors, there is no specific Ns only at the interface, as is known in single-crystal heterojunctions, and the energy band is the conduction band and the valence band. Both electronic bands were able to form independent step-like continuity or smooth continuity.

この異なる接合部でのEgの程度は、被膜形成速度0.
1〜10μ/分と調節し、加えて添加物のドープ量を0
N10FFに調整または連続的に階段を追って調整する
ことにより成就した。しかし重要なことは、この異なる
!!gの境界またはその近傍においては、製造方法にも
起因するが、単結晶半導体のへテロ接合に見られる格子
不整合等によるNsは発生せず、またEgのエッヂであ
る伝導帯および価電子帯にはノツチ、スパイク等は存在
しなかった。
The degree of Eg at these different joints is determined by the film formation rate of 0.
The doping rate was adjusted to 1 to 10 μ/min, and the doping amount of the additive was adjusted to 0.
This was achieved by adjusting to N10FF or continuously adjusting the steps. But the important thing is that this is different! ! At or near the boundary of Eg, Ns does not occur due to lattice mismatch, etc. seen in heterojunctions of single crystal semiconductors, although this may also be due to the manufacturing method, and the conduction band and valence band, which are the edges of Eg, do not occur. There were no notches, spikes, etc.

(9) または実質的に存在しないことが判明した。これはEg
を水素またはハロゲン元素の不純物に添加するに加えて
化学量論比に従って決めていることによるものと推察さ
れる。以上は減圧CVO<化学蒸着)法またはグロー放
電法を用いた実施例である。
(9) or was found to be substantially non-existent. This is Eg
This is presumed to be due to the addition of hydrogen or halogen element impurities and the fact that they are determined according to the stoichiometric ratio. The above is an example using a low pressure CVO (chemical vapor deposition) method or a glow discharge method.

本発明において異なるEgを有せしめる2つの半導体の
一方が、純粋の半導体であって他方が添加物の加えられ
た半導体のみである必要はない。いずれにおいても同種
の添加物がその量を変えて例えば一方が1015、.1
018 C111−3他方が0.01〜30%といった
ように添加されていれば、本発明を実施することができ
る。さらにまた一方は、炭素を10v&〜10”cm’
例えば5〜10%と添加物の種類を変えて行えばよいこ
とはいうまでもない。以上の理論および実施方法および
その結果より明らかなごとく、本発明は半導体の動作に
きわめて重要な接合部またはその近傍で異なるEgの材
料を接合することにより発生する従来期待しない要素で
あるノツチ、スパイク等と界面固有のNsとを排除し、
いわゆる異なる格子定数の材料を接合することに本質的
に(10) 帰因する要素を排除したことにある。このためミクロな
意味での格子不整を排除した非単結晶構造の半導体であ
ることが本発明の重要な要旨である。
In the present invention, it is not necessary that one of the two semiconductors having different Eg be a pure semiconductor and the other only a semiconductor to which additives have been added. In both cases, the same type of additive is used in different amounts, for example, one is 1015, . 1
018 C111-3 If the other is added in an amount of 0.01 to 30%, the present invention can be carried out. Furthermore, one of the carbon
It goes without saying that it is sufficient to change the type of additive, for example, from 5 to 10%. As is clear from the above-mentioned theory, implementation method, and results, the present invention is effective against notches and spikes, which are conventionally unexpected elements that occur when materials of different Eg are joined at or near the junction, which is extremely important for the operation of semiconductors. etc. and the interface-specific Ns are eliminated,
This is essentially due to the elimination of (10) factors that are attributable to the joining of materials with different lattice constants. Therefore, an important gist of the present invention is a semiconductor having a non-single crystal structure that eliminates lattice misalignment in a microscopic sense.

かかる非単結晶構造であって、かつ再結合中心を水素ま
たはハロゲンにより中和したため、化学量論比に応じて
エネルギーギャップを連続的に変えるいわゆる連続接合
を有する半導体装置を完成させることができた。
By having such a non-single crystal structure and neutralizing the recombination center with hydrogen or halogen, it was possible to complete a semiconductor device having a so-called continuous junction, in which the energy gap is continuously changed according to the stoichiometric ratio. .

第2図は本発明に至る2つの非単結晶半導体におけるE
gを変えた実施例である。第2図(A)は接合部が境界
となり、非単結晶半導体(11)はN型でW (WID
E) Eg (広いエネルギーギャップ)、非単結晶半
導体(13)はL (NALI、ow) 17g (狭
いエネルギーギャップ)のP型である。第2図(B)は
同種のP型導電型であり、非単結晶半導体(11)がW
−t+gでありまた非単結晶半導体(14)はL −E
gである。さらにまた第2図< c )、(D )はそ
れぞれPP接合、PN接合である。第2図(E)はなめ
らかに連続して設けられたNP接合を構成している。
Figure 2 shows E in two non-single crystal semiconductors that led to the present invention.
This is an example in which g is changed. In Figure 2 (A), the junction is the boundary, and the non-single crystal semiconductor (11) is N type and W (WID
E) Eg (wide energy gap), the non-single crystal semiconductor (13) is of P type with L (NALI, ow) 17g (narrow energy gap). Figure 2 (B) shows the same type of P conductivity type, in which the non-single crystal semiconductor (11) is W.
-t+g and the non-single crystal semiconductor (14) is L -E
It is g. Furthermore, FIG. 2<c) and (D) are a PP junction and a PN junction, respectively. FIG. 2(E) shows a smoothly continuous NP junction.

第2図(F)は段階的なNP接合を構成している。FIG. 2(F) shows a stepwise NP junction.

(11) 第3図は本発明の構造の実施例をエネルギバンド中で示
したものである。即ちこの発明はPI、NIまたはPN
接合を2つ有せしめ、PNP接合、NPN接合、PIN
接合、pH’接合およびNIN接合を導電型で有し、か
つ3つの半導体のうちの少なくとも隣の半導体に比べて
異なるエネルギバンド中を有したものである。
(11) FIG. 3 shows an embodiment of the structure of the present invention in energy bands. That is, this invention applies to PI, NI or PN.
Have two junctions, PNP junction, NPN junction, PIN
It has a conductivity type of a junction, a pH' junction, and an NIN junction, and has a different energy band than at least the adjacent semiconductor among the three semiconductors.

第3図(A)はW (Eg、) L (Egt ) W
(Eg、)のNPN l−ランジスタである。LのEg
、のP型のベース領域で、Egにより決められた再結合
を促進させることができる。即ちエミッタ(30〉、ベ
ース(31)、コレクタ(32)において、電子の少数
キャリアは[!g、よりEgLに(15)を容易にドリ
フトできるが、逆方向拡散はホールが(15’>の障壁
のためふさがれる。その結果、周波数特性に優れたバイ
ポーラトランジスタとすることができた。
Figure 3 (A) shows W (Eg,) L (Egt) W
(Eg,) is an NPN l-transistor. L's Eg
The P-type base region of , can promote Eg-determined recombination. That is, in the emitter (30〉, base (31), and collector (32), the minority carriers of electrons can easily drift (15) to EgL from [!g, but the reverse diffusion causes holes to This results in a bipolar transistor with excellent frequency characteristics.

第3図(B)はL (Eg+ ) W (Egz ) 
、L(Eg7)のPNP )ランジスタである。即ち、
ソース(33)、ドレイン(35)間もその不純物を(
34)で混合することなく、この外側に設けられたチャ
(12) ネル形成領域により制御された電流を流すことができた
。第3図(C)はL−W−LのNIPのNTr’構成で
ある。
Figure 3 (B) is L (Eg+) W (Egz)
, L (Eg7) PNP) transistor. That is,
The impurities are also removed between the source (33) and drain (35) (
A controlled current could be passed through the channel forming region (12) provided on the outside without mixing in the channel (34). FIG. 3(C) shows the NTr' configuration of the L-W-L NIP.

第3図(D)はW−V/−Lのl”IN構成である。FIG. 3(D) shows a W-V/-L l''IN configuration.

これはW値により光を照射せしめるいわゆるフォトセル
または太陽電池に対して高効率(15〜30%)の変換
効率を期待できる。入射光側のP層(36)が広いEg
であるため、ここでの光損失が少な(、活性層の1層(
37)で有効に光電変換を行うことができる。加えて、
この発生したキャリアも電子(40)、ホール(40’
)も連続接合のため、接合面での障害もなく、N (3
8)、 P (36)にドリフトさせることができた。
This can be expected to provide high conversion efficiency (15 to 30%) for so-called photocells or solar cells that emit light depending on the W value. The P layer (36) on the incident light side has a wide Eg
Therefore, the optical loss here is small (, one layer of the active layer (
37) allows effective photoelectric conversion. In addition,
These generated carriers are also electrons (40) and holes (40').
) is also a continuous bond, so there is no failure on the bonding surface, and N (3
8), it was possible to drift P (36).

加えて電子(40つのP (36)への逆流を防ぐ効果
もあり、効率の向」二が著しかった。
In addition, it had the effect of preventing the backflow of electrons (40 P (36)), resulting in a significant improvement in efficiency.

第3図(E)はW−W−LのNPN、 (F)はL−W
−−WのPNP )ランジスタである。
Figure 3 (E) is W-W-L NPN, (F) is L-W
--W PNP) transistor.

第3図(E )、< F )は第3図(A)と同様に超
高周波特性の向上に有効であった。
FIG. 3(E) and <F) were effective in improving the ultra-high frequency characteristics as in FIG. 3(A).

さらに以下にその具体例を示す。Further specific examples are shown below.

(13) 具体例1 この具体例は第3図(D)の構造である。(13) Specific example 1 This specific example has the structure shown in FIG. 3(D).

ガラス上の電極上にP型非単結晶層(36)を炭素が5
〜30原子%になるようにシランとメタンとジボランと
を混合しグロー放電法で形成した。さらに炭素を1〜5
%添加されるようシランとメタンとのグロー放電法によ
り■型非単結晶層(37)を形成した。次にシランとフ
ォスヒンとを混合し、N型非単結晶半導体層(38)を
形成し、2つの接合を設けた。最後にアルミニューム電
極を設け、第3図(D)の構造として、この太陽電池で
変換効率を測定したところ、2.07%(開放電圧0.
57V。
A P-type non-single crystal layer (36) is formed on the electrode on the glass with 5 carbon atoms.
Silane, methane, and diborane were mixed to a concentration of ~30 at % and formed by a glow discharge method. Add 1 to 5 carbons
A ■-type non-single-crystal layer (37) was formed by a glow discharge method using silane and methane so that the silane and methane were added at a concentration of 5%. Next, silane and phosphine were mixed to form an N-type non-single crystal semiconductor layer (38), and two junctions were provided. Finally, an aluminum electrode was provided, and the conversion efficiency of this solar cell was measured with the structure shown in Figure 3 (D), and was found to be 2.07% (open circuit voltage 0.
57V.

短絡電流0.95mA、曲線因子0.387.面積0.
10cd、直列抵抗353Ω、並列抵抗2089Ω)を
得た。
Short circuit current 0.95mA, fill factor 0.387. Area 0.
10 cd, series resistance 353Ω, parallel resistance 2089Ω).

具体例2 この具体例は第3図(A)の構造であるセラミック上に
金属膜の電極を設け、この上に非単結晶半導体層(20
)をシランとメタンとフォスヒンとの混合によりグロー
放電法でP型非単結晶半導体層(31)をシランとジボ
ランとの混合気体により(14) N型非単結晶半導体N(32)をシランとメタンとフォ
スヒンとの混合によりfJi層して形成した。このNP
N l−ランジスタでN型Jtij (20)を2.3
eV、 P型層(31)を1.5eν、N型層(31)
を2.OeVをエネルギバンドlJで有している。その
周波数特性はエミッタ、ベース間1.5V、ヘース、コ
レクタ間10Vにて12MIIzの高い周波数特性を示
す。
Specific Example 2 In this specific example, a metal film electrode is provided on a ceramic having the structure shown in FIG. 3(A), and a non-single crystal semiconductor layer (20
) by a glow discharge method using a mixture of silane, methane, and phosphin (14) and a P-type non-single crystal semiconductor layer (31) with silane and a mixture of silane and diborane (14). The fJi layer was formed by mixing methane and phosphin. This NP
N type Jtij (20) with N l-transistor 2.3
eV, P-type layer (31) is 1.5eν, N-type layer (31)
2. OeV in the energy band lJ. Its frequency characteristics exhibit a high frequency characteristic of 12 MIIz at 1.5V between the emitter and base and 10V between the heath and collector.

この添加物は、その応用の目的により決定すればよい。This additive may be determined depending on the purpose of the application.

しかしそれらは本発明をさらに工業的に普及せしめるた
めの手段にすぎない。
However, these are merely means for further industrially disseminating the present invention.

本発明においては、半導体材料として珪素、ゲルマニュ
ーム、炭化珪素を用いた。しかしその他いわゆるGaA
s、GaAIP、GaP等の化合物半導体をあててもよ
いことはいうまでもない。加えて太陽電池等フォト・セ
ンシティブ・ディバイスにおける反射防止膜はλ/4で
あって、n (nは半導体の屈折率)によるが、それは
水素またはハロゲン元素が添加され、さらに添加物のC
,Nまたは0の量をさらに十分多くして、低級窒化珪素
、低級酸化珪素(SiOまたは5iOx)の絶縁体とし
て用いてもよ(15) いことはいうまでもない。
In the present invention, silicon, germanium, and silicon carbide are used as semiconductor materials. However, other so-called GaA
It goes without saying that a compound semiconductor such as S, GaAIP, or GaP may be used. In addition, the antireflection coating in photosensitive devices such as solar cells has a thickness of λ/4, which depends on n (n is the refractive index of the semiconductor), and is doped with hydrogen or a halogen element, as well as the additive C.
, N or 0 may be sufficiently increased and used as an insulator for lower silicon nitride or lower silicon oxide (SiO or 5iOx) (15).

以上の説明より明らかなごとく、本発明は実施例におい
て珪素を中心として半導体を示した。しかし、本発明は
単に珪素に限定されることなく、ゲルマニューム、炭化
珪素等であってもその応用半導体装置に従ってI!gの
適当な制御を成就することにあり、さらにこれを実用化
するためNsを中和する水素、または塩素の如きハロゲ
ン化物が0.1〜200原子%の濃度に添加された非単
結晶半導体に基礎材料として用いたこと、これに酸素、
窒素、炭素等の添加物を化学量論的に10+5〜102
2cm−ヨの範囲例えば炭素を0.1〜80%、窒素を
0.01〜10%、さらに酸素を101S〜10210
2Oヨと階段的または連続的に変化調節して添加したこ
と、このため異なるEgを有する半導体が隣接しても、
その界面には格子不整等によるNsの発生を抑止できた
。さらにP型、N型、■型の導電型およびその伝導度を
不純物の種類およびその量を調整して添加することによ
り成就したこと、加えてこれら半導体装置を多量生産可
能であり、かつ連続生産の可能なグロー(16) 放電または減圧化学蒸着(CVD ”)を用いて作製し
たことにある。その結果、1つの半導体の厚さを0.0
1μ〜lOμの範囲で自由に制御可能であり、Pまたは
N型の不純物も1014〜〜1022cm−9の濃度の
範囲で制御可能であり、PN接合、PI接合、Nl接合
またはPNP、 PIN等の多層接合が容易に作製でき
ることがわかった。加えて多量生産が同一反応炉で連続
的に実施できる等、工業的に全く新しい分野への道が開
けたという大きな特徴を有する。
As is clear from the above description, in the embodiments of the present invention, semiconductors are mainly made of silicon. However, the present invention is not limited to silicon, and can also be applied to germanium, silicon carbide, etc. according to the applied semiconductor device. The objective is to achieve appropriate control of g, and in order to put this into practical use, a non-single crystal semiconductor to which hydrogen to neutralize Ns or a halide such as chlorine is added at a concentration of 0.1 to 200 atomic %. It was used as a basic material in
Additives such as nitrogen and carbon are stoichiometrically 10+5 to 102
For example, 0.1 to 80% carbon, 0.01 to 10% nitrogen, and 101S to 10210% oxygen.
2O was added stepwise or continuously, so even if semiconductors with different Eg are adjacent to each other,
The generation of Ns due to lattice misalignment etc. could be suppressed at the interface. Furthermore, the conductivity types of P-type, N-type, The possible glow (16) lies in the fabrication using discharge or reduced pressure chemical vapor deposition (CVD).As a result, the thickness of one semiconductor can be reduced to 0.0
The concentration of P or N type impurities can be freely controlled within the range of 1μ to lOμ, and the concentration of P or N type impurities can be controlled within the range of 1014 to 1022cm-9. It was found that multilayer junctions can be easily fabricated. In addition, large-scale production can be carried out continuously in the same reactor, which is a major feature that opens the way to completely new industrial fields.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のへテロ接合のエネルギーバンド図を示す
。 第2図および第3図は本発明の実施例を示す。 (17) 駕1口
FIG. 1 shows an energy band diagram of a conventional heterojunction. 2 and 3 show an embodiment of the invention. (17) 1 palanquin

Claims (1)

【特許請求の範囲】 1、水素またはハロゲン元素が添加された第1、第2お
よび第3の非単結晶半導体がr’IN、 I’NP。 NPN、NINまたはPIF接合を構成して設けられ前
記半導体の少なくとも1つの半導体は該半導体に隣接し
た他の半導体材料にエネルギバンドを変更し得る添加物
を添加して設けられたことを特徴とする半導体装置。 2、水素またはハロゲン元素が0.2〜200原子%添
加された第1、第2および第3の非単結晶半導体が積層
して設けられ、前記第1、第2または第3の非単結晶半
導体は珪素、ゲルマニュームまたは炭化珪素よりなり、
該半導体に隣接した他の第1、第2または第3の半導体
は前記半導体材料に炭素、窒素または酸素が添加された
広いエネルギバンド中を有し、互いに隣接した半導体は
連続して2つの接合(1) が設けられたことを特徴とする半導体装置。 3、特許請求の範囲第1項または第2項において、半導
体の厚さが0.01μ〜10μmの範囲で設けられたこ
とを特徴とする半導体装置。
[Claims] 1. The first, second and third non-single crystal semiconductors to which hydrogen or halogen elements are added are r'IN and I'NP. At least one of the semiconductors provided to constitute an NPN, NIN or PIF junction is characterized in that an additive capable of changing an energy band is added to another semiconductor material adjacent to the semiconductor. Semiconductor equipment. 2. First, second and third non-single crystal semiconductors doped with 0.2 to 200 atomic % of hydrogen or halogen elements are provided in a stacked manner, and the first, second or third non-single crystal semiconductor The semiconductor is made of silicon, germanium or silicon carbide,
Another first, second or third semiconductor adjacent to the semiconductor has a wide energy band in which the semiconductor material is doped with carbon, nitrogen or oxygen, and the semiconductors adjacent to each other continuously form two junctions. (1) A semiconductor device characterized by being provided with the following. 3. A semiconductor device according to claim 1 or 2, characterized in that the semiconductor has a thickness in the range of 0.01 μm to 10 μm.
JP59051687A 1984-03-16 1984-03-16 Semiconductor device Pending JPS6041269A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59051687A JPS6041269A (en) 1984-03-16 1984-03-16 Semiconductor device
JP4209437A JPH05304308A (en) 1984-03-16 1992-07-15 Semiconductor device having continuously varying junction and fabrication thereof
JP4345097A JP2626653B2 (en) 1984-03-16 1992-12-02 Silicon semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP59051687A JPS6041269A (en) 1984-03-16 1984-03-16 Semiconductor device
JP4209437A JPH05304308A (en) 1984-03-16 1992-07-15 Semiconductor device having continuously varying junction and fabrication thereof
JP4345097A JP2626653B2 (en) 1984-03-16 1992-12-02 Silicon semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP8346778A Division JPS5511329A (en) 1978-07-08 1978-07-08 Semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP4209437A Division JPH05304308A (en) 1984-03-16 1992-07-15 Semiconductor device having continuously varying junction and fabrication thereof
JP4345097A Division JP2626653B2 (en) 1984-03-16 1992-12-02 Silicon semiconductor device

Publications (1)

Publication Number Publication Date
JPS6041269A true JPS6041269A (en) 1985-03-04

Family

ID=27294399

Family Applications (2)

Application Number Title Priority Date Filing Date
JP59051687A Pending JPS6041269A (en) 1984-03-16 1984-03-16 Semiconductor device
JP4209437A Pending JPH05304308A (en) 1984-03-16 1992-07-15 Semiconductor device having continuously varying junction and fabrication thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP4209437A Pending JPH05304308A (en) 1984-03-16 1992-07-15 Semiconductor device having continuously varying junction and fabrication thereof

Country Status (1)

Country Link
JP (2) JPS6041269A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61244072A (en) * 1985-04-22 1986-10-30 Ricoh Co Ltd Amorphous silicon photoelectric conversion element
JPS61244075A (en) * 1985-04-23 1986-10-30 Ricoh Co Ltd Amorphous silicon photoelectric conversion element
JPH05251722A (en) * 1984-03-16 1993-09-28 Semiconductor Energy Lab Co Ltd Photoelectric converter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51890A (en) * 1974-06-20 1976-01-07 Shunpei Yamazaki Handotaisochi oyobi sonosakuseihoho
JPS51132793A (en) * 1975-02-27 1976-11-18 Varian Associates Solar battery using opposite electroconductive laminate
JPS5342693A (en) * 1976-09-29 1978-04-18 Rca Corp Semiconductor device including amorphous silicone layer
JPS5511329A (en) * 1978-07-08 1980-01-26 Shunpei Yamazaki Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0532901A (en) * 1991-07-31 1993-02-09 Idemitsu Petrochem Co Ltd Thermoplastic resin composition

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51890A (en) * 1974-06-20 1976-01-07 Shunpei Yamazaki Handotaisochi oyobi sonosakuseihoho
JPS51132793A (en) * 1975-02-27 1976-11-18 Varian Associates Solar battery using opposite electroconductive laminate
JPS5342693A (en) * 1976-09-29 1978-04-18 Rca Corp Semiconductor device including amorphous silicone layer
JPS5511329A (en) * 1978-07-08 1980-01-26 Shunpei Yamazaki Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05251722A (en) * 1984-03-16 1993-09-28 Semiconductor Energy Lab Co Ltd Photoelectric converter
JPS61244072A (en) * 1985-04-22 1986-10-30 Ricoh Co Ltd Amorphous silicon photoelectric conversion element
JPS61244075A (en) * 1985-04-23 1986-10-30 Ricoh Co Ltd Amorphous silicon photoelectric conversion element

Also Published As

Publication number Publication date
JPH05304308A (en) 1993-11-16

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