JPS63202044A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63202044A JPS63202044A JP3487387A JP3487387A JPS63202044A JP S63202044 A JPS63202044 A JP S63202044A JP 3487387 A JP3487387 A JP 3487387A JP 3487387 A JP3487387 A JP 3487387A JP S63202044 A JPS63202044 A JP S63202044A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- point metal
- silicide
- manufacturing
- metal silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000008034 disappearance Effects 0.000 abstract 2
- -1 polysilicon Chemical compound 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置の！ｌｌｌｌ決方法し、特に配線
構造の一部に高融点金属シリサイドを使用する半導体装
置の製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to semiconductor devices! In particular, the present invention relates to a method of manufacturing a semiconductor device that uses refractory metal silicide in a part of the wiring structure.
［従来の技術］
第２図はＭＯＳ Ｆ Ｅ Ｔのゲート部を示した断面模
式図である。[Prior Art] FIG. 2 is a schematic cross-sectional view showing a gate portion of a MOS FET.
以下、簡単にこの製造方法について説明する。This manufacturing method will be briefly explained below.
まず、たとえばシリコン基板１上にＬＯＣＯ８法等によ
って分離酸化渠２を形成した後、分１酸化膜２上に第１
電極３を写真製版でパターニングして形成する。次に、
熱酸化法等で全面にシリコン酸化膜４を形成し、さらに
その上にＣＶＤ法等でポリシリコン５を形成する。ポリ
シリコン５上にスパッタ法によってたとえばモリブデン
シリサイド６を形成し、いわゆるポリシリサイド構造の
配線層とする。First, for example, after forming an isolation oxide conduit 2 on a silicon substrate 1 by the LOCO8 method, a first
The electrode 3 is formed by patterning using photolithography. next,
A silicon oxide film 4 is formed on the entire surface by thermal oxidation or the like, and polysilicon 5 is further formed thereon by CVD or the like. For example, molybdenum silicide 6 is formed on polysilicon 5 by sputtering to form a wiring layer having a so-called polysilicide structure.
Ｒ＠に、このポリシリサイド膜に所望のパターニングを
施した後、層間絶縁ｌ１１７をＣＶＤ法によって形成し
て所望の配線構造が製造される。After performing desired patterning on this polysilicide film at R@, an interlayer insulating layer 117 is formed by the CVD method to manufacture a desired wiring structure.
［発明が解決しようとする問題点］
上記のような従来の製造方法では、１１１間絶縁膜がＣ
ＶＤ法での高温く８００〜９５０℃〉状況の中で形成さ
れるので、この高温雰囲気がモリブデンシリサイド膜に
影響を及ぼして結晶変態を発生させ、その結果モリブデ
ンシリサイド膜に強い収縮応力が生じる。この応力が特
にモリブデンシリサイド膜の段差部に集中するため、そ
の段差部でモリブデンシリサイドの欠落部８を生じ異常
な配線抵抗の上昇や断線等を生じる問題点があった。[Problems to be solved by the invention] In the conventional manufacturing method as described above, the insulating film between 111 and 111 is C
Since it is formed in a high temperature environment of 800 to 950° C. in the VD method, this high temperature atmosphere affects the molybdenum silicide film to cause crystal transformation, and as a result, strong shrinkage stress is generated in the molybdenum silicide film. Since this stress is particularly concentrated at the step portion of the molybdenum silicide film, there is a problem in that a missing portion 8 of molybdenum silicide is formed at the step portion, resulting in an abnormal increase in wiring resistance, disconnection, etc.
この発明はかかる問題点を解決するためになされたもの
で、高融点金属シリサイドをその一部に使用する配線構
造であっても、段差部における高融点金属シリサイドの
欠落のない半導体装置の製造方法を提供することを目的
とする。This invention has been made to solve such problems, and is a method for manufacturing a semiconductor device without missing high-melting-point metal silicide at the stepped portion even in a wiring structure in which high-melting-point metal silicide is used in a part of the wiring structure. The purpose is to provide
［問題点を解決するための手段］
この発明に係る半導体装置の製造方法は、ポリシリコン
等の上に高融点金属シリサイドを形成した後、これらを
パターニングする前に熱処理を行なう工程を追加したも
のである。[Means for Solving the Problems] The method for manufacturing a semiconductor device according to the present invention includes an additional step of forming high melting point metal silicide on polysilicon etc. and then performing heat treatment before patterning the silicide. It is.
［作用］
この発明においてはパターニング前の熱処理が高融点金
属シリサイドの形成時における段差部での応力集中を緩
和するので、後工程の層間絶縁膜の形成時の熱影響を受
けてもその段差部における欠落を防止する。[Function] In this invention, the heat treatment before patterning alleviates the stress concentration at the stepped portion during the formation of the high melting point metal silicide, so even if the stepped portion is affected by heat during the formation of the interlayer insulating film in the subsequent process, the stepped portion Prevent omissions in
［実施例］
第１図はこの発明の一実施例における主要工程の断面模
式図である。[Example] FIG. 1 is a schematic cross-sectional view of main steps in an example of the present invention.
図において、たとえばシリコン基板１上にＬＯＣＯ８法
等によって分ｗｉ酸化膜２を形成した後、分離酸化膜２
上に第１電極３を写真製版でパターニングして形成する
。次に熱酸化法等で全面にシリコン酸化膜４を形成し、
さらにその上にＣＶＤ法でポリシリコン５を形成する〈
第１図（ａ ）参照）。In the figure, for example, after forming a separation oxide film 2 on a silicon substrate 1 by the LOCO8 method, an isolation oxide film 2 is formed.
A first electrode 3 is formed thereon by patterning using photolithography. Next, a silicon oxide film 4 is formed on the entire surface by thermal oxidation method etc.
Furthermore, polysilicon 5 is formed on it by CVD method.
(See Figure 1(a)).
このときのポリシリコン５の段差は約５００ＯＡである
が、この上にスパッタ法によってたとえばモリブデンシ
リサイド６を形成した後、これに８００℃以上での熱処
理を実施し、モリブデンシリサイド形成時の段差部での
応力集中を緩和させる〈第１図（ｂ）参照）。The step difference in the polysilicon 5 at this time is about 500 OA, but after forming molybdenum silicide 6 on top of it by sputtering, heat treatment is performed on it at 800°C or higher, so that the step part when forming the molybdenum silicide is (see Figure 1(b)).
最漫に、写真製版技術等でパターニングを行ないポリシ
リコン５とモリブデンシリサイド６よりなる２層構造の
所望の配線を形成した後、層間絶縁ＦＩ７をＣＶＤ法で
形成して完成する（第１図（ｃ）参照）。Finally, patterning is performed using photolithography or the like to form a desired two-layer interconnection structure consisting of polysilicon 5 and molybdenum silicide 6, and then an interlayer insulation FI 7 is formed using the CVD method (see Fig. 1). c).
なお、上記実施例では、配線構造の一部をモリブデンシ
リサイドとしているがタングステンシリサイドやタンタ
ルシリサイドであっても同種の効果を奏する。In the above embodiment, a part of the wiring structure is made of molybdenum silicide, but the same effect can be obtained even if tungsten silicide or tantalum silicide is used.
［発明の効果］
この発明は以上説明したとおり、高融点金属シリサイド
を形成した後パターニング前に熱処理して段差部での応
力集中を緩和するので、後工程においての欠落を防止し
信頼のおける配線構造を有した半導体装置の製造方法と
なる効果がある。[Effects of the Invention] As explained above, in this invention, after forming a high melting point metal silicide, heat treatment is performed before patterning to alleviate stress concentration at the stepped portion, thereby preventing chipping in subsequent processes and providing reliable wiring. This has the effect of providing a method for manufacturing a semiconductor device having a structure.
第１図はこの発明の一実施例における概略工程断面図、
第２図は一般のＭＯＳＦＥＴのゲート部を示した断面模
式図である。
図において、１はシリコン基板、４はシリコン酸化膜、
５はポリシリコン、６はモリブデンシリサイド、７は層
間絶縁膜である。
なお、各図中同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄
第１回
５ ボｌノシνコ／FIG. 1 is a schematic cross-sectional view of the process in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view showing the gate portion of a general MOSFET. In the figure, 1 is a silicon substrate, 4 is a silicon oxide film,
5 is polysilicon, 6 is molybdenum silicide, and 7 is an interlayer insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa 1st 5 Voluntary Nuko/
Claims (7)
を有する半導体装置の製造方法であって、 基板上に絶縁膜を介して配線の一部となる層を形成する
工程と、 前記層上に前記高融点金属シリサイドを形成する工程と
、 形成された前記高融点金属シリサイドを応力除去するた
めの熱処理を行なう工程と、 前記熱処理の後、前記高融点金属シリサイドおよび前記
層をパターニングして所望の配線構造を形成する工程と
、 前記所望の配線構造上に層間絶縁膜を形成する工程とを
備えた、半導体装置の製造方法。(1) A method for manufacturing a semiconductor device having a wiring structure containing at least high-melting point metal silicide, comprising: forming a layer that will become part of the wiring on the substrate via an insulating film; a step of forming a melting point metal silicide; a step of performing heat treatment to relieve stress on the formed high melting point metal silicide; and after the heat treatment, patterning the high melting point metal silicide and the layer to form a desired wiring structure. A method for manufacturing a semiconductor device, comprising: forming an interlayer insulating film on the desired wiring structure.
第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the layer is polysilicon.
特許請求の範囲第１項記載の半導体装置の製造方法。(3) the heat treatment is carried out at a temperature of 800°C or higher;
A method for manufacturing a semiconductor device according to claim 1.
イドである、特許請求の範囲第１項、第２項または第３
項記載の半導体装置の製造方法。(4) Claim 1, 2 or 3, wherein the high melting point metal silicide is molybdenum silicide.
A method for manufacturing a semiconductor device according to section 1.
サイドである、特許請求の範囲第１項、第２項または第
３項記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the high melting point metal silicide is tungsten silicide.
ドである、特許請求の範囲第１項、第２項または第３項
記載の半導体装置の製造方法。(6) The method for manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the high melting point metal silicide is tantalum silicide.
特許請求の範囲第１項ないし第６項のいずれかに記載の
半導体装置の製造方法。(7) the interlayer insulating film is formed by a CVD method;
A method for manufacturing a semiconductor device according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3487387A JPS63202044A (en) | 1987-02-17 | 1987-02-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3487387A JPS63202044A (en) | 1987-02-17 | 1987-02-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202044A true JPS63202044A (en) | 1988-08-22 |
Family
ID=12426268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3487387A Pending JPS63202044A (en) | 1987-02-17 | 1987-02-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202044A (en) |
-
1987
- 1987-02-17 JP JP3487387A patent/JPS63202044A/en active Pending
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