JPS63200571A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To manufacture a thin film transistor having a high mobility, a low threshold voltage, and a large ON/OFF ratio by reducing the thickness of a polycrystalline Si film for forming a gate electrode and conducting hydrogenating step. CONSTITUTION:A polycrystalline silicon film 2 is deposited, for example, on a Pyrex substrate 1 as a substrate made of insulating substance at least on the surface, and patterned to form an active layer. Then, a silicon oxide film 3 to become a gate insulating film is deposited, a polycrystalline silicon film 4 is further deposited, and patterned as a gate electrode. After phosphorus ions are implanted, a silicon oxide film 6 to become an interlayer insulating film is deposited, and annealed to activate the ions in a nitrogen atmosphere. Then, the contact holes 7, 8 of source, drain are opened, AlSi is deposited, source, drain electrodes 9, 10 are patterned, annealed in a hydrogen atmosphere, and hydrogenated by a hydrogen plasma. Thus, the polycrystalline silicon film for forming the gate electrode can be reduced in thickness, thereby improving the characteristics of a transistor.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to thin film transistors using polycrystalline silicon, which are applied to large-area active matrix liquid crystal displays and tertiary element devices, etc. The present invention relates to a method of manufacturing a thin film transistor in which performance is improved by making the gate thinner.

<Conventional technology> In recent years, MI using a polycrystalline silicon thin film as an active region has been developed.
S-type FET is SOI (5illicon on Ins
Active research is being carried out on applications such as application to ulator) devices and thin film transistors (TPT) for liquid crystal display elements. These device characteristics are greatly influenced by the polycrystalline silicon thin film used as the active layer. The film quality of a polycrystalline silicon thin film is mainly determined by the grain size of the crystal grains constituting the thin film and the dangling bonds present at the grain boundaries, and generally the fewer the dangling bonds, the better. As a means of improving film quality, high-temperature annealing is performed to expand the grain size of the crystal grains and reduce the density of dangling bonds in the grain boundaries, but this alone does not eliminate the dangling bonds in the grain boundaries. However, if the dangling bonds are further amalgamated with hydrogen plasma (hydrogenation), the localized levels formed in the band gap are reduced.

<Problems to be Solved by the Invention> However, the effect of hydrogenation using hydrogen plasma cannot be said to be sufficient.

The reason for this is that since a thick gate electrode exists directly above the channel region to be hydrogenated, the efficiency of hydrogenation is significantly reduced due to localized levels in the polycrystalline silicon that is the gate electrode. Therefore, in order to obtain sufficient hydrogenation efficiency, it was necessary to make the gate electrode thin.

However, the film thickness of the gate electrode must be (■) thick enough to reduce the resistance of the polycrystalline silicon for the gate;
) When implanting impurities to form the source and drain portions, the film must satisfy conditions such as having a film thickness that can prevent impurity implantation into the channel region.

In addition, in conventional processes, the projected range of impurities is increased so that the impurity concentration reaches its maximum at the gate surface and reduces the contact resistance between the gate electrode and the wiring metal.
It was necessary to remove the outermost surface of the gate polycrystalline silicon by etching to a depth corresponding to ion range). This increases the number of etching steps that require precision, and it is necessary to thicken the polycrystalline silicon in consideration of process errors in order to ensure reproducibility, making it difficult to reduce the thickness of the polycrystalline silicon film.

The present invention was devised in view of the above points, and provides an ultra-thin gate structure that can facilitate hydrogenation in a MIS field effect transistor using polycrystalline silicon as an active layer and a gate electrode. The present invention aims to provide a method for manufacturing a thin transistor that achieves low threshold voltage and high mobility.

Means and operation for solving the above problems In order to achieve the above object, in the present invention, an MIS field effect transistor is formed on a silicon active layer formed on the entire surface of a substrate whose surface is made of an insulating material. In the manufacturing method of the thin film transistor to be formed, a polycrystalline silicon film forming a gate electrode is deposited, a silicon oxide film is deposited on this polycrystalline silicon film, and then a silicon oxide film is deposited in a region contacting the gate electrode and immediately above the silicon oxide film. The structure is such that the excess silicon oxide film and polycrystalline silicon film are removed leaving only the film, and in this state impurity ions are implanted into the source, drain, and gate regions. In the preferred embodiment of the present invention, the thickness of the silicon oxide film is set so that the impurity implantation concentration is close to the maximum on the gate polycrystalline silicon surface, and the impurity is concentrated in the active layer under the thinned gate. 1 x 10
The configuration is such that it is selected so as not to inject more than 13 cWV2.

That is, in the present invention, in a thin film transistor in which an MIS type field effect transistor is formed in an active layer formed on the entire surface of a substrate whose surface is at least an insulating material,
Deposit polycrystalline silicon for the gate on the gate insulating film, then deposit a silicon oxide film, remove it by etching leaving only the silicon oxide film located directly above the gate electrode, and then pattern the polycrystalline silicon that will become the gate electrode. Then, by implanting impurities into the source, drain, and gate, it is possible to make the polycrystalline silicon gate electrode extremely thin, facilitating hydrogenation, and improving transistor characteristics.

The film thickness of the silicon oxide film on the polycrystalline silicon is such that the gate polycrystalline silicon is doped so that the impurity concentration is maximum near the outermost surface by an impurity implantation process for forming source and drain regions. By using the process according to the present invention, the polycrystalline silicon gate, which is a factor inhibiting hydrogenation, can be made extremely thin without reducing the blocking ability against impurity implantation for the following reasons.

(I) Since the silicon oxide film on the polycrystalline silicon has a thickness corresponding to the projected range of impurities in the polycrystalline silicon, the polycrystalline silicon can be made thinner by the thickness of the projected range.

m) The presence of the oxide film reduces ion channeling in polycrystalline silicon so that the stopping power does not decrease even if the film is made thinner.

(Conversion) Since the above-mentioned ethoching process is unnecessary, the film thickness margin for ensuring reproducibility is small.

Due to the functions and effects described above, the extremely thin gate polycrystalline silicon has greatly improved efficiency in the hydrogenation process, resulting in high mobility and low threshold voltage (and TPT with a large on-off ratio). realizable.

<Example> Sufficient hydrogenation efficiency has not been obtained in conventional processes, especially low-temperature processes.

Therefore, as an example of the present invention, manufacturing of a polycrystalline thin film transistor by a low temperature process will be described in detail.

FIGS. 1(a) to 1(f) are diagrams each showing a cross section of an element in each manufacturing process as an embodiment of the present invention.

In carrying out the present invention, a Pyrex glass substrate 1 is used as a substrate having at least a surface made of an insulating material.
As shown in FIG. 1(a), xo
A polycrystalline silicon thin film 2 of OOI was deposited, and the active layer portion was patterned. Next, as shown in FIG. 1(b), a silicon oxide film 3 which will become a gate insulating film is deposited at 500× at 420° C. by normal pressure CVD method, and then deposited at 500× in an oxygen atmosphere.
Annealing was performed at 0° C. for 2 hours to densify the silicon oxide film 3.

Next, as shown in FIG. 1(c), a polycrystalline silicon film 4 is deposited at 500X using the vacuum evaporation method described above, and then a silicon oxide film 5 is deposited at 500X using the normal pressure CVD method and patterned to form a gate. An electrode was formed. Next, Figure 1 (d
), phosphorus ion (3I P+ ) was
1.5XI915/12 injections were performed at eV. After that, a silicon oxide film 6, which will become an interlayer insulating film, is deposited at a 50°C using the normal pressure CVD method.
ooX was deposited and annealed for 70 hours at 550'C in a nitrogen atmosphere for phosphorus ion (31P+) activation. Next, as shown in FIG. 1(e), contact holes 7 and 8 are opened for the source and drain parts, and 5,000 layers of AfSi are deposited by sputtering. 9 and the drain electrode 10 were patterned. Finally, annealing was performed at 440° C. for 30 minutes in a hydrogen atmosphere, and then hydrogenation was performed using hydrogen plasma. Hydrogenation was performed at a substrate temperature of 300°C and a hydrogen/nitrogen ratio of 1:1. pressure 1'
rorr, Rfpower 280mW/-1, processing time 5 hours. Figure 2 shows the gate voltage vs. drain current characteristics of the thin film transistor fabricated as described above. In the figure, A indicates the gate voltage. B is a gate electrode with a thickness of 1500X and hydrogenated, B is a gate electrode with a thickness of 1500X and hydrogenated, and C is a gate electrode prepared in the above example with a thickness of 500X. It is hydrogenated using The channel length and channel width of this thin film transistor are both 10/1 m, and the drain bias voltage with respect to the source is +IV.
It is.

As is clear from FIG. 2, by making the gate electrode thinner, hydrogenation becomes easier, the threshold voltage decreases, and the on-current increases.

In the above example, the film thickness of the gate electrode was set at 500, but it is necessary to optimize the film thickness of the gate electrode and the silicon oxide film thereon depending on the film quality of the gate electrode and the required transistor characteristics. be.

In addition, polycrystalline silicon is not limited to the vacuum evaporation method, but can also be formed using other film formation methods, or by implanting silicon ions (28Si+) into a microcrystalline silicon film formed at a low temperature, an amorphous silicon film, or a polycrystalline silicon film to form a partially amorphous silicon film. A solid-phase grown silicon film may also be used. Regarding the temperature of the annealing, it is desirable to perform the annealing at as high a temperature as possible without adversely affecting the substrate and the device.

Effects of the Invention> As described above, according to the present invention, when forming a thin film transistor on a substrate whose surface is an insulating material, it is possible to reduce the thickness of the polycrystalline silicon film forming the gate electrode, and the hydrogenation process is It is possible to increase the efficiency of the transistor and improve the characteristics of the transistor. This makes it possible to manufacture TPT with good characteristics, and is expected to be applied to thin film transistors for potassium SJI devices and liquid crystal display elements.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are diagrams showing device cross sections in each process of manufacturing a polycrystalline silicon thin film transistor as an embodiment of the present invention, and FIG. 2 is a diagram showing a cross section of a device manufactured as an embodiment of the present invention 1. Topyrex glass (insulating substrate), 2. Polycrystalline silicon thin film (active layer), 3. Silicon oxide film. (gate insulating film), 4... polycrystalline silicon film (
gate electrode), 5... silicon oxide film (impurity implantation depth control oxide film), 6... silicon oxide film (interlayer insulating film), 7... contact hole (source part), 8... contact hole (
Drain part), 9...AI! Si (source electrode),
10...AlSi (drain electrode).

Claims (1)

[Claims] 1. A method for manufacturing a thin film transistor in which an MIS field effect transistor is formed in a silicon active layer formed on one main surface of a substrate whose surface is made of an insulating material, comprising the steps of: Deposit a silicon film, deposit a silicon oxide film on the polycrystalline silicon film, and then remove the excess silicon oxide film and polycrystalline silicon film, leaving only the region that will become the gate electrode and the silicon oxide film directly above it. A method for manufacturing a thin film transistor, characterized in that impurity ions are implanted into the source, drain, and gate regions in such a state. 2. The thickness of the silicon oxide film is adjusted so that the impurity implantation concentration is close to the maximum on the gate polycrystalline silicon surface, and the impurity concentration is 1×10^1^3 in the active layer under the thinned gate.
2. The method of manufacturing a thin film transistor according to claim 1, wherein the implantation is selected so as not to exceed cm^-^2.