JPS63200521A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To lessen a loss because of a damage to a nearby wafer by causing dimensions at the center part of the water of a semiconductor chip to be larger than those at its peripheral part. CONSTITUTION:Situating among chips that are partitioned by partitioning lines, chips 2a on a wafer 2 are in the form of regular square and each of them has a small area, while the chips 2b are rectangular, each of which has an area that is twice that of the chips 2a. A wafer area is efficiently used by placing the chips 2b at the center part and the chips 2a at peripheral parts. The larger an area ratio of a chip 2b to 2a is, the more effectively a wafer are is utilized. Further, when the peripheral parts of the wafer are damaged, only small chips 2a suffer damage and then the quality of the wafer is not harmed very much.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor wafers having semiconductor chips therein having a plurality of sizes.

[Conventional technology]

FIG. 3 is a plan view showing an example of a conventional semiconductor wafer having nine semiconductor chips having different sizes therein. In FIG. 3, a semiconductor wafer 2
1 is divided into a large number of square semiconductor chips 2a and rectangular chips 2b in which two chips 28t are arranged by a large number of dividing lines drawn vertically and horizontally. These chips are arranged in alternating columns evenly over the wafer surface.

[Problem that the invention seeks to solve]

The conventional semiconductor wafer described above that has semiconductor chips of a plurality of sizes therein has a drawback that as the size of the semiconductor chips increases, the area of unused portions on the same side of the wafer increases. Furthermore, when a semiconductor chip at the periphery of a wafer is damaged with wafer tweezers or the like, there is a drawback that as the size of the semiconductor chip increases, the area of the wafer that is damaged by one scratch becomes relatively large.

[Means for solving problems]

In order to solve the above-mentioned problems, the semiconductor wafer 1 of the present invention includes a large number of semiconductor chips of multiple types of sizes divided by dividing lines drawn vertically and horizontally, and a large-sized semiconductor chip is placed in the center of the wafer. , a semiconductor chip smaller in size than the semiconductor chip is arranged around the periphery of the semiconductor chip.

〔Example〕

The present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention. In FIG. 1, 1 is a semiconductor wafer, and 2a is a square chip with a small area among a large number of chips partitioned by a large number of dividing lines drawn vertically and horizontally.

The chip 2b is rectangular and its area is the same as the conductor chip 2a.
It is twice the area of . A semiconductor chip 2b is placed in the center of the wafer l, and a semiconductor chip 2a is placed in the periphery of the wafer 1.
By doing this, we aim to make effective use of the area of Ueno. Comparing with the conventional example shown in FIG. 3, in the third case there are 64 semiconductor chips 2a and 32 semiconductor chips 2b on a wafer of the same size, and in the case of FIG.
6 pieces, 2b contains 44 pieces. Comparing the effective usable area of these two, it can be seen that when converted to a small chip 2a,
The figure has 144 pieces, and the figure 3 has 128 pieces, so the difference is 1
Six more chips 2a can be taken from the wafer of the invention. This effect becomes more pronounced as the area ratio between the semiconductor chips 2a and 2b increases. Furthermore, if a single scratch is made on the wafer periphery with wafer tweezers or the like, in the case of Fig. 1, the small semiconductor chip 2a
However, in the case of FIG. 3, twice as much area as in the case of FIG. 1 is damaged, so the damage is reduced by the present invention.

FIG. 2 is a plan view of another embodiment of the invention.

In FIG. 2, 2e is a large square semiconductor chip that occupies the center of the wafer 11. In FIG. Step 2c,
2d is a small semiconductor chip for measuring the characteristics of the semiconductor wafer 11, and is located at the periphery of the wafer 21. In the case of the conventional technology, only the semiconductor chip 2e can be placed on the semiconductor wafer, but in the uninvention, a small semiconductor chip device for measuring the characteristics of the semiconductor wafer is placed in an unused part on the semiconductor quaenor 11, and the entire surface of the wafer is placed. We are trying to make effective use of the building.

〔Effect of the invention〕

As explained above, in a semiconductor wafer having semiconductor chips having a plurality of sizes, the semiconductor wafer has a semiconductor chip of a small size placed in the center of the entire semiconductor wafer with a semiconductor chip of a large size. Placing the wafer near the periphery of the wafer can reduce the unused portion of the wafer and reduce damage caused by scratching the wafer periphery with a wafer, wafer tweezers, etc.

[Brief explanation of the drawing]

1 and 2 are plan views showing one embodiment and another embodiment of a semiconductor wafer having therein semiconductor chips having a plurality of dimensions according to the present invention, and FIG. 1 is a plan view of a semiconductor wafer having semiconductor chips therein having a plurality of dimensions; FIG. 1, 11, 21--...Semiconductor waeno...2
b, 2e...Large semiconductor chip, 2a, 2c
, 2d・・・・・・・・・Small semiconductor chip.

Claims (1)

[Claims] A semiconductor wafer having semiconductor chips of different shapes and sizes in the semiconductor wafer, characterized in that the dimensions of the semiconductor chips located at the center of the wafer are larger than those of the semiconductor chips located at the periphery of the wafer. semiconductor wafer.