JPS63200521A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS63200521A JPS63200521A JP3395287A JP3395287A JPS63200521A JP S63200521 A JPS63200521 A JP S63200521A JP 3395287 A JP3395287 A JP 3395287A JP 3395287 A JP3395287 A JP 3395287A JP S63200521 A JPS63200521 A JP S63200521A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chips
- semiconductor
- area
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 238000000638 solvent extraction Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 35
- 230000000694 effects Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は複数種類の寸法をもった半導体チップをその中
に有する半導体ウェーハに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor wafers having semiconductor chips therein having a plurality of sizes.
第3図は、従来技術における複数種類の寸法を持つ九半
導体チップをその中に有する半導体つ・エーハの一例を
示す平面図である。第3図において、半導体ウェーハ2
1は、縦横に引かれた多数の分割線によシ正方形の半導
体チップ2aと、チップ28t−2個並べた長方形のチ
ップ2bとの多数に区画されている。そして、これらチ
ップはウェーハ面一様に、交互の縦列に配置されている
。FIG. 3 is a plan view showing an example of a conventional semiconductor wafer having nine semiconductor chips having different sizes therein. In FIG. 3, a semiconductor wafer 2
1 is divided into a large number of square semiconductor chips 2a and rectangular chips 2b in which two chips 28t are arranged by a large number of dividing lines drawn vertically and horizontally. These chips are arranged in alternating columns evenly over the wafer surface.
上述した従来技術における複数種類の寸法をもった半導
体チップをその中に有する半導体ウェーハにおいて、半
導体チップ寸法の増大に伴い、ウェーハ同辺部に未使用
部分の面積が大きくなる欠点がある。また、ウェーハピ
ンセットなどでウェーハ周辺部の半導体チップを傷付け
た場合、半導体チップ寸法の増大に伴い相対的に一つの
傷により損害を受けるウェーハの面積が大きくなる欠点
がある。The conventional semiconductor wafer described above that has semiconductor chips of a plurality of sizes therein has a drawback that as the size of the semiconductor chips increases, the area of unused portions on the same side of the wafer increases. Furthermore, when a semiconductor chip at the periphery of a wafer is damaged with wafer tweezers or the like, there is a drawback that as the size of the semiconductor chip increases, the area of the wafer that is damaged by one scratch becomes relatively large.
上記問題点に対し本発明の半導体ウエーノ1は、縦横に
引かれた分割線に↓シ区画された複数種類寸法の多数の
半導体テ・ツブを含み、ウエノ・の中心部に寸法の大き
い半導体テップ、ウエノ・の周辺部に前記半導体チップ
よ、り寸法の小さい半導体チップを配置している。In order to solve the above-mentioned problems, the semiconductor wafer 1 of the present invention includes a large number of semiconductor chips of multiple types of sizes divided by dividing lines drawn vertically and horizontally, and a large-sized semiconductor chip is placed in the center of the wafer. , a semiconductor chip smaller in size than the semiconductor chip is arranged around the periphery of the semiconductor chip.
以下図面を参照しで、本発明を説明する。 The present invention will be described below with reference to the drawings.
第1図は本発明の一実施例の平面図である。第1図にお
いて、1は半導体ウェーハ、2aは、縦横に引かれた多
数の分割線によ多区画された多数のチップのうち、正方
形の小面積のチップである。FIG. 1 is a plan view of one embodiment of the present invention. In FIG. 1, 1 is a semiconductor wafer, and 2a is a square chip with a small area among a large number of chips partitioned by a large number of dividing lines drawn vertically and horizontally.
チップ2bは長方形で、その面積が牛導体チ・ツブ2a
の面積の2倍のものである。ウェーハlの中心部に半導
体チップ2b、ウェーハ1の周辺部に半導体チップ2a
’kit<ことにより、ウエーノ1面積の有効利用をは
かっている。第3図の従来例と比較すると、同じ大きさ
のウェーハに、第3の場合、半導体チップ2aは64個
、2bは32個、第1図の場合、半導体チップ2aは5
6個、2bは44個含まれている。この2者の有効利用
面積を比較すると、小形のチップ2aに換算して、第1
図は144個、第3図は128個であるから、その差1
6個だけ多くのチップ2aが、本発明のウェーハから採
取できることになる。この効果は、半導体チップ2aと
2bの面積比が大きい程、顕著になる。また、友とえは
ウェーハピンセットなどでウェーハ周辺部に1箇所傷付
けた場合、第1図の場合だと、小形の半導体チップ2a
の面積が損害を受けるが、第3図の場合、第1図の場合
の2倍の面積が損害を受けるので、本発明により損害が
小さくなる。The chip 2b is rectangular and its area is the same as the conductor chip 2a.
It is twice the area of . A semiconductor chip 2b is placed in the center of the wafer l, and a semiconductor chip 2a is placed in the periphery of the wafer 1.
By doing this, we aim to make effective use of the area of Ueno. Comparing with the conventional example shown in FIG. 3, in the third case there are 64 semiconductor chips 2a and 32 semiconductor chips 2b on a wafer of the same size, and in the case of FIG.
6 pieces, 2b contains 44 pieces. Comparing the effective usable area of these two, it can be seen that when converted to a small chip 2a,
The figure has 144 pieces, and the figure 3 has 128 pieces, so the difference is 1
Six more chips 2a can be taken from the wafer of the invention. This effect becomes more pronounced as the area ratio between the semiconductor chips 2a and 2b increases. Furthermore, if a single scratch is made on the wafer periphery with wafer tweezers or the like, in the case of Fig. 1, the small semiconductor chip 2a
However, in the case of FIG. 3, twice as much area as in the case of FIG. 1 is damaged, so the damage is reduced by the present invention.
第2図は本発明の他の実施例の平面図である。FIG. 2 is a plan view of another embodiment of the invention.
第2図において、2eは正方形の大きな半導体チップで
、ウェーハ11の中央部を占めている。テップ2c 、
2dは半導体ウェーハ11の特性を測定するための小形
の半導体チップであって、ウェーハ21の周辺部に位置
している。従来技術の場合、半導体チップ2eのみしか
半導体ウェーハ上に置けないが、不発明では、半導体ク
エーノー11上の未使用部分に、半導体ウェーハの特性
を測定するための小形の半導体チップ装置いて、ウェー
ハ全面棟の有効利用をはかっている。In FIG. 2, 2e is a large square semiconductor chip that occupies the center of the wafer 11. In FIG. Step 2c,
2d is a small semiconductor chip for measuring the characteristics of the semiconductor wafer 11, and is located at the periphery of the wafer 21. In the case of the conventional technology, only the semiconductor chip 2e can be placed on the semiconductor wafer, but in the uninvention, a small semiconductor chip device for measuring the characteristics of the semiconductor wafer is placed in an unused part on the semiconductor quaenor 11, and the entire surface of the wafer is placed. We are trying to make effective use of the building.
以上説明しtように、本発明は、複数種類の寸法を持っ
た半導体チップをその中に有する半導体ウェーハにおい
て、寸法が大きい半導体チップ全半導体ウェーハの中心
部に、小さい寸法の半導体チップを半導体ウェーハの周
辺部に置くことにょシ、ウェーハの未使用部分を減らす
ことができ、マタ、ウェーハピンセットなどでウェーハ
周辺部を傷付けた場合の損害を、小さくできる効果があ
る。As explained above, in a semiconductor wafer having semiconductor chips having a plurality of sizes, the semiconductor wafer has a semiconductor chip of a small size placed in the center of the entire semiconductor wafer with a semiconductor chip of a large size. Placing the wafer near the periphery of the wafer can reduce the unused portion of the wafer and reduce damage caused by scratching the wafer periphery with a wafer, wafer tweezers, etc.
第1図および第2図は、本発明による複数種類の寸法を
持った半導体チップをその中に持つ半導体ウェーハの一
実施例および他の実施例を示す平面図、第3図は、従来
技術での複数種類の寸法を持っt半導体チップをその中
に持つ半導体ウェーハの平面図である。
1 、11 、21−・・・−・半導体ウエーノ・、2
b、2e・・・・・・大形の半導体チップ、2a、2c
、2d・・・・・・・・・・・・小形の半導体チップ。1 and 2 are plan views showing one embodiment and another embodiment of a semiconductor wafer having therein semiconductor chips having a plurality of dimensions according to the present invention, and FIG. 1 is a plan view of a semiconductor wafer having semiconductor chips therein having a plurality of dimensions; FIG. 1, 11, 21--...Semiconductor waeno...2
b, 2e...Large semiconductor chip, 2a, 2c
, 2d・・・・・・・・・Small semiconductor chip.
Claims (1)
する半導体ウェーハにおいて、このウェーハの中心部に
位置する半導体チップの寸法が、ウェーハ周辺部に位置
する半導体チップの寸法より大なることを特徴とする半
導体ウェーハ。A semiconductor wafer having semiconductor chips of different shapes and sizes in the semiconductor wafer, characterized in that the dimensions of the semiconductor chips located at the center of the wafer are larger than those of the semiconductor chips located at the periphery of the wafer. semiconductor wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3395287A JPS63200521A (en) | 1987-02-16 | 1987-02-16 | Semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3395287A JPS63200521A (en) | 1987-02-16 | 1987-02-16 | Semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63200521A true JPS63200521A (en) | 1988-08-18 |
Family
ID=12400833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3395287A Pending JPS63200521A (en) | 1987-02-16 | 1987-02-16 | Semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63200521A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0709740A1 (en) * | 1994-09-30 | 1996-05-01 | Texas Instruments Incorporated | Integrated circuit and method of making the same |
-
1987
- 1987-02-16 JP JP3395287A patent/JPS63200521A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0709740A1 (en) * | 1994-09-30 | 1996-05-01 | Texas Instruments Incorporated | Integrated circuit and method of making the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI462218B (en) | Pedestal pocket tray containment system for integrated circuit chips | |
US8343804B2 (en) | Implementing multiple different types of dies for memory stacking | |
JP2001176959A5 (en) | ||
JPS63200521A (en) | Semiconductor wafer | |
US5873772A (en) | Method for polishing the top and bottom of a semiconductor wafer simultaneously | |
US20190006197A1 (en) | Wafer part and chip packaging method | |
JPS59220947A (en) | Manufacture of semiconductor device | |
JPS551170A (en) | Semiconductor apparatus | |
JPS5599719A (en) | Heat treatment jig of wafer | |
JPS5935448A (en) | Master-slice integrated circuit device | |
JP2766857B2 (en) | Semiconductor integrated circuit device forming wafer | |
JPH08186064A (en) | Semiconductor wafer and method for dicing semiconductor pellet | |
JPS59117215A (en) | Semiconductor wafer | |
JPS6076135A (en) | Semiconductor wafer | |
JPH04368175A (en) | Master slice lsi | |
JPH0360053A (en) | Semiconductor integrated circuit device | |
JPH0562974A (en) | Semiconductor device | |
JPH03214658A (en) | Multiple-structure buffer cell | |
JPS59167036A (en) | Semiconductor integrated circuit | |
JPH0513569A (en) | Semiconductor device | |
JPH0461320A (en) | Basket type board | |
JPS63244639A (en) | Semiconductor substrate | |
JPH04124873A (en) | Integrated circuit chip | |
JPH02246205A (en) | Semiconductor device | |
JPS59173334U (en) | Semiconductor wafer transfer equipment |