JPS63244639A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS63244639A
JPS63244639A JP7805187A JP7805187A JPS63244639A JP S63244639 A JPS63244639 A JP S63244639A JP 7805187 A JP7805187 A JP 7805187A JP 7805187 A JP7805187 A JP 7805187A JP S63244639 A JPS63244639 A JP S63244639A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
semiconductor substrate
semiconductor devices
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7805187A
Other languages
Japanese (ja)
Inventor
Toshio Ishii
石井 利生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7805187A priority Critical patent/JPS63244639A/en
Publication of JPS63244639A publication Critical patent/JPS63244639A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain an element and a circuit for evaluation use of a large-area semiconductor substrate without reducing the number of semiconductor devices obtainable using one semiconductor substrate by a method wherein auxiliary semiconductor devices are formed at the four corners of a main semiconductor device. CONSTITUTION:Octagonal main semiconductor devices 1 as first semiconductor devices and diamond-shaped auxiliary semiconductor devices 3 as second semiconductor devices are arranged on a semiconductor substrate lengthwise and breadthwise at individually prescribed intervals, and are partitioned by individual scribing lines 2. Electrode pads 4 are situated at the inside of each main semiconductor device 1 and a actual circuit part 5 is formed at their inner part. On the other hand, pads 6 for evaluation use are arranged on each auxiliary semiconductor device 3; an element and a circuit for evaluation use of the semiconductor substrate are mounted. In this case, an area of the actual circuit part 5 is decided by a width of a region for a bonding connection to the electrode pads 4; accordingly, if a size of the auxiliary semiconductor device 3 is limited to almost the same as this width, the area of the actual circuit part 5 is not reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板に関し、特に複数種類の半導体装1
を形成してなる半導体基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor substrate, and particularly to a plurality of types of semiconductor devices 1.
The present invention relates to a semiconductor substrate formed by forming.

〔従来の技術〕[Conventional technology]

従来、この種の半導体基板においては、矩形の半導体装
置を縦横に各々一定の間隔で配置したものが使用されて
いる。
Conventionally, in this type of semiconductor substrate, one in which rectangular semiconductor devices are arranged at regular intervals in both the vertical and horizontal directions has been used.

第5図は従来の半導体基板の一部の平面図である。FIG. 5 is a plan view of a portion of a conventional semiconductor substrate.

第5図に示すように、半導体基板上に矩形の半導体装置
11が各々一定間隔で配置され、各々は分割予定線(ス
ライプ線)12によって区切られている。
As shown in FIG. 5, rectangular semiconductor devices 11 are arranged on a semiconductor substrate at regular intervals, and each is separated by a dividing line (slide line) 12.

第6図は第5図に示す半導体装置の−繰り返しパターン
の拡大図である。
FIG. 6 is an enlarged view of the repeating pattern of the semiconductor device shown in FIG.

第6図に示すように、半導体装置11はスクライブ線1
2によって切断され、周辺に形成された電極パッド部1
4とこれらパッド部14に囲まれた実回路部15とに分
けられる。このような半導体基板においては、半導体基
板上に形成された素子や回路11の特性を評価するため
の部分を同じ半導体装置11内に配置する方法、および
半導体装置11と同一の外形をもつ別の半導体装置内に
設は縦横の配列の一部を置換して設置する方法等が行な
われている。
As shown in FIG. 6, the semiconductor device 11 has a scribe line 1
2 and formed around the electrode pad part 1
4 and an actual circuit section 15 surrounded by these pad sections 14. In such a semiconductor substrate, there are methods for arranging parts for evaluating the characteristics of the elements and circuits 11 formed on the semiconductor substrate in the same semiconductor device 11, and methods for arranging parts for evaluating the characteristics of the elements and circuits 11 formed on the semiconductor substrate, and methods for arranging parts for evaluating the characteristics of the elements and circuits 11 formed on the semiconductor substrate, and methods for arranging parts for evaluating the characteristics of the elements and circuits 11 formed on the semiconductor substrate. A method is used in which a part of the vertical and horizontal arrangement is replaced in the semiconductor device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体基板においては、半導体装置が矩
形構造になっているため、前者の設置方法にあっては一
つの半導体装置の大きさが大きくなるかあるいは搭載で
きる評価項目が少なくなる欠点があり、また後者の設置
方法にあっては一枚の半導体基板上に形成できる半導体
装置の数が減少するという欠点がある。
In the conventional semiconductor substrate described above, the semiconductor device has a rectangular structure, so the former installation method has the disadvantage that the size of one semiconductor device becomes large or the number of evaluation items that can be mounted is reduced. Furthermore, the latter installation method has the disadvantage that the number of semiconductor devices that can be formed on one semiconductor substrate is reduced.

本発明の目的は、かかる半導体装置の大きさを大きくす
ることなく且つ評価項目を減少させることなく、また一
つの基板から形成できる半導体装置の数も減少させるこ
とのない半導体基板を提供することにある。
An object of the present invention is to provide a semiconductor substrate without increasing the size of the semiconductor device, without reducing evaluation items, and without reducing the number of semiconductor devices that can be formed from one substrate. be.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体基板は、縦横に各々一定間隔で配置され
た第一の半導体装置と、前記第一の半導体装置を分断す
るためのスクライブ線と、前記スクライブ線の交差する
個所で前記第一の半導体装置にまたがるように形成され
た第二の半導体装置とを含んで構成される。
The semiconductor substrate of the present invention includes first semiconductor devices arranged at regular intervals in the vertical and horizontal directions, a scribe line for dividing the first semiconductor devices, and a first semiconductor device at a point where the scribe lines intersect. and a second semiconductor device formed so as to straddle the semiconductor device.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第一の実施例を説明するための半導体
基板の一部の平面図である。
FIG. 1 is a plan view of a portion of a semiconductor substrate for explaining a first embodiment of the present invention.

第1図に示すように、半導体基板上には第一の半導体装
置である六角形の本半導体装置1と第二の半導体装置で
ある菱形の副半導体装置3が縦横に各々一定の間隔で配
置され、各々スクライブ線2で区切られている。
As shown in FIG. 1, on a semiconductor substrate, a hexagonal main semiconductor device 1, which is a first semiconductor device, and a rhombic sub-semiconductor device 3, which is a second semiconductor device, are arranged at regular intervals vertically and horizontally. and are separated by scribe lines 2.

第2図は第1図に示す本半導体装置と副半導体装置の−
繰り返しパターンの拡大図である。
Figure 2 shows the main semiconductor device and sub-semiconductor device shown in Figure 1.
It is an enlarged view of a repeating pattern.

第2図に示すように、本半導体装置1の内部には周辺部
に電極パッド4があり、その内側に実回路部5がある。
As shown in FIG. 2, inside the present semiconductor device 1, there are electrode pads 4 at the periphery, and an actual circuit section 5 inside thereof.

一方、副半導体装置3には評価用パッド6が配置されて
おり、半導体基板の評価用素子や回路が搭載されている
On the other hand, an evaluation pad 6 is arranged on the sub-semiconductor device 3, and evaluation elements and circuits of the semiconductor substrate are mounted thereon.

ところで、実回路部5の面積は電極パッド4へのボンデ
ィング接続のための領域の幅で決まるため、副半導体装
置3の大きさはこの幅と同程度までに制限しておけばよ
い、すなわち、これを設置したことによる実回路部5の
面積の減少はない。
Incidentally, since the area of the actual circuit portion 5 is determined by the width of the region for bonding connection to the electrode pad 4, the size of the sub-semiconductor device 3 may be limited to the same extent as this width. There is no reduction in the area of the actual circuit section 5 due to this installation.

また、本実施例においては本半導体装置1の角は鈍角に
なっているため、スクライブ後の角の欠けもしくははが
れの問題は少なくなる。
Further, in this embodiment, since the corners of the semiconductor device 1 are obtuse angles, the problem of chipping or peeling of the corners after scribing is reduced.

第3図は本発明の第二の実施例を説明するための半導体
基板の一部の平面図である。
FIG. 3 is a plan view of a portion of a semiconductor substrate for explaining a second embodiment of the present invention.

第3図に示すように、半導体基板上には本半導体装置1
と矩形の副半導体装置7が配置されている。
As shown in FIG. 3, the present semiconductor device 1 is placed on the semiconductor substrate.
A rectangular sub-semiconductor device 7 is arranged.

第4図は第3図における半導体装置の−繰り返しパター
ンの拡大図である。
FIG. 4 is an enlarged view of the repeated pattern of the semiconductor device in FIG. 3.

第4図に示すように、この実施例は第一の実施例に比べ
て多くの電極バッド4がある例であり、このような場合
は副半導体装置7の形を矩形にした方が本半導体装置1
の面積を大きくとれるという利点がある。
As shown in FIG. 4, this embodiment is an example in which there are many electrode pads 4 compared to the first embodiment, and in such a case, it is better to make the sub-semiconductor device 7 rectangular in shape. Device 1
It has the advantage of being able to take up a large area.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は本半導体装置の四隅に副
半導体装置を設けることにより、−半導体基板上でとれ
る半導体装置の数を減らすことなしに大きな面積の半導
体基板の評価用の素子や回路の部分を得られる効果があ
る。更に、副半導体装置を単体で組立て詳細な評価を行
い易いという効果もある。
As explained above, the present invention provides sub-semiconductor devices at the four corners of the present semiconductor device, thereby enabling the evaluation of elements and circuits on large-area semiconductor substrates without reducing the number of semiconductor devices that can be formed on the semiconductor substrate. It has the effect of obtaining the following parts. Furthermore, there is an effect that it is easy to assemble the sub-semiconductor device as a single unit and perform detailed evaluation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一の実施例を説明するための半導体
基板の一部の平面図、第2図は第1図に示す半導体装置
の−繰り返しパターンの拡大図、第3図は本発明の第二
の実施例を説明するための半・導体基板の一部の平面図
、第4図は第3図に示す半導体装置の−繰り返しパター
ンの拡大図、第5図は従来の半導体基板の一部の平面図
、第6図は第5図に示す半導体装置の−繰り返しパター
ンの拡大図である。 1・・・本半導体装置、2・・・スクライブ線、3.7
・・・副半導体装置、4・・・電極パッド、5・・・実
回路部、6・・・評価用パッド。 汀 代理人 弁理士 内 原  晋f 、’−:、。 磐1 面 第3 図 牛4 図
FIG. 1 is a plan view of a part of a semiconductor substrate for explaining a first embodiment of the present invention, FIG. 2 is an enlarged view of a repeating pattern of the semiconductor device shown in FIG. 1, and FIG. A plan view of a part of a semiconductor/conductor substrate for explaining a second embodiment of the invention, FIG. 4 is an enlarged view of a repeating pattern of the semiconductor device shown in FIG. 3, and FIG. 5 is a conventional semiconductor substrate. FIG. 6 is an enlarged view of the repeating pattern of the semiconductor device shown in FIG. 1... Semiconductor device, 2... Scribe line, 3.7
...Sub-semiconductor device, 4...Electrode pad, 5...Actual circuit section, 6...Evaluation pad. Susumu Uchihara, Patent Attorney, '-:,. Iwa 1, 3rd figure, cow 4 figure

Claims (1)

【特許請求の範囲】[Claims] 縦横に各々一定間隔で配置された第一の半導体装置と、
前記第一の半導体装置を分断するためのスクライブ線と
、前記スクライブ線の交差する個所で前記第一の半導体
装置にまたがるように形成された第二の半導体装置とを
含んでいることを特徴とする半導体基板。
first semiconductor devices arranged at regular intervals in the vertical and horizontal directions;
The method includes a scribe line for dividing the first semiconductor device, and a second semiconductor device formed to straddle the first semiconductor device at a location where the scribe lines intersect. semiconductor substrate.
JP7805187A 1987-03-30 1987-03-30 Semiconductor substrate Pending JPS63244639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7805187A JPS63244639A (en) 1987-03-30 1987-03-30 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7805187A JPS63244639A (en) 1987-03-30 1987-03-30 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS63244639A true JPS63244639A (en) 1988-10-12

Family

ID=13651049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7805187A Pending JPS63244639A (en) 1987-03-30 1987-03-30 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS63244639A (en)

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