JPS62114257A - Wire bonding pad layout - Google Patents

Wire bonding pad layout

Info

Publication number
JPS62114257A
JPS62114257A JP60257095A JP25709585A JPS62114257A JP S62114257 A JPS62114257 A JP S62114257A JP 60257095 A JP60257095 A JP 60257095A JP 25709585 A JP25709585 A JP 25709585A JP S62114257 A JPS62114257 A JP S62114257A
Authority
JP
Japan
Prior art keywords
pads
pad
bonding pad
layout
interval
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60257095A
Other languages
Japanese (ja)
Inventor
Takahiro Morimoto
森本　隆博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60257095A priority Critical patent/JPS62114257A/en
Publication of JPS62114257A publication Critical patent/JPS62114257A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To highly integrated a semiconductor chip by laying out adjacent bonding pads in a zigzag disposition displaced inward and outward, and disposing a peripheral buffer corresponding to the pad displaced inward at the outside. CONSTITUTION:Adjacent pads are replaced at every other one at the inner and outer relationship of peripheral buffer 3 corresponding to the pads at outside and inside pads 2a, 2b. Accordingly, the interval of the adjacent pads 2a, 2b is separated in the amount displaced in the zigzag manner, thereby considerably approaching the pads 2a, 2a... and 2b, 2b... belonging to the same rows at zigzag disposition at the distance corresponding to the separated distance. That is, the interval between the adjacent pads 2a, 2b can be set to relatively narrow interval A-DELTAA as compared with the disposing interval A of the conventional example.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路装置におけるワイヤボンディ
ングパッドのレイアウトに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the layout of wire bonding pads in a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

従来例によるこの種の半導体集積回路装置のワイヤボン
ディングパッドレイアウトとしては、一般的に第２図に
示す通り、半導体チップ１の表面外側周辺にあって、通
常、複数の各ボンディングパッド２を一直線上に等間隔
で配置させた構成になっており、この配置構成に伴なっ
て、各ボンディングパッド２に対応する各周辺バッファ
３についても、個々のボンディングパッド２の内側に配
置させている。As shown in FIG. 2, the conventional wire bonding pad layout of this type of semiconductor integrated circuit device is generally located around the outside of the surface of the semiconductor chip 1, and usually connects a plurality of bonding pads 2 in a straight line. According to this arrangement, each peripheral buffer 3 corresponding to each bonding pad 2 is also arranged inside each bonding pad 2.

そしてこの従来例構成の場合、前記各ボンディングパッ
ド２の配置間隔Ａとしては、第３図に示すように、この
ボンディングパッド２にワイヤボンダーヲ用いてワイヤ
リングする際にあって、先にワイヤリングし終えた隣接
するパッド上のポールポンド４に対し、そのときのワイ
ヤボンダーのキャピラリチップ５の部分が、これに接触
するのを避は得るだけの許容範囲外にあるように〃１約
されることになる。In the case of this conventional structure, the arrangement interval A between the bonding pads 2 is such that, as shown in FIG. 3, when the bonding pads 2 are wired using a wire bonder, The capillary tip 5 of the wire bonder at that time is adjusted so that the portion of the capillary tip 5 of the wire bonder is outside the permissible range enough to avoid contact with the pole pound 4 on the adjacent pad. Become.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例構成での各ボンディングパッド２の配置間隔は、
このようにワイヤリングのためのワイヤボンダーの操作
により制約を受け、許容間隔範囲内にレイアウトされて
いるので、より以上にパッド間隔を狭めることができず
、これが半導体チップの高密度集積化を妨げるものであ
った。The arrangement interval of each bonding pad 2 in the conventional configuration is as follows:
In this way, the layout is limited by the operation of the wire bonder for wiring and the pad spacing is within the allowable spacing range, so the pad spacing cannot be further narrowed, and this hinders high-density integration of semiconductor chips. Met.

従ってこの発明の目的とするところは、各ボンディング
パッドの配置間隔を狭めることにより、パッド数の増加
、ひいては半導体チップの高密度集積化を図り得るよう
にした。この種のワイヤボンディングパッドレイアウト
を提供することである。Therefore, it is an object of the present invention to increase the number of pads and to achieve higher density integration of semiconductor chips by narrowing the spacing between bonding pads. The purpose is to provide this kind of wire bonding pad layout.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するために、この発明においては、各ボ
ンディングパッドを従来の直線状配置から、隣接するパ
ッド同志が相互に内外にずれ合った千鳥状配置にレイア
ウトさせると共に、内側にずれ込んだパッドの外側に、
同内側パッドに対応する周辺バッファを配置させて、隣
接パッド相互の配置間隔を相対的に狭め得るようにし、
また必要に応じて、内側にずれ込んだパッドに対応する
周辺バッファについては、これを外側から同パッドの下
方内部を通して配線するようにしたものである。In order to achieve the above object, in this invention, each bonding pad is laid out in a staggered arrangement, in which adjacent pads are shifted inwardly and outwardly from each other, instead of the conventional linear arrangement, and pads that are shifted inwardly are arranged in a staggered arrangement. on the outside,
A peripheral buffer corresponding to the same inner pad is arranged so that the spacing between adjacent pads can be relatively narrowed,
Further, if necessary, peripheral buffers corresponding to pads shifted inward are wired from the outside through the inside and below the pads.

〔作　　　用〕[For production]

すなわち、この発明では、各ボンディングパッドの隣接
する相互を、内外にずれ合った千鳥状配置にレイアウト
させたので、隣接パッド相互の配置間隔を千鳥状のずれ
込み相当分だけ狭めることができ、また内側にずれ込ん
だパッドに対応する周辺バッファを外側に配置させて、
これを外側から同パッドの下方内部を通して配線させ得
る。That is, in this invention, since the adjacent bonding pads are laid out in a staggered arrangement in which they are shifted inwardly and outwardly, the spacing between adjacent bonding pads can be narrowed by the amount equivalent to the staggered shift, and By placing the peripheral buffer outside that corresponds to the pad that has shifted,
This can be routed from the outside through the inside and under the same pad.

〔実　施　例〕〔Example〕

以下この発明に係るワイヤボンディングパッドレイアウ
トの一実施例につき、第１図を参照して詳細に説明する
。Hereinafter, one embodiment of the wire bonding pad layout according to the present invention will be described in detail with reference to FIG.

第１図はこの実施例を適用した半導体チップにおけるワ
イヤボンディングパッドのレイアウト配置を示す要部平
面図であり、この第１図実施例において前記第２図従来
例と同一符号は同一または相当部分を表わしている。FIG. 1 is a plan view of main parts showing the layout of wire bonding pads in a semiconductor chip to which this embodiment is applied. In this embodiment, the same reference numerals as in the conventional example in FIG. It represents.

この実施例においては、前記した各ボンディングパッド
２のレイアウト配置に関して、隣接するパッド同志が相
互に内外にずれ合った千鳥状配置にレイアウトさせる。In this embodiment, the layout of each of the bonding pads 2 described above is arranged in a staggered manner in which adjacent pads are shifted inwardly and outwardly relative to each other.

すなわち換言すると、相互に隣接する各パッドを、外側
パッド２ａと内側パッド２ｂとに、交互にずらせたレイ
アウト配置、こ＼では、具体的に各パッド２と対応する
周辺バッファ３との内外関係位置を、一つ置きに入れ替
えさせるのである。In other words, a layout arrangement in which mutually adjacent pads are alternately shifted to outer pads 2a and inner pads 2b, specifically, the inner and outer relative positions of each pad 2 and the corresponding peripheral buffer 3. , and have them replaced every other time.

従ってこの実施例によるレイアウト配置では、隣接する
パッド２ａ　、　２ｂ相互の間隔が、千鳥状のずれ込み
分だけ離されることになり、これによって千鳥状配置で
の各々同列に属するパッド２ａ、２ａ、・・・・・・お
よび２ｂ、２ｂ、・・・・・・を、この離された距離相
当分対応に接近させ得るもので、結果的には、この場合
の隣接するパラＫ　２ａ　、　２ｂ相互の間隔を、前記
従来例での配置間隔Ａよりも相対的に狭めた配置間隔Ａ
−ΔＡに設定できるのである。Therefore, in the layout arrangement according to this embodiment, the spacing between adjacent pads 2a, 2b is separated by the amount of staggered displacement, so that the pads 2a, 2a, . . . , which belong to the same row in the staggered arrangement, . . . and 2b, 2b, . is an arrangement interval A that is relatively narrower than the arrangement interval A in the conventional example.
-ΔA can be set.

そしてこの実施例ではまた、これらの各外側パッド２ａ
、および内側パッド２ｂの個々に対応する各周辺バッフ
ァ３についても、外側に位置する外側パッド２ａでは、
従来と同様にその内側に配置した内側周辺バッファ３ｂ
とし、また内側にずれ込んだ内側パッド２Ｍ’は、その
外側に配置した外側周辺バッファ３ａにすると共に、こ
の外側周辺バッファ３ａの接続は、その内側パッド２ｂ
の下方内部を通して、チップの内部ロジック回路などに
配線させれば良く、こへでもこの構成によって、千鳥状
配置に伴って生ずる空間スペースを、より有効に活用で
きるのである。And in this embodiment, each of these outer pads 2a
, and for each peripheral buffer 3 corresponding to each of the inner pads 2b, for the outer pad 2a located on the outer side,
Inner peripheral buffer 3b placed inside as before
In addition, the inner pad 2M' that has shifted inward is replaced with the outer peripheral buffer 3a arranged outside, and the connection of this outer peripheral buffer 3a is with the inner pad 2b.
The wires can be wired to the internal logic circuit of the chip through the lower interior of the chip, and with this configuration, the space created by the staggered arrangement can be used more effectively.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、各ボンディング
パッドを相互に内外にずれ合った千鳥状にレイアウト配
置させたから、ワイヤボンダーの操作に制約される許容
間隔範囲を実質的に増加し得て、隣接パッド相互の配置
間隔を相対的に狭めることができ、また内側にずれ込ん
だパッドに対応する周辺バッファを外側に配置させ、こ
れを外側から同パッドの下方内部を通して配線させたの
で、この周辺バッフγのために、特に新たな領域を設定
させる必要がなく、これらによって半導体チップの高密
度集積化を向上できるもので、しかも単なるレイアウト
配置の改善であるため、構造的にも比較的簡単で、容易
かつ安価に実施できるなどの特長を有する。As described in detail above, according to the present invention, since the bonding pads are arranged in a staggered layout with mutual inward and outward shifts, the allowable interval range that is restricted by the operation of the wire bonder can be substantially increased. , the spacing between adjacent pads can be relatively narrowed, and the peripheral buffer corresponding to the pad that has shifted inward is placed outside, and this is routed from the outside through the inside of the same pad. There is no need to specifically set up a new area for the buffer γ, and this can improve the high-density integration of semiconductor chips.Furthermore, since it is simply an improvement in layout arrangement, it is relatively simple in terms of structure. It has the advantage of being easy and inexpensive to implement.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を適用した半導体チップに
おけるワイヤボンディングパッドのレイアウト配置を示
す要部平面図であり、また第２図は同上従来例によるワ
イヤボンディングパッドのレイアウト配置を示す要部平
面図、第３図は同上ワイヤリング時の断面説明図である
。 １・・・・半導体チップ、２・・・・ボンディングパッ
ド、　２ａ・・・・外側パッド、２ｂ・・・・内側パッ
ド、３・・・・周辺バッファ、３ａ・・・・外側周辺バ
ッファ、　３ｂ・・・・内側周辺バッファ、４・・・・
ポールポンド、５・・・・キャピラリチップ。 第１図FIG. 1 is a plan view of main parts showing the layout arrangement of wire bonding pads in a semiconductor chip to which an embodiment of the present invention is applied, and FIG. 2 is a main part showing the layout arrangement of wire bonding pads according to the conventional example of the same. The plan view and FIG. 3 are cross-sectional explanatory views when wiring the same as above. 1... Semiconductor chip, 2... Bonding pad, 2a... Outer pad, 2b... Inner pad, 3... Peripheral buffer, 3a... Outer peripheral buffer, 3b ...Inner peripheral buffer, 4...
Paul Pond, 5...Capillary tip. Figure 1

Claims (2)

【特許請求の範囲】[Claims] （１）半導体チップの表面周辺に配置される各ボンディ
ングパッドに対するワイヤリングを考慮したレイアウト
であつて、前記各ボンディングパッドを、隣接するパッ
ド同志が相互に内外にずれ合つた千鳥状にレイアウト配
置させると共に、この千鳥状配置に伴ない、内側にずれ
込んだパッドの外側に、同内側パッドに対応する周辺バ
ッファを配置させたことを特徴とするワイヤボンディン
グパッドレイアウト。(1) A layout that takes into consideration wiring for each bonding pad arranged around the surface of a semiconductor chip, in which each bonding pad is arranged in a staggered manner with adjacent pads being shifted inwardly and outwardly relative to each other; , a wire bonding pad layout characterized in that a peripheral buffer corresponding to the inner pad is arranged on the outer side of the pad that is shifted inward due to this staggered arrangement. （２）外側に配置される周辺バッファを、対応する内側
パッドの下方内部を通して配線したことを特徴とする特
許請求の範囲第１項記載のワイヤボンディングパッドレ
イアウト。(2) The wire bonding pad layout according to claim 1, wherein the peripheral buffer arranged on the outside is wired through the inside and under the corresponding inside pad.
JP60257095A 1985-11-13 1985-11-13 Wire bonding pad layout Pending JPS62114257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60257095A JPS62114257A (en) 1985-11-13 1985-11-13 Wire bonding pad layout

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60257095A JPS62114257A (en) 1985-11-13 1985-11-13 Wire bonding pad layout

Publications (1)

Publication Number Publication Date
JPS62114257A true JPS62114257A (en) 1987-05-26

Family

ID=17301667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60257095A Pending JPS62114257A (en) 1985-11-13 1985-11-13 Wire bonding pad layout

Country Status (1)

Country Link
JP (1) JPS62114257A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63209134A (en) * 1987-02-25 1988-08-30 Nec Corp Semiconductor integrated circuit
GB2422485A (en) * 2004-12-22 2006-07-26 Agilent Technologies Inc IC die with rows of staggered I/O pads with each row having a different pad shape
CN102074510A (en) * 2010-11-11 2011-05-25 友达光电股份有限公司 Contact-mat array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63209134A (en) * 1987-02-25 1988-08-30 Nec Corp Semiconductor integrated circuit
GB2422485A (en) * 2004-12-22 2006-07-26 Agilent Technologies Inc IC die with rows of staggered I/O pads with each row having a different pad shape
CN102074510A (en) * 2010-11-11 2011-05-25 友达光电股份有限公司 Contact-mat array

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