JPS5831733B2 - integrated circuit device - Google Patents
integrated circuit deviceInfo
- Publication number
- JPS5831733B2 JPS5831733B2 JP57039541A JP3954182A JPS5831733B2 JP S5831733 B2 JPS5831733 B2 JP S5831733B2 JP 57039541 A JP57039541 A JP 57039541A JP 3954182 A JP3954182 A JP 3954182A JP S5831733 B2 JPS5831733 B2 JP S5831733B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- distance
- leads
- becomes smaller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 本発明は、集積回路（ＩＣ）装置に関する。[Detailed description of the invention] The present invention relates to integrated circuit (IC) devices.
従来、ＩＣ内蔵半導体チップ（ＩＣチップ）をレジン封
止する場合などには、一枚の金属板を所望のパターンで
打抜いて形成したリードフレームがしばしば使用されて
いる。Conventionally, when sealing a semiconductor chip with a built-in IC (IC chip) with resin, a lead frame formed by punching a single metal plate in a desired pattern has often been used.
これまで提案されているこの種のＩＣ用リードフレーム
においては、レジン封止体内に埋設されるインナーリー
ドの先端かボンディングワイヤを介してＩＣチップの所
定のポンディングパッドに接続されるようになっており
、各インナーリードの先端位置はＩＣチップにおけるポ
ンディングパッド配置辺に沿って一直線状に並んでいる
。In this type of IC lead frame that has been proposed so far, the tips of the inner leads embedded in the resin molding are connected to predetermined bonding pads of the IC chip via bonding wires. The tip positions of the inner leads are aligned in a straight line along the side where the bonding pads are arranged on the IC chip.
しかしながら、このような従来のＩＣ用リードフレーム
を用いて作られた集積回路装置は、例えばメモリーｔＩ
ｃ化したＩＣチップによくみられるようにＩＣチップの
２辺に多数のポンディングパッドが集中的に配列されて
いるような場合にはボンディング作業にあたりボンディ
ングワイヤがとなりのリードに接触して歩留りを低下さ
せるという欠点がある。However, integrated circuit devices made using such conventional IC lead frames, for example,
If a large number of bonding pads are arranged in a concentrated manner on two sides of the IC chip, as is often the case with IC chips that have been converted to PC, the bonding wire may come into contact with the adjacent lead during the bonding process, reducing yield. It has the disadvantage of lowering
本発明の目的は、このような欠点をなくした新規な集積
回路装置を提供することにある。It is an object of the present invention to provide a novel integrated circuit device that eliminates these drawbacks.
本発明の要旨は、集積回路を内蔵した半導体チップと、
上記半導体チップの対向する２辺それぞれに沿って形成
された複数のポンディングパッドと、上記半導体チップ
の周囲にその先端か位置するように形成された複数のリ
ードと、上記複数のリードの先端と上記ポンディングパ
ッドとを接続するボンディングワイヤとを有し、上記複
数のリードのうち、上記対向する２辺それぞれに沿って
位置するリードは、そのリードの先端と上記半導体チッ
プとの距離がその中央部のリードからはなれるにつれて
小さくなるように上記半導体チップ周囲に位置している
ことを特徴とする集積回路装置にある。The gist of the present invention is to provide a semiconductor chip with a built-in integrated circuit;
a plurality of bonding pads formed along each of two opposing sides of the semiconductor chip; a plurality of leads formed around the semiconductor chip so that their tips are located; and tips of the plurality of leads; and a bonding wire connecting the bonding pad, and among the plurality of leads, the leads located along each of the two opposing sides are such that the distance between the tip of the lead and the semiconductor chip is at the center. The integrated circuit device is characterized in that the integrated circuit device is located around the semiconductor chip so that it becomes smaller as it gets farther away from the leads of the semiconductor chip.
以下、添付図面を参照して本発明を詳述する。Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
図は、本発明の一実施例による集積回路装置ＩＣｋ示し
、特にＩＣチップとインナーリードとかボンディングワ
イヤで接続されている状態を示す平面図である。The figure is a plan view showing an integrated circuit device ICk according to an embodiment of the present invention, particularly showing a state in which an IC chip is connected to an inner lead or a bonding wire.
同図において、１０はリード１０Ａ、１０Ｂを介してリ
ードフレーム本体に接続されたタブ、２０はタブ１０の
表面に固着されたＩＣチップをそれぞれ示す。In the figure, 10 indicates a tab connected to the lead frame main body via leads 10A and 10B, and 20 indicates an IC chip fixed to the surface of the tab 10.
この例のＩＣチップ２０は対向する２辺にポンディング
パッド２１Ａ、２１Ｂがそれぞれ集中的に配置され、他
の２辺には全くポンディングパッドが配置されていない
ものであり、この種のＩＣチップはメモ’Ｊ’ｅＩＣ化
した場合にしばしばみられるものである。The IC chip 20 in this example has bonding pads 21A and 21B arranged intensively on two opposing sides, and no bonding pads at all on the other two sides. This is often seen when memo 'J'eIC is converted.
ところで、リードフレーム本体はＩＣチップ１０の４辺
に対向配置される４群のインナーリード１１，１２，１
３．１４を有し、これらのリードの先端位置は本発明の
教示にしたがって適宜ずらされている。By the way, the lead frame main body has four groups of inner leads 11, 12, 1 arranged oppositely on the four sides of the IC chip 10.
3.14, and the tip positions of these leads are appropriately offset in accordance with the teachings of the present invention.
すなわち、ＩＣチップ２０のポンディングパッド配置辺
に対向する２群のインナーリード１２，１４においては
リード列中央からはなれるにつれてリード先端とＩＣチ
ップ２０との離間距離が小さくなるようになっており、
また、ＩＣチップ２０の他の２辺に対向する２群のイン
ナーリードＩＬ１３においてはリード列中央からはなれ
るにつれてリード先端とＩＣチップ２０との離間距離が
大きくなるようになっている。That is, in the two groups of inner leads 12 and 14 facing the side where the bonding pads are arranged of the IC chip 20, the distance between the lead tips and the IC chip 20 becomes smaller as they move away from the center of the lead row.
In addition, in the two groups of inner leads IL13 facing the other two sides of the IC chip 20, the distance between the lead tips and the IC chip 20 increases as the distance from the center of the lead row increases.
フ
このようなインナーリード配置によれば、ボンディング
ワイヤ２２Ａ、２２Ｂで各リードの先端をポンディング
パッド２１Ａ、２１Ｂに接続する際に、各ボンディング
ワイヤかとなりのリードに接触することがなくなり、ボ
ンディング歩留りを大幅に向上させることができる。According to such an inner lead arrangement, when connecting the tip of each lead with the bonding wires 22A and 22B to the bonding pads 21A and 21B, each bonding wire does not come into contact with the adjacent lead, which improves the bonding yield. can be significantly improved.
また、ＩＣチップ上にボンディングバンドを配置するに
あたっても、上記のようにリードフレームのインナーリ
ード配置でボンディングワイヤの不要な接触を阻止でき
るようになっていると、設計の自由度が増す効果がある
。Additionally, when placing the bonding band on the IC chip, if the inner lead arrangement of the lead frame can prevent unnecessary contact with the bonding wires as described above, it will have the effect of increasing the degree of freedom in design. .
図は、本発明の一実施例による集積回路装置のインナー
リード配置を示す平面図である。
１０・・・・・・タブ、１１〜１４・・・・・・インナ
ーリード、２０・・・・・ＩＣチップ、２１Ａ、２１Ｂ
・・・・・・ポンディングパッド、２２Ａ、２２Ｂ・・
・・・・ボンディングワイヤ。The figure is a plan view showing an inner lead arrangement of an integrated circuit device according to an embodiment of the present invention. 10...Tab, 11-14...Inner lead, 20...IC chip, 21A, 21B
...Pounding pad, 22A, 22B...
...bonding wire.
Claims (1)
ップの対向する２辺それぞれに沿って形成された複数の
ポンディングパッドと、上記半導体チップの周囲にその
先端か位置するように形成された複数のリードと、上記
複数のリードの先端と上記ポンディングパッドとを接続
するボンディングワイヤとを有し、上記複数のリードの
うち、上記対向する２辺それぞれに沿って位置するリー
ドは、そのリードの先端と上記半導体チップとの距離が
その中央部のリードからはなれるにつれて小さくなるよ
うに上記半導体チップ周囲に位置していることを特徴と
する集積回路装置。1 A semiconductor chip containing an integrated circuit, a plurality of bonding pads formed along each of two opposing sides of the semiconductor chip, and a plurality of bonding pads formed around the semiconductor chip so as to be located at the tip thereof. It has a lead and a bonding wire that connects the tips of the plurality of leads and the bonding pad, and among the plurality of leads, the leads located along each of the two opposing sides are connected to the tip of the lead. and the semiconductor chip are located around the semiconductor chip such that the distance between the leads and the semiconductor chip decreases as the distance between the lead and the semiconductor chip decreases as the distance between the lead and the semiconductor chip decreases as the distance between the lead and the semiconductor chip decreases as the distance between the lead and the semiconductor chip decreases as the distance between the lead and the semiconductor chip becomes smaller as the distance between the lead and the lead becomes smaller as the distance between the lead and the lead becomes smaller as the distance between the lead and the lead becomes smaller as the distance between the lead and the lead becomes smaller as the distance between the lead and the lead in the center of the lead becomes smaller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57039541A JPS5831733B2 (en) | 1982-03-15 | 1982-03-15 | integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57039541A JPS5831733B2 (en) | 1982-03-15 | 1982-03-15 | integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57164557A JPS57164557A (en) | 1982-10-09 |
| JPS5831733B2 true JPS5831733B2 (en) | 1983-07-08 |
Family
ID=12555907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57039541A Expired JPS5831733B2 (en) | 1982-03-15 | 1982-03-15 | integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831733B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604524A (en) * | 1983-06-22 | 1985-01-11 | Ajinomoto Co Inc | Latent curing agent for epoxy resin |
| US5269452A (en) * | 1992-11-12 | 1993-12-14 | Northern Telecom Limited | Method and apparatus for wirebonding |
| JP2636776B2 (en) * | 1995-02-09 | 1997-07-30 | 日本電気株式会社 | Wire bonding method |
-
1982
- 1982-03-15 JP JP57039541A patent/JPS5831733B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57164557A (en) | 1982-10-09 |
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