JPS63194422A - Parallel-serial conversion circuit - Google Patents

Abstract

PURPOSE:To make the provision of a counter unnecessary, by providing an FF which inverts and holds the least significant bit of a parallel data, detecting the completion of a conversion operation by the propagation of the above n-bit values from a first bit to the (n-1)-th bit of a shift register of n-bits, and generating the next parallel load signal. CONSTITUTION:When the parallel data is set at the shift register 1 of n-bits, the inverted data of the least significant bit of the above data is set at the FF4. Afterwards, the data inputted to the register 1 is shifted out in order, and simultaneously, the bit value held by the FF4 is inputted to a final stage. At a time when an n-th bit is shifted to the most significant bit, the data from the (n-1)-th bit to the least significant bit becomes the same data as that of the FF4. A coincidence circuit 3 detects the above state, and recognizes it as the completion of conversion, and generates the parallel load signal on the register 1 with the next clock. Hereafter, the above operation is repeated at every n-bits.

Description

[Detailed Description of the Invention] [Summary] In a parallel-serial conversion circuit, a flip-flop is provided that inverts and holds the least significant bit of 1n bits of parallel data using an inverter, and the output of this flip-flop is output as serial data. 9 Serial data output operation occurs because the inverted value of the lowest pinpoint, which is injected into the shift register as shift input data at the time of shift operation, is propagated to the 1st to (n-1)th shift register stages of the n-bit shift register. A parallel load signal for setting primary parallel data is generated by detecting the end of the 1 counter, and the circuit size can be reduced. - [Industrial Application Field] The present invention relates to a parallel-to-serial conversion circuit, and particularly to a parallel-to-serial conversion circuit that continuously converts a plurality of parallel data of a fixed length into serial data.

(Prior technology) Parallel converting parallel data to serial data
Serial conversion circuits are widely used in digital circuits.

FIG. 5 is a diagram showing a conventional parallel-to-serial conversion circuit.

In FIG. 5, 11 is an n-bit shift register, 12
1 is a timing generator, and 13 is an n-ary counter.

First, when a timing generator 12 conversion start signal is input, a parallel load signal is output from the timing generator 12, and parallel data is set in the n-bit shift register 11.

Subsequently, each bit of the serial data is output one after another each time a clock is manually input to the n-bit shift register 11, and at the same time, the clock is counted by the n-ary counter 13. When n bits have been output, the n-ary counter 1
3 generates an overflow output, and the timing generator 1
given to 2. As a result, the parallel load signal is output again from the timing generator 12 and the primary parallel data is sent to the n-bit shift register 11.

Thereafter, the above operation is repeated every n clocks.

The serial data valid signal is a signal that indicates whether serial data is valid or invalid, and becomes valid at the same time as the first serial data is output after conversion starts.

[Problem that the invention seeks to solve]

In the conventional example, an n-ary counter is required to generate the parallel load signal, and there is a problem in that the scale of the circuit increases accordingly.

Means for Solving Problem c] The present invention provides a flip-flop that inverts and holds the least significant bit of n-bit parallel data using an inverter, and uses the output as shift input data of an n-bit shift register. .

1st to n-1st of the n-bit shift register.

By detecting whether the contents of each shift register stage up to and including the contents of the flip-flop match, and generating a parallel load signal if they match, it is possible to eliminate the need for a counter and reduce the circuit scale. It is something to do.

FIG. 1 is a diagram showing the basic configuration of the present invention.

In FIG. 1, 1 is an n-bit shift register.

2 is a timing generator, 3 is a one-digit circuit, 4 is a flip-flop, and 5 is an inverter.

The n-bit shift register 1 inputs n-bit parallel data, converts it into serial data, and outputs it.

The timing generator 2 generates a conversion start signal and outputs a parallel load signal.

- the number output circuit 3 detects whether the contents of the first to n-1st shift register stages of the n-bit shift register 1 match the contents of the flip-flop 4;
If they match, a parallel load signal is generated.

Flip-flop 4 inverts and holds the least significant bit of n-bit parallel data by inverter 5.

The inverter 5 is for inverting the least significant bit of the n-bit parallel data applied to the flip-flop 4.

[Effect]

First, a conversion start signal is applied to the timing generator 2,
A parallel load signal is output from the timing generator 2.

The output parallel load signal is applied to the n-bit shift register 1, and parallel data is set in the n-bit shift register 1. At this time.

Data obtained by inverting the least significant bit of the n-bit parallel data by an inverter 5 is sent to the flip-flop 4.

Thereafter, the parallel data input to the n-bit shift register 1 is sequentially shifted out by a clock, and at the same time, the bit value held by the flip-flop 4 is input to the lowest stage.

When the n-th bit is shifted to the most significant bit, the data from the n-1 bit to the least significant bit of the n-bit shift register 1 becomes the same data as that of the flip-flop 4. This state is detected by the minus number construction circuit 3.

The coincidence detection circuit 3 detects that the data from the n-1 bit to the least significant bit of the n-bit shift register 1 is the same data as the flip-flop 4, recognizes that the conversion is completed, and shifts the n-bit data at the fifth clock. A parallel load signal is generated to set parallel data in shift register 1.

Thereafter, the above operation is repeated every n bits.

〔Example〕

FIG. 2 is an operation timing diagram of each part.

The operations of the shift register, flip-flop, and -number structure circuit will be explained using FIG.

The shift register is timing [. Parallel loading is performed at , and shift operation (serial output) is performed between timing t and xjy.

The flip-flop performs FF setting at timing t0, and inputs the FF-Q output to the least significant bit of the shift register during timing t1 to t.

The coincidence detection circuit performs coincidence detection at timing t.

FIG. 3 is an explanatory diagram of the operation of the shift register.

FIG. 3 shows an example of an 8-bit shift register.

The operation of the shift register will be explained in detail with reference to FIG.

At timing t0, parallel data, for example “0100
1101" is input. In this case, the least significant bit is 1", so this least significant bit "1" is inverted by the inverter and #0' is applied to the flip-flop.

Timing 1. Then, it is shifted one bit at a time.

The most significant bit "0" is serially output, and the least significant bit is inputted with "0" held by the flip-flop.

Between timings t2 and t, the bits are shifted one bit at a time in the same way as the operation at timing t1, and the i upper bits are serially outputted to the lowest bits.

“0” held by the flip-flop is input.

At timing t, the bits are shifted one bit at a time.

The most significant bit is serially output and the least significant bit is inputted with "0" held by the flip-flop, which is the same as between timings t1 and t.
A match detection circuit detects whether the content from the bit next to the most significant bit to the least significant bit (“000ooooo” in this example) matches the content held by the flip-flop (“O” in this example). Detect with.

FIG. 4 shows an example of a coincidence detection circuit.

In FIG. 4, 3 is a coincidence detection circuit, 6.7 is an AND circuit, and 8 is an OR circuit.

The AND circuit 6 is for detecting a case where the contents held by the flip-flop and the contents from the bit next to the most significant bit to the least significant bit are all "1".

The AND circuit 7 is for detecting a case where the contents held by the flip-flop and the contents from the bit next to the most significant bit to the least significant bit are all "0".

The OR circuit 8 determines whether the contents held by the flip-flop and the contents from the bit next to the most significant bit to the least significant bit are all "1 degree," the contents held by the flip-flop, and the contents next to the most significant bit. This is intended to function in both cases where the contents from the bit to the least significant bit are all "0".

〔Effect of the invention〕

In the present invention, since no counter is used, the scale of the two circuits can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is an operation timing chart of each part, FIG. 3 is an explanatory diagram of the operation of a shift register, and FIG. 4 is a diagram showing a coincidence detection circuit. FIG. 5 is a diagram showing a conventional example. In FIG. 1: n-bit shift register 2: Timing generator 3 Ni-failure detection circuit 4: Flip-flop 5: Inverter

Claims (1)

[Claims] A parallel register comprising an n-bit shift register (1) that receives n-bit parallel data and performs a shift operation based on a clock, and a timing generator (2) that generates a parallel load signal for the shift register (1). In the serial conversion circuit, a flip-flop (
4), the output of this flip-flop (4) is connected to the n-bit shift register (1), and when the n-bit shift register (1) shifts, the first to n-1st shift register stages are connected. The timing generator (2) is provided with a coincidence detection circuit (3) that detects whether each content of and the content of the flip-flop (4) match and generates a parallel load signal if they match. Features a parallel-to-serial conversion circuit.