JPS6134677A - Image outline processing circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit which can paint out an image at a high speed, by converting outline bit information of an image to paint-out information by an outline bit generating part, etc. for supplying successively said information by setting adjacent N bits on the same line as a unit. CONSTITUTION:The decoding part 11 of an outline bit information generating part 1 decodes and reproduces outline bit information based on an outline data supplied from the outside, stores it in a memory 12, and an output part 13 outputs outline bit information generated based on said information by setting adjacent N bits on the same line as a unit. A paint-out information generating part 2 is provided with a converting part 21 to which processing units of N stages are connected in a shape of a cascade, and a latching circuit 22 for latching temporarily its output, and based on the outline bit information of N bits supplied from the pre-stage, paint-out bit information related to a section corresponding to its N bit information is outputted in parallel. A write circuit 3 writes information outputted successively from the paint-out information generating part 2, in a prescribed address of a memory 4, and a paint-out data is reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image contour processing circuit, and in particular, to a circuit that generates filling information for a character or image (hereinafter referred to as an image) based on contour data of the image. This invention relates to an image contour processing circuit.

[Prior art] As a prior art of the present invention, for example, Japanese Patent Application Laid-Open No. 58-142
There is a technique disclosed in Publication No. 390. In these conventional techniques, in order to fill in the interior of a given image outline, the outline bits determined from the outline data are developed and stored in a bitmap memory, and then the memory is sequentially read bit by bit. Check whether the content is a contour bit or not,
For the section corresponding to the odd-numbered contour bit detected on the same line to the next contour bit, information indicating that the image is present is sequentially written into a separate output refresh memory or the like.

[Problems to be Solved by the Invention] Therefore, in this type of conventional device, data processing takes time due to the checking operation to see if there is an outline bit, and high-speed filling processing cannot be performed.

Therefore, the present invention provides an image contour processing circuit that can fill in an image at high speed with a simple configuration.

No other means to solve problem E] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 2 is a schematic configuration diagram showing an embodiment of an image contour processing circuit according to the present invention.

In the figure, 1 indicates that the contour bit is set to ``1'' and the frame is set to ``1''.
This is a contour bit information generating section that sequentially outputs contour bit information of "0" in units of N bits adjacent to each other on the same line, and is composed of a decoding section 11, a memory 12, an output section 13, and the like.

The decoding unit 11 decodes and reproduces bit information corresponding to the shape of the contour based on, for example, externally supplied contour data 14 (in many cases encoded).
The information regarding the contour bits obtained in step 1 is stored in the memory 12.

Based on the information stored in the memory 12, the output unit 13 generates contour bit information in which the bit corresponding to the contour position is, for example, "1" and the square is "0", and furthermore, the generated contour bit information , adjacent to each other on the same line (N
) output in bits.

2 in FIG. 2, as mentioned above, is a fill information generator equipped with a converter 21 in which N stages of processing units are connected in a cascade, and a latch circuit 22 that temporarily latches the output of the converter 21. and the contour bit information generating section 1
Based on the N-bit contour bit information supplied from
Fill-in bit information (N bits) for the section corresponding to the N-bit information is output in parallel.

3 is a writing circuit, and the filling information generating section 2
The information sequentially outputted from is written to a predetermined address in the memory 4 to reproduce the filled data.

Next, the detailed configuration of the filling information generating section 2 will be explained in the first section.
As shown in the figure.

In FIG. 1, input bit information A1 to An are N-digit contour bits 1 supplied from the contour bit information generating section 1.
~It is information.

Processing units 51 to 5n are provided corresponding to each of the input bit information A1 to An, respectively, and the conversion section 21 is configured by connecting these processing units in a cascade manner as shown in the figure. .

Each of the processing units 5L calculates the logical sum of the input bit information AL of the arbitrary i-th digit of the N-bit information supplied from the contour bit information generation section 1 and the carry-over information 0L-1 from the previous stage.
An OR (logical sum) circuit that generates output bit information BL of the digit, the input bit information AL of the arbitrary i-th digit, and carry-up information B from the previous stage.1. It is configured in combination with an EXOR (exclusive OR) circuit that outputs the exclusive OR with -1 as carry information CL to the next stage, and each of the output bit information B1 to Bn is sent via the write circuit 3. and are sequentially stored in the memory 4.

The latch circuit 22 is the Nth stage (final stage) processing unit 5.
Temporarily latches carry-up information Cn output from n,
The latched information is output as advance information Co to be supplied to the first stage processing unit 51.

The latch circuit 22 is reset according to a command from the R8 terminal each time the operation starts and the processing of one line ends.

[Operation] Next, the operation of the configuration shown in FIGS. 1 and 2 will be explained according to a specific example.

For example, suppose that the contour shape of the image 6 as shown in FIG. 3 is given by the contour data 14.

FIG. 4 is a diagram schematically showing contour bit information on an arbitrary line Lm of the image 6, where "1" corresponds to contour information.

-〇- The output unit 13 sequentially outputs contour bit information of an arbitrary line as shown in FIG. 4 in units of adjacent N bits for each output cycle.

That is, sections I, T1. I[ is the adjacent 8 bits (
The output cycle is shown when the unit is N=8). For example, in the ■th cycle, roi oooo.

A signal ``O'' is supplied to the fill-in information generating circuit 2 as input bit information A1 to 8.

FIGS. 5(I) to (III) are state diagrams showing the relationship between the input/output bit information A, B and the carry-up information C in the converter 21 in correspondence to each cycle ■ to ■ of FIG. 4. be.

The operation of each cycle will be described below with reference to the state diagram shown in FIG.

(2) Operation in the first cycle Since the latch circuit 22 is reset in the initial state of the arbitrary line, it is C0-0.

Therefore, the first stage processing unit 51 has A+ =0 and Go
By ORing =O, 81=O, and by EXOIt, C1-0.

The processing unit 52 in the second stage is A2-1 and O where C+ = O.
R makes it 82-1, EXOR makes 02=1
becomes.

Next, the processing unit 53 in the third stage becomes TB:+=1 by ORing A3-0 and C2-1, and 0 by EXOII.
It becomes 3-1.

Thereafter, the same state is repeated until the eighth stage, and 08-1 is taken into the latch circuit 22, which becomes Go for the next cycle.

(2) Second cycle operation The first stage processing unit 51 is the OR of A1=0 and Co=1.
By this, it becomes B1-1, and by EXOR, it becomes 01=1.

The second stage processing unit 52 is the OR of Δ2-1 and C+-1.
82=1 by EXOR, and 02=O by EXOR.

The processing unit 53 in the third stage is the OR of A3=0 and 02-0.
NiJ: T B 3 = O, EXORk:
"Yotsu" CC3 = 0.

Thereafter, the same state is repeated until the 6th stage, and C6=O.

The processing unit 57 in the seventh stage is the OR of A7=1 and 06-0.
becomes 87-1, and 07=1 by IEXOR
becomes.

The processing unit 58 in the eighth stage is As=O and O of C7-1.
88=1 by R, 08=1 by EXOR
becomes. This C3=1 is taken into the latch circuit 22 as before, and becomes CO for the next cycle.

(2) Operation of the third cycle The processing unit 51 in the first stage is O where A1=O and Co=1.
81=1 by R, 01=1 by EXOR
becomes.

Thereafter, the same state is repeated until the sixth stage, and C6=1.

The processing unit 57 in the seventh stage is the OR of A7-1 and Ca=1
becomes 87-1, and EXOII makes 07=O
becomes.

The processing unit 58 in the eighth stage is the OR of A8=0 and C7-0.
TBg = O, EXORICJ: TC
The score becomes 8-0. And this C3=0 is the same as above 〇
It is taken into the uniform latch circuit 22 and becomes the Co signal in the next cycle.

FIG. 6 is a diagram showing the output bit information 81 to B8 obtained for each cycle, following the example of FIG. 4.

As shown in the comparison between Figure 4 and Figure 6,
The bit information "1" in the figure is information for filling in the section from the odd-numbered contour bit to the next contour bit in FIG. 4.

That is, the output bit information B is the image 6 shown in FIG.
Forms information that fills the inside of.

[Other Embodiments] In the above explanation related to FIGS. 4 to 6, the processing unit 5
Although the case has been described in which the number of stages is eight, it goes without saying that the present invention is not limited to this and can be implemented with any number of stages.

By configuring and connecting each processing unit 5 as shown in Fig. 1, multiple digits of information B can be processed simultaneously in each cycle.
By appropriately increasing the number of stages of the processing unit 5, it becomes possible to obtain fill-in information at extremely high speed.

[Effects of the Invention] As described above in detail, the present invention is an image contour processing circuit that converts contour bit information of an image into fill information; A contour bit information generating unit to supply; a logical sum of input bit information Ac of the arbitrary i-th digit of the supplied N-bit information and carry-up information CL-1 from the previous stage to output bit information BL of the 1st digit; and an EXOR circuit that outputs the exclusive OR of the arbitrary i-th digit input bit information AL and carry information Bt-1 from the previous stage as carry information CL to the next stage. A conversion unit configured by connecting processing units in the Nth stage in a cascade configuration; latches carry-up information Cn output from the processing unit in the Nth stage, and transfers the latched information to the first processing unit; It is characterized by consisting of a circuit with a very simple configuration: a latch circuit that outputs carry-up information co to be supplied to the processing unit of the stage.

Moreover, by operating each cycle of this simple circuit, multiple digits of output bit information B can be obtained simultaneously, and the desired filling information can be obtained extremely quickly using an appropriate number of processing units. This provides a new processing circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing details of the fill-in information generating section constituting the present invention, FIG. 2 is a schematic configuration diagram showing an embodiment of an image contour processing circuit according to the present invention, and FIG. 3 is an example of an image to be processed. FIG. 4 is a diagram schematically showing an example of contour bit information, and FIG. 5 is a state diagram showing the relationship between input/output bit information A, B and carry-up information C corresponding to each cycle 1 to ■. , FIG. 6 is a diagram showing fill information corresponding to the outline bit information of FIG. 4. 1... Contour pick 1 - information generation unit 2... Fill information generation unit 3... Writing circuit 4... Memory 5... Processing unit 6... Image 11... Decoding unit
12...Memory 13...Output section 14...
・Contour data 21...Converter 22 Latch circuit A...Input bit information B...Output bit information C...Carry up information

Claims (1)

[Scope of Claims] An image contour processing circuit that converts contour bit information of an image into fill information, comprising: a contour bit information generation unit that sequentially supplies contour bit information in units of N bits adjacent on the same line; and an OR circuit that generates the logical sum of arbitrary i-th digit input bit information A_L of the supplied N-bit information and carry-up information C_L_-_1 from the previous stage as i-th digit output bit information B_L; Input bit information A_L of the arbitrary i-th digit
and the carry-on information B_L_-_1 from the previous stage, which outputs the exclusive OR as carry-on information C_L to the next stage.
The i-th processing unit consisting of the combination with the R circuit is N
A conversion unit connected in a cascade configuration latches the carry-up information Cn output from the N-th stage processing unit, and outputs the latched information as carry-up information C_0 to be supplied to the first-stage processing unit. An image contour processing circuit comprising: a latch circuit that performs the following steps;