JPS63268198A - Memory test method - Google Patents

Abstract

PURPOSE:To attain a high-speed test method for a memory with high accuracy by compressing an address and a write data by utilizing a write-operating time, obtaining a true signature value automatically, and comparing the result with a read-out time value. CONSTITUTION:A write address information and a write data are inputted in parallel to a linear feedback register LFSR 6-1, and are compressed, so that a true signature value is generated automatically at the tie of writing. Meanwhile, in order to check whether or not data are correctly written in all the addresses of a memory cell array 1, data are read out from the memory by the same address sequence as that of the writing. The address information and reading out data obtained at this time, are supplied to an LFSR 6-2, and its output is compared with that of the LFSR 6-1 by a comparator 7. If the data are correctly written in the array 1 and are correctly read from there, the signature values stored in the LFSRs 6-1 and 6-2 are to be coincidence with each other. Therefore, the memory can be tested accurately and rapidly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a simple, high-speed, and highly accurate memory testing method.

(Prior Art) As a test for random access memory (RAM), many test buttons have been known in the past. If the memory capacity is N bits, the so-called test time is N
As an N pattern test proportional to
Checkerboard pattern tests, N2 pattern tests in which the test time is proportional to N2, walking tests, gear lobbing tests, etc. are known. These are used differently in terms of test time and test accuracy. N-pattern tests are inferior in test accuracy but are capable of high-speed testing, while N2-pattern tests have problems in terms of test time. Used when test accuracy is important but test accuracy is important. An intermediate N3'' pattern has also been proposed.

In recent years, the density of RAM has improved significantly, from 1Mbit to 4Mbit.
With the advent of bit devices, test time has become a major issue. From this point of view, there is active research into test methods that have high test accuracy and can perform high-speed tests.

In addition, a method is being considered in which a test circuit is built into the chip to enable automatic testing.

Representative research from these perspectives is K.Kin.
“Build” by oshita, ni, ni, 5aluja
t-In Testing of Me＋＊ory U
sing an 0n-Chip Compait T
asting Scheme” and IEEE.

Transactions on Computers
, vol, C-35, 410゜pp862-870
．． 0ctober 1986.

This method adds a write pattern that takes into account fixed faults in memory cells, address decoding faults, and faults due to the influence of neighboring cell contents, and then reads the memory contents by sequentially specifying addresses. This is a simple test method in which the number of "1"s is counted, or the number of "1s" is counted based on logic (counting logic) that takes into account data from neighboring cells, and compared with the correct value.

In this method, control is executed by a microprogram built on an on-chip, and correct values are also built into this for comparison testing. Therefore, even though it is a simple test method, it is not necessarily easy to control since it requires the use of a microprogram and the need to prepare correct values in advance.

Furthermore, the increment of the address is, in principle, in the form of adding 1, and there is a problem in that the margin test of the address decoder is performed by changing the address irregularly, which is not sufficient.

In addition, these simple test methods include, for example, counting the number of '1's in the read data and comparing it with the correct value.
This method has the problem that addresses are often separated and tested, and the test method is not necessarily highly accurate.

(Object of the Invention) The object of the present invention is to provide a method that eliminates the need to obtain the correct value in advance.
The objective is to provide a simpler, more accurate, and faster testing method.

(Structure of the Invention) (Characteristics of the Invention and Differences from Conventional Technologies) The present invention inputs both address information and write data in parallel to a linear feedback shift register (LFSR), compresses them, and detects the correct answer at the time of writing. By automatically generating a signature value for the memory, incrementing the address during reading in the same way as writing, and compressing the address information and read data in the same way and comparing them with the previously determined signature value, memory failures are automatically detected. The main feature is that it can be tested.

In conventional technology, the correct signature value and correct count value generally vary depending on the written data and must be determined in advance through simulation, etc., whereas in this technology, the correct signature value and correct count value are determined using the writing time. The major difference is that it is automatically generated.

Furthermore, the present invention differs from conventional simple test methods in that a pseudo-random pattern is generated for address information using a linear feedback shift register (LFSR), so that a marginal test of the address decoder can be performed.

Furthermore, since the present invention compresses both address information and data at the same time, it is possible to test unique data for a unique address, compared to conventional simple test methods that only test read data. Therefore, highly accurate tests can be performed.

(Embodiment) FIG. 1 is a block diagram of an embodiment for realizing the test method of the present invention, in which 1 is a memory cell array, 2 is an address decoder, 3 is a write data register for storing write data, and 4 is a block diagram of an embodiment for realizing the test method of the present invention. A read data register for storing read data; 5 is an address generator; 6-1, 6-2 are parallel input LFSRs 1 having the same configuration; however, 6-1 is an address information output from the address generator 5 and a write data register 3;
6-2
inputs the address information output from the address generator 5 and the read information output from the read data register 4.

, and 7 is a comparator which compares the outputs from 6-1 and 6-2 on a one-to-one basis and outputs the result.

Generally, the memory configuration of the memory cell array 1 is 2m words-b
In the case of a bit configuration, that is, in the case of a memory configuration in which the word direction is 2m and the write or read data bits are b bits at the same time, the address information output from the address generator 5 is a bit, write data register 3 or read data register 4. The data output from 6-1 or 6-2 is b bits, and the signal line input to 6-1 or 6-2 is (a +
b) It is a bit.

In this test method, first, address information indicating the position to be written and the write data are sent to the LF of 6-1.
Input to SR in parallel. At this time.

The input to the LFSR is (a+b) bits, and every time the address is incremented, the LFSR clock is added in synchronization to increment the shift register.

On the other hand, the address generator 5 is an LFSR consisting of a bits.
Therefore, (2'-1) different addresses can be randomly generated.

The configuration of the LFSR that generates (2a-1) patterns is:
It is generally determined based on a primitive multi-diagram, and its structure, operating principle, etc. are described in Miyakata, Iwadare, and Kiben, "Coding Theory," Shokodo, pages 112 to 135. In this case, A
If the LFSR shift register uses the reset state for the address 11'O', 2m random addresses can be generated by adding (2'-1) LFSR clocks.

At 6-1, such an address and its unique write data are input to the LFSR and compressed by advancing the clock.

When 21 addresses have been added, the final compressed value (signature value) is stored in 6-1.

Next, in order to check whether or not the data written to all addresses in the memory cell array A1 has been correctly written, the data in the memory is read out using the same address sequence as in the writing. The address information and read data at this time are 6-1, which is an LFSR with the same structure as 6-1.
Added to 2.

Therefore, if the correct data is written to the correct address in the memory cell array 1 and can be read out correctly from the memory cell array 1, then when 2a1 address and read data are added in 6-2, the data in 6-1 is It should match the stored signature value.

Reference numeral 7 denotes a comparator, which is composed of (a+b) two-manual exclusive OR gates, and outputs the results by ORing the results from each gate.

Therefore, if data is not correctly written to or read from memory cell array 1, there will be a difference in compression in stages 6-1 and 6-shi, and this will be saved until the final stage. The final compression values are different for both, and a failure can be detected by setting the result of comparator 7 as 11'.

Here, the operation of the parallel input LFSR used in 6-1 or 6-2 will be explained using a simple example.

FIG. 2 shows four shift registers S. -83 parallel inputs (9° to 93 parallel inputs) LFSR is an example.

The feedback of the output value of this final stage shift register is determined by the irreducible polynomial g(x)=x'+x+1,
In this case, it is added to exclusive OR gates 8° and 8□ located at the inputs of So and 81.

Further, the other inputs of each exclusive OR gate are the outputs of the shift registers in the previous stage, and data 90 to 9 . . . are added in parallel. It is.

This 9°~9. contains both the address information a bit and the (write or read) data bit mentioned above = m=
This is data corresponding to (a+b) bits. C is a clock, 96-9. A clock is input every time information is input to the shift register to shift the contents of the shift register to the next stage.

In general, the contents of the shift register of the LFSR are:

It can be expressed as the product of a characteristic matrix T determined by g(x') of order m and an input data vector e of order m. An irreducible polynomial.

g (x) = Σ giX' r go”g++
When +=1, T can be expressed as an m×m square matrix as follows.

In the example shown in Figure 2, From g(x)=x'+x+1, it can be expressed as follows.

To this LFSR, a process having m bit width is applied. ,■□.

・・・＃工、、-z＋I. If n data of -2 are input in this order, as a result of the intermediate shift stage, 5l(
i=ot ip ·I n-1) can generally be expressed by the following formula.

S, = IieSl-1-T -----・-
(1) i=Or 1 + ”・t n 1 (s-0
=0) Here, S,,I, is an m-th order row vector,
e indicates exclusive OR.

In the example shown in FIG. 2, the following input data of n=4 pieces are input in the order of I, → IW1 → I w2 → I w3.

Address Write data■,. =(00;11) In this example, the address is the first two bits, and the write data is the second two bits.

The address in this case can be generated by a two-stage LFSR created by an irreducible polynomial of
2, 3) can be expressed as follows from equation (1).

S, ,=1.
=(0011)S, =If169S, -T=1.
．． 1lEI1. ,,-T = (1
010)S,=1. , fEEIS, -T=Iw26EI
1. , -Te1. , -T" = (1000)
S,=1. Φ52-T=1. JI, -TeI, -T"@
1. ．． -T”=(1110) Therefore, S w3 is the signature value in this case example. From this it follows that 6-1 can be used to automatically create the signature value on write.

Next, the readout is done. →I wt→■, 2→XW are executed with the same address increment. In other words, the addresses are in the order of (00) → (01) → (11) → (10),
The data read from this will be processed, respectively. tIwi*
If it is the same as the data in Iwz+Iw3, the final value obviously matches SW3.

Suppose now that the input to the LFSR at the time of reading is. That is, suppose that a 1-bit error (indicated by Q in the above) occurs in the read data of l1lL and □. At this time, the compression value of LFSR is 5I1
0,5I11. SR2 and SR3 are as follows from equation (1).

S++o=(OO11) SI11=(1000) S++2=(1001) S,l3=(0011) From now on, SR3≠5If3, and unlike the compressed value and the correct signature value at the time of reading, an error can be detected.

In the above explanation, the length of the LFSR as a compressor is basically (a + b) bits, but in the case of a memory with a large word direction and a large address bit length a, it is space compression to create a shorter LFS
It is obvious that the R structure may be used. In this case, since the object to be inspected is mainly read data, compression of b must be avoided.

Further, in the present invention, no particular mention is made of the contents of the write data.

That is, in order to test the influence from memory cell adjacency, a checkerboard pattern (Ol #
A checkerboard pattern for writing l1 may be adopted. In this case, the data to be written to the address may be determined in advance and input to the write data register 3.

Furthermore, the address generator used in the present invention can easily be configured with additional control signals and gates to function as a normal address register during normal online operation and as an LFSR during testing. be.

(Effects of the Invention) As explained above, the present invention does not require the signature value to be determined in advance, and the correct signature value can be automatically determined by compressing the address and write data using the write operation. This has the advantage of being a very simple test method.

In addition, L is used to generate address information that changes randomly.
Since FSR is used, it has the advantage of being able to perform marginal tests of the address decoder as address information changes.

In addition, it is easy to control and the test circuit has a simple configuration, so it is suitable for random access memory, etc.
It has the advantage that these circuits can be mounted on a chip, and automatic tests built into the chip can be configured relatively easily.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment for realizing the test method of the present invention, and Fig. 2 shows an example of LFSR using a fourth-order irreducible polynomial and the process of compressing input information using this. It is a diagram. 1...Memory cell array, 2...Address decoder, 3...Write data register, 4...Read data register. 5...Address generator using LFSR, 6-1.6-
2...Parallel input LFSR17 having the same configuration...
Comparators, 811-83... exclusive OR gates, 9°-9.・
...Parallel input information, 80~S,...Shift register, C...Clock. Figure 1 1B11 Human power LFSR Figure 2 (OOI Il'SW. (I OI O)lISwl (I OOOl"5W2 (I I
I 01g5w38o~83...Jyota fishing#Riwa'7''-)90~9s -tt column input information board So~S3 ° shift register C ° Click

Claims (1)

[Claims] 2^ For a memory with a-word-b-bit configuration, a-bit address information is generated by a linear feedback shift register (LFSR), and at the same time a predetermined bit length data is written to the memory, the corresponding Input (a + b) bits, which are both address information and write data, in parallel to a separately provided LFSR for writing information compression of length (a + b), and according to the 2^a addresses generated in the address generation LFSR, When the specified data is written to all memories, the LFS for compressing the written information is
The result generated in R is used as the correct signature value, and then a read operation is executed with the same address sequence as the write operation, and a read information compression LFSR having the same structure as the write information compression LFSR is separately prepared. , input the read address and (a+b) bit information of the read data to this, and write the corresponding LFS in the same way as the write operation.
The normality of the memory is tested by compressing it in R and comparing the compressed value generated at the end of the read operation with the 2^a address sequence with the correct signature value generated during the write operation. A memory test method characterized by: