US3686631A

US3686631A - Compressed coding of digitized quantities

Info

Publication number: US3686631A
Application number: US873794A
Authority: US
Inventors: Joseph E Elliott
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1969-11-04
Filing date: 1969-11-04
Publication date: 1972-08-22
Anticipated expiration: 1989-08-22
Also published as: BE758268A; CA957073A; DE2053341A1; GB1328266A; FR2071741A5

Abstract

A digital code is developed for alphanumeric characters to represent areas covered by the characters in digital form; this code is compressed by comparing full count codes of successive linear arrays of areas with a preceding scan and representing the differences in successive scans by a change code. The compressed data codes of the characters are fed from storage to an expansion system which restores the codes for the individual scans to full count form for control of photocomposing apparatus.

Description

States Patent 1 51 Elliott 1451 Aug. 22, 1972 COMPRESSED CODING OF DIGITIZED 3,347,981 10/1967 Kagan et a1. ..178/6 UX QUANTITIES 3,225,333 12/ 1965 Vinal ..340/203 X 3,293,605 12/1966 Moore ..340/204 X [72] Inventor Boulder 3,449,726 6/1969 Kawamoto Ct 31.....340/324 x [73] Assignee: International Business Machines 3,439,753 4/1969 Mounts et a1. ..325/38 R Corporation, Armonk, NY. 3,483,317 12/1969 Groat ..178/6 3,502,806 3/1970 Townsend l78/7.1 [22] 7 1969 3,524,926 8/1970 Starr et al ..325/38 B [21] Appl. No.2 873,794

Primary Examiner-Maynard R. Wilbur Assistant Examiner-Leo H. Boudreau [52] 22 55 551 Attorney-Littlepage, Quaintance, Wray & Aisenberg [51] Int. Cl. ..G08c 9/00 57 ABSTRACT [58] Field of Search ..340/146.3, 177, 203-206,.

340/324; 178/6 BW, 15, 7.3, DIG. 3, 7.3 D, A digital code is developed for alphanumeric charac- 73 R, 75 D 75 R 88 89 6 7 11235/92 ters to represent areas covered by the characters in 54 38 digital form; this code is compressed by comparing full count codes of successive linear arrays of areas with a [56] ,References Cited preceding scan and representing the differences in successive scans by a change code. The compressed UNITED STATES PATENTS data codes of the characters are fed from storage to an expansion system which restores the codes for the in- 3,061,672 10/1962 Wyle ..178/6 UX dividual scans to fun count form for control of 3,230,514 l/l966 Kliman ..235/92 UX photocomposing apparatus 3,295,105 12/1966 Gray et a1. ..340/l46.3 3,305,841 2/1967 Schwartz ..178/6 UX 4 Claims, 13 Drawing Figures CHANGE $0111 ADDRESS 63B m 68 56 BOTCHANGE J 82 COUNT 1o 64 a, 115140111 BUFFER 2 DECODE 1110115115111/ 4 fi SCAN REGISTER 3 65 DECREMENT STORAGE 151011105 J '3 11 4 m 1111111,

L 1111 111 g gg CYCLE END OF L. 60 REGISTER DECODE 52 REQUEST MOVE SCAN MODE scA11cYc1E CONTROL SCAN 04 E00 E00 TART 58 H SCAN DECODE t 1111111 11 ACE LEFT E0 E08 DECO DE DECODE T 74 151 BYTE X 2ND BYTE Patented Aug. 22, 1972 3,686,631

7 Sheets-Sheet 1 FIG.1

COMPUTER DATA IN DATA EXPANDER USE DATA CYCLE, BUSS EOC V MSPLAY CONTROLS FIG. 2

INVENTOR 5 JOSEPH E.ELL|0TT eak a c Que. mi anc m/ y 7 '41: :2 A 0:7

ATTORNEYS Patented Aug. 22, 1972 3,686,631

7 Sheets-Sheet 5 FIG. 4 91 01 CLOCK 52 as USE CYCLE REQUEST 94 95 9s MOVE SCAN ,s fl 0B 3 FIG. 5

Patented Aug. 22, 1972 3,686,631

7 Sheets-Sheet 4 FIG. 6

LEFT EDGE SPACE ,124 I26 I22 s V A CHARACTER START PRIME OYOLE R 3RD BYTE c 2ND BYTE c FIG. 7

INPUT REGISTER POSITION I 5 BITS/COUNT 6 BITS/COUNT INPUT REGISTER POSITION 2 IST BYTE I BITS/ COUNT 8 BITS/COUNT PRIME OYOLE FIG. 9

16 /I80 I28 A70 CHANGE SCAN ADDRESS NOT 1s CAN I ITEM CYCLE B 4 SET MOVE SCAN EOS Patented Aug. 22, 1972 3,686,631

" 7 Sheets-Sheet 5 8 SCANCYCLE EXCLOR 442 CHANGE COUNT MODE A BUFFER REGISTER 65A A INCREMENT/ A DECREHENT A TO A MEMORY coum SIZE DECODE A FULL coum MODE A A PRIME CYCLE I146 444 14a MOVE SCAN Patented Aug. 22, 1972 3,686,631

7 Sheets-Sheet 6 SET now some: 202 A 5 FULL COUNT UoUF B4 A go R 208 CHANGE INITIAL RESET 201 ZEP COUNT MODE CHARACTER START P V s "206 eoc 490 204 196 192 194 mm V P *OPRIME CYCLE Fwo 1'5 H FULL COUNT LFFU END-NOT E08 BUFFER REGISTER POSITION 0W FULL COUNT ITEM FULL COUNT MODE: 3 =END N0T E05 214 216 S 1 EE|-5FF MOVE SCAN --l I IF R o 212 PRIME CYCLE 240 DATA Patented Aug. 22, 1972 3,686,631

7 Sheets-Sheet 7 FIG. 12

DATA

CHANGE COUNT NDDE FULL COUNT ITEN END- CHANCE SCAN ADDRESS NDT EDS TWD I'S CHANCE DIRECTION ADVANCE 210 260 262 END or NOVE scm $500 INITIAL RESET R QMTIST "E" COMPRESSED CODING F DIGITIZED QUA a IES NATURE AND OBJECT OF INVENTION Typographical matter may be reproduced by transmitting digital codes representing the alphanumeric characters from remote locations or from computer storage to a photocomposing apparatus, which controls operation of a cathode ray tube for recording the alphanumeric characters on sensitive film. Fonts of characters may also be stored for use in control of similar photocomposing apparatus.

The characters, or other images to be reproduced, are coded in digital form by relating to a grid system, the coordinates of which denote the areas covered by the character, and a digital code is developed denoting the areas of each character. This code may then be transmitted or stored for control of the photocomposing apparatus. Such a character as outlined on a grid in black areas is illustrated in FIG. 2, in which the coordinates of the black elemental areas forming the character are designated by digits.

Each column or linear array of the white or blank areas is counted, then the number of black or unblank areas to the next blank area, etc. Thus, as the numbers of blank and unblank areas along each array, or each scan, are recorded, the counts of the scans all are sets of digits, each set representing the items of one column of blank and unblank areas, and as a whole, the character itself. This set of digits, or character block, if in binary digits, may be transmitted to a photocomposing apparatus to write the character with the cathode ray tube beam, or stored in a memory for future use in the same manner.

Applicant has discovered that the number of digits necessary for a record of a digitized character may be reduced substantially, that is, the code for a digit may be compressed, by representing the changes in counts of successive scans instead of the full counts. The first linear array of areas which forms the first scan is represented by counts of blank areas and unblank areas in the array, and then the results of the next scan are compared and the changes in length of the blank and unblank areas are registered. This registering by a change count code substantially reduces the number of digits to be stored or transmitted. For control of a photocomposing apparatus, the code is expanded, or restored to its original full count form, by modifying each preceding scan by its change code to produce the full code, which is registered to actuate the photocomposer.

It is the object of this invention to compress the digital codes denoting the coordinates of alphanumeric characters or other images by a change count of successive linear arrays or scans compared with preceding scans denoted by full counts, and to expand such code after storage and/or transmission to its original form for representation of a character or image and for use as controls of photocomposing apparatus. In the practice of this invention, the sensitized elemental areas which form each character, variously known as black or unblank areas, are located along each scan, or column of areas by counting the number of white or blank areas and black or unblank areas scanned successively in each linear array. The next succeeding scan may then be recorded by designating the changes in lengths of the areas compared to the preceding scan.

The compression of the codes for the quantities representing counts of scan items for digitized characters is only one application of the broader concept of reducing the digital representation of sets of variable quantities. In a similar manner, any set of variable quantities may be successively registered by the use of the compressed coding system to transfer or store new values after registering base values of such quantities.

THE DRAWINGS FIG. I is a diagrammatic view of a photocomposing system embodying the invention.

FIG. 2 illustrates the representation of a character on a coordinate grid network.

FIG. 3 is a general schematic view of the basic units of the data expanding apparatus to register the complete data for control of the photocomposing apparatus.

FIG. 4 is a schematic of the clock circuit to furnish control pulses for the data expanding circuits.

FIG. 5 is a schematic of one input register which receives the character data from the computer storage.

FIG. 6 is the space decode circuit for blank spaces along the left margin of a character.

FIG. 7 is the full count size decode circuit, which fixes the number of digits to be used for the items of each scan.

FIG. g is the memory input gating circuit which controls the transfer of complete data to the storage and output registers.

FIG. 9 is a schematic of the scan address controls circuits and registers for controlling the address of the storage registers.

FIG. It) is the mode control circuit which sets the operation of the expanding system in either the full count or change count mode.

FIG. 11 is the end-of-scan decode circuit which signals the change to successive scans.

FIG. 12 is the change count decode circuit for controlling operation to expand into the full count code for successive change count scans.

FIG. 13 is the end-of-character circuit to denote the completion of a character.

TECHNICAL DESCRIPTION Referring now to FIG. I, the relationship of the data expander to the photocomposing system is schematically represented. Computer 10 supplies display data in coded form to the data expander 12. The editing of the text and the choice of fonts to be used is controlled in the computer lb. The final formatted text is passed to data expander in a compressed code. Data expander 12 then decodes the data and provides the control signals to the display controls 13. The display controls provide drive signals that enable the cathode ray tube 14 to print the text material on photographic film 16.

The operation of the display controls 13 is described in detail in copending patent application, Ser. No. 682,845, filed Nov. 14, 1967, entitled Reciprocating Lens Photocomposer, and invented by J. L. Overacker and owned by the same assignee. The cathode ray tube I41 displays one vertical scan at a time, and lens I8 focuses that scan onto film 16. When the next adjacent scan is to be printed, the scan appears at the same place on the face of the cathode ray tube, and the lens is indexed horizontally to move the scan line horizontally on the film. Accordingly, a character is painted onto the film by a series of vertical scans of the cathode ray tube with a slight horizontal adjustment of lens 18 between each scan.

A control for the reciprocating lens motor to position lens 18 is described in copending, commonly assigned patent application, invented by V. C. Martin Ser. No. 871,932, filed on Oct. 28, 1969, and entitled Photocomposing System."

In FIG. 2, the lower case character e is shown as an example of a character broken down into small blocks. For simplicity in understanding the operation of the invention, the scans in the example of the letter e have been numbered along the bottom of the letter, while the vertical bits in the scan have been numbered along the left side of the e. A bit is here defined as one block in a scan. The e, as shown in FIG. 2, appears very crude, and is not of print quality. However, with many more bits per scan and many more scans per inch, the print quality of the e can be made extremely high with to the left, although coding could be done from either direction) and denoting the change per scan item. An additional rule to be followed in compressing the data in Table I is that when the number of scan items change from one scan to the next, it is necessary to change some of the scan items from change-count items to fullcount items. A full count is the number of bits contained in a scan item, while a change count is the difference in number of bits between the scan item in the present scan and the same scan item in the preceding scan. If the number of scan items decreases from the number in a previous scan, the last scan item of a scan must be coded as a full count. If the number of scan items increases, the scan item corresponding to the last scan item of the previous scan and all remaining scan items must be coded as full counts. Also, any time a scan item changes by a large amount, that scan item and all remaining scan items of the scan must be coded 20 as full counts. With these simple rules, Table 11, shown below, may be generated from Table I.

TABLE II 1 I) 1 +1 -1 (l l) 0 ll +1 1 +1 0 +1 +1 +1 0 +1 0 (l U U -l (I 1 l (l (l i] U (l l) t) (I O (I U 0 (l U +l +1 +1 (1 +1 I] 0 (J 0 i1 1 0 l l -1 U 1 +1 1 U l] 0 ll 0 +1 -1 +1 0 i1 -1 0 1 U l) 0 0 l) U 0 +1 +1 It) 11 12 13 14 1G 17 18 19 21 22 23 no discernible discontinuity along its outer periphery. The transition between Table II and Table I is as fol- With the grid overlying the character e as in FIG. 2, it is possible to arrive at a data code for the e by splitting up each scan into a series of alternating black and white scan items. The length of a scan item is measured by the number of bits (blocks) in the scan item. The starting position for the scan is at some vertical reference position below the character. For purposes of the example in FIG. 2, it is assumed that the vertical reference position for each scan is three-bit positions below the lowest portion of the character. The top of the scan for a character is defined by the last black scan item in a scan.

In scan 4, the first scan item is white and is 13 bits in length. The second scan item is black and is seven bits in length. Because the vertical reference position is below the character, the first scan item in each scan will always be white. The scan items will then alternate black and white. The following table may be built up as,

a code for the scan items in the character 2 shown in FIG. 2. On the vertical coordinate of the table, the white and black alternating scan items are indicated. On the horizontal coordinate of the table, the number of the scan is indicated.

Scans

1, 2, and 3, and scan 30 are not in Table I because these scans, as can be seen in 55 FIG. 2, do not contain any pieces of the character.

lows. Scan 4 is the first scan through the character, and, accordingly, the scan items must be full count items. Scan 5 is the second scan through the character and contains the same number of scan items as scan 4. Therefore, scan 5 may be indicated by change counts relative to scan 4. Similarly, scans 6 and 7 are indicated by change counts relative to the size of the same scan item in the preceding scan. For example, in scan 7, from Table I, it is clear that the first item decreased from magnitude 8 in scan 6 to magnitude 7 in scan 7. Accordingly, the first item in scan 7 is identified as negative 1. Similarly, the second item in scan 7 increased from 16 in scan 6 to 18 in scan 7. (See Table 1.) Therefore, in Table H, the second item in scan 7 is indicated as being a+2.

A comparison of Tables I and II with FIG. 2 shows that from scan 7 to scan 8, the number of scan items change. Therefore, it is necessary for the code to revert to full counts to code the last three scan items in scan 8. Likewise, scan 9 also increases in scan items from scan 8, and, therefore, the last three items of scan 9 must again be coded as full-count scan items.

Scan Eli contains the same number of scan items as in both scans 9 and 10 is five bits in length, and, the

TABLE I 3 4 5 5 6 6 b (i (i G 5 5 4 3 2 B 7 5 5 4 5 4 4 4 4 4 4 5 4 5 5 ii (i 5 4 2 4 7 G 5 4 4 3 3 3 3 3 3 3 3 4 4 5 5 6 7 8 10 16 Sean 4 5 6 7 S J 10 11 12 13 14 15 1G 17 18 19 2G 21 22 23 24 25 26 27 28 29 As pointed out earlier, it is desirable to compress the change count for that scan item is 0 in scan 10. By

code shown in Table 1 into a code showing only the changes between scans. Accordingly, a second table can be generated from the first by comparing each scan with the preceding scan (usually the scan immediately comparing scans 9 and 10 in Table I, the difference, or change-count code, can be arrived at for insertion in scan 10 of Table 11. Similarly, scans 11 through 24 will all be change-count coded since all of these scans conscan 9, and is change-count coded. The first scan item.

tain the same number of scan items. One point of interest starts at scan 15 where a comparison of

scans

14 and 15 in Table 1 indicates that these scans are identical.

Therefore, scan 15 in Table II contains all Os for the scan items.

The change back to full-count items occurs next at scan 25. Scan 25, in FIG. 2, is where the intersection between white and black segments of the character drop from 6 to 4. The last count of scan 25 is then fullcount coded. Scans 26 through 28 are change-count coded since they also contain four scan items, just as scan 25. Finally, scan 29, which is the last scan through the character, is full-count coded starting with the first count since the first count change from scan 28 is +6. This change could have been coded as a change count, but is not because the change is relatively large.

DATA COMPRESSION CODE The code utilized by the computer to send compressed data to the data expander follows a set of rules. The code is binary and in this case contains eight bits per byte. Data from the computer is sent over to the expander, one byte at a time. As will be seen later, the data expander contains a serializer so that effectively the data expansion works on a bit at a time as the data is received out of the serializer.

Continuing with the set of codes, the first bit, or bit zero, in the first byte indicates whether there is a leftedge space preceding the start of the character, or no left-edge space. A 0 indicates no space and a l indicates space. Also, if there is left-edge space, the number of scans in the left space will be indicated by the count to be received in the second byte.

Bits one and two of the first byte are a two-binary code to identify the four possible count sizes for fullcount items. The code is as follows.

The EOS bit is an End-of-Scan flag bit in a full-count scan item. If the EOS bit contains a 1 that full-count item is the last scan item in a scan. Accordingly, if the counts are of a magnitude that seven hits plus an EOS bit are required to specify a scan item, then bits one and two will contain a 1 and 0, respectively.

Bits three through seven of the first byte are unused in this invention. They may be used for check bits or other data processing functions.

After the first byte, or the second byte, the data expansion proceeds on a serial-by-bit basis. Whether this serial operation starts after the first byte or after the second byte depends upon whether or not bit zero in the first byte indicates left-edge space data. lfbit zero is a l the number of blank scans in left-edge space is the content of the second byte. If bit zero in the first byte is a 0, this indicates that character data begin immediately with the second byte, and, therefore, serial-by-bit operation begins with the second byte.

Once the expansion of character data has begun, the following codes are used. If the end-of-scan bit is a 1 then the full-count item containing this bit is the last scan item in a scan. The end-of-scan bit is the first bit in a full-count scan item. Accordingly, if there are seven bits per full-count scan item, these will be proceeded by an end-of-scan bit, so that in total there will be eight bits defining a full-count scan item. Once the code, as previously pointed out, defines the size of the full-count scan item, that size is retained throughout the data expansion of the entire character.

If an end-of-scan signal occurs, the first scan item of the next scan is treated as a change-count scan item. The data expansion hardware will be triggered automatically to go to a change-count mode of operation. To return to full-count mode of operation, the data expander must receive the code 111. If 1111 is received by the data expander, this indicates end-ofcharacter. 1

The change-count codes are as follows. A single 0 in a bit position indicates that the scan item in the present scan is the same as the scan item in the preceding scan. If the change count is other than 0, the magnitude of the count is defined by a variable length word, the beginning and the end of the word being defined by a binary 1" and the number of 0s between the two binary ls indicating magnitude of the change. Accordingly, a code 0 10001 indicates a change count of 3, while a code of 101 indicates a change of one.

As to the sign of the change count, if the code contains two ones at the beginning of a change-count item, the direction of the change is opposite to the direction of the change for the same scan item in the previous scan. For example, a 110001 indicates a change count of magnitude three plus a change in direction from the change count for that scan item in the previous scan. If the scan item in the previous scan was a full-count scan item, it is assumed that the change count in this next scan will be positive or additive to the full-count item of the preceding scan. Therefore, if the change count scan item which first follows a full-count scan item in the preceding scan is negative, then the first change-count code for the change-count scan item must have a l l as the beginning of the change-count scan item.

The following Table 111 indicates some of the codes as they would be sent from the computer to the data expander for the letter e of FIG. 2. The codes are indicated on a scan-by-scan basis, except for the first line which indicates the first two bytes of the display data. Also, the codes below contain a space which would not be present in the data. The spaces are added here to aid the reader in picking out the end of each binary word.

TABLE III Scan Serial date Scan The first two bytes of data from the computer indicative of character information are indicated at the top of Table HI. Bit zero of the first byte contains a 1. Accordingly, the second byte indicates the number of scans at the left edge of the character before the character scans start. In the example in FIG. 2, there are three scans, and, accordingly, the second byte con tains the binary indication for three.

Returning to the first byte, the bits in the l and 2 positions of the byte are Os indicating that the full-count items for the character to be generated will be five bits in length plus an end-of-scan bit. The remaining bits in the first byte are indicated by Xs as these bits are not used in the invention, and could be utilized by the data processing equipment for other functions.

In the next line of Table III, the binary words for scan 4 of FIG. 2 are shown. Of course, the binary words in Table III would follow one right after the other and are delineated here line-by-line for ease in understanding which binary words are associated with each scan. The binary words for full-count items will be five bits plus anend-of-scan bit as the first bit of each word. The first binary word has a at the first bit position, indicating that this scan item is not the end-of-scan. The next five bits indicate the magnitude of the scan item-in this case, a count of 13. This corresponds to the 13 for the first scan item in the fourth scan, as indicated in Table II. The second scan item defined by the next binary word contains a 1 in the first bit position of the word indicating that this scan item is the end of the scan. The count in the binary word is seven and, of course, corresponds to the seven bits, or blocks, in the second scan item of scan 4 as indicated in Table H.

Scan 5 is the first scan which is change-count coded. In Table II, the first scan item for scan 5 is indicated by the first binary word for scan 5. This binary word indicates that a change of three is required, and that the change should also begin a direction opposite to that which the decode hardward is presently set for. Accordingly, a change in sign must be coded into the data sent to the data expander. The change in sign, as explained previously, is signaled by a second binary l in the change-count binary word. According y the first binary word for scan 5 indicates a change of negative three as required by Table II. The second binary word in scan 5 indicates no change in sign and a change count of 5. Accordingly, the second binary word for scan 5 calls for a change of +5 as indicated in Table I! for the second scan item of scan 5.

The second scan item of scan 5 contains no end-ofscan signal because the end-of-scan condition during change-count mode of operation is handled by the hardware in the data expander, as will be explained hereinafter.

The binary words for

scans

6 and 7, as shown in Table III, represent change-count codes and are developed in the same manner, as just explained for scan 5. Notice that no change in sign is required because the same scan item in adjacent scans is changing in the same direction.

The binary words for scan 8 represent a significant departure from the binary words in scan 7 because the number of scan items changes from 2 to 4. As explained previously, when there is a change in the number of scan items, the operation of data expansion reverts to a full-count mode for some scan items. The binary words for the last three scan items in scan 8, as shown in Table III, are full-count items.

The second binary word consists of three binary l s. This is the code signal indicating a change to a fullcount mode. This code signal causes the data expander to change to a full-count mode of operation. The next binary word is the full count for the second scan item of scan 8. The first or end-of-scan bit of the word is 0 indicating that the second scan item is not the end-ofscan. The count indicated by the binary word is 7 and corresponds to the size of the second scan item as indicated in Table II. The remaining binary words in scan 8 indicate the size of the scan items by full counts. Of course, the last binary word for scan eight contains a binary 1 at the first or end-of-scan bit position indicating it is the last scan item in scan 8.

The end-of-scan signal at the end of the previous scan 8 causes the data expansion hardward to auto matically change to a change-count mode of operation for scan 9. As can be seen from FIG. 2 and Tables I and II, scan 9 differs in number of scan items from that of scan 8. Scan 8 contains four items and scan 9 contains six. Therefore, the last three scan items of scan 9 must be coded as full-count items. The fourth word for scan 9 in Table III is three serial binary ones, l l l, indicating a change to full-count mode. The full count binary words for the last three scan items in scan 9 are then indicated in Table III. The last scan item contains a binary one at the first or end-of-scan bit position and indicates end of the scan.

The next scan 10, as can be seen in Table II, is coded entirely in change-count code. Thus, when the data expander automatically changes to change-count mode of operation at the end of scan 9, it is ready to commence decoding, or data expansion of scan 10. The first scan item in scan 10 is zero, indicating that that scan item is unchanged from the previous scan. The second binary word in scan 10 of Table III indicates a change of l The third binary word in scan 10 indicates a change of +1. These changes correspond to the changes indicated in Table II and are decoded in the same manner as previously described for scans S, 6, and 7.

The next scan that is significantly different in procedure is scan 15. By examining

scan

14 and 15 in Table I, it is clear that the scan items in these two scans are identical. Accordingly, the change count for scan 15 in Table I1 is a series of zeros. Likewise, in Table III, the change-count code for scan 15 is a series of binary words where each binary word is a single bit, and that bit is a zero.

in scan 25, there is again a change to full count mode, signal 111, preceding the last scan item. The last item is therefore a full count item for a count of 10 and also contains an end-of-scan flag 1" as the first bit. The change to full count mode is required so that an end-of-scan flag could be put in the last scan item.

The last significant change in the data expansion code which has not been discussed is shown in scans 29 and 30 of Table IH. Scan 29 is a full-count item scan. Accordingly, as described above, the signal for change to full count is a series of three ones and is the first binary word of scan 29. Scan 29 then proceeds in the typical fashion using full-count items.

Scan 30 is shown only in Table III as scan 30 is the first scan which is not generating a portion of the lower case e shown in FIG. 2. The binary word in scan 30 is a series of four ls. A series of four binary ls is the code which indicates to the data expander that end-ofcharacter has been reached.

DATA EXPANDER So far, the description has dealt with the code which the data expander works with. The coding of the scan items into full-count and change-count items is necessary to the invention, which also includes restoring the data to its original full-count state. The significance in the code is the fact that the great percentage of the data may be change-count coded, and, thereby, save transmission or storage in a computer operating controls. The gist of the invention is the storage or transmission of compressed data and the use of data expander circuitry to expand compressed data into full counts, whereby the data may be used for display or controls, as for example, in a photocomposer. A preferred embodiment of the data expander is shown in FIG. 3.

The connections of the functional blocks in FIG. 3 are complete, with the exception of timing signals and reset signals. The timing and reset signals will be pointed out in later figures which show the detail implementation of the more unusual blocks shown in FIG. 3.

The flow of data from the computer enters input register 50. The data from the computer arrives in eightbit bytes. The input register 50 contains a parallel storage array for storing the eight bits in parallel as they arrive. The register also contains hardware for thereafter serializing the parallel bits into a serial string of eight bits. At the output of the input register 50, there is indicated the -bit, the l-bit, and the 2-bit positions. The O-bit position is the serial data output position. The 1- and 2-bit positions contain the full-count size information, or code, when the first byte of character data is received at the input register. Accordingly, the 1-bit and 2-bit positions are passed to a full-count size decoder 52, which will be described hereinafter.

In addition, the input register has an output cable carrying all eight bits of a byte in parallel out of the register. This cable is provided so that left-edge space counts can be passed in parallel as a full byte out of the input register through AND gate 54 for storage in memory 56. AND gate 54 is represented as a single AND gate in FIG. 3. In fact, the AND gate 54 would consist of a plurality of eight AND gates in parallel with each AND gate passing one-bit position in the byte. The two controlling gating signals for AND gate 54 are applied to all eight of the AND gates to enable each AND gate to pass one bit of the 8-bit byte.

One of the enabling signals for AND gate 54 is the left-edge space signal generated by space decode 58. The function of space decode 58 is to indicate when there is a left-edge space preceding the scan items of a character and also to indicate character start, i.e., begin of scan items. The space decode responds to the input serial data, to a prime cycle signal from mode control 60 and to a first byte, a second byte signal and a third byte signal from the computer. The first, second and third byte signals are pulse signals which accompany, in time, the first, second and third 8-bit bytes of character information at the beginning of each character. The second byte pulse is also used as an enabling signal for AND gate 54; so that only the second byte of input character data is passed to storage in memory 56. It is, of course, only the second byte which contains left-edge space countif there is a leftedge space at the beginning of a character. The operation of the space decode 58 will be described hereinafter with reference to FIG. 6.

When the first byte of eight bits is in the input register, the full-count size decode is active to identify from the one and two bits of the 8-bit byte what the size of full-count items is for the character about to be photocomposed. The full-count size decode 52 responds to the 1-bit and 2-bit positions in the input register and the prime-cycle signal from the mode control 60 and, also, to the first byte indication from the computer. Its function is to decode the one and two bits and identify the size of the full-count items and convey this size information to the memory input gating 62.

The function of the memory input gating is to control whether data from cable 63, or data from cable 64, or serial data from line is gated into the memory 56. The memory 56 operates on a cyclic basis with each cycle being divided into a write time and a read time.

The remaining input lines to the memory input gating 62 are the lines which provide the control signals to control which data flow into the input gating is passed onto memory 56. The signals passed via cable 66 from the mode control are prime cycle, full-count mode, and change-count mode. In full count mode operation, the memory input gating is receiving serial data over line 65 and acts to store that data in parallel in memory 56 by a recirculating operation operating with buffer register 68. As each bit in the serial string of data is applied to the memory input gating, it is passed to the memory during the write time. During read time of the same cycle, the bit is passed to the buffer register, and from the buffer register 68 back over cable 63 and 63A to the memory input gating 62. During the next cycle of the memory, the next bit in the serial data string is written in parallel with the first bit into the memory. During the next read time the two bits are then passed to the buffer register 68 and recirculated back to the memory input gating as before. This recirculating procedure continues until all the bits of a full-count item as specified by the full-count size decoder 52 have been assembled at a scan address in the scan storage section of memory 56.

During change-count-mode operation to be described in detail later on, the count-item (or scan item) is read from scan storage section of memory 56 into buffer register 68 and recirculated back to the increment/decrement '70 where it is changed according to the change-count signal and gated by the memory input gating back into scan storage.

During the assembly of full-count items and also the updating of previous scan items by change counts, the memory controls issue a scan-cycle signal which enables the memory input gating 62 and scan address controls 74. When a full scan has been decoded and accumulated in the scan storage area of memory 56, a move-scan cycle of operation begins.

During move scan, the scan items are read from the scan storage section of memory 56 into the buffer register 68. They are then recirculated back over cable 63 and 63A to the memory input gating 62. The movescan signal from the memory controls is applied to the memory input gating 62 and enables the memory input gating to pass the recirculated scan item back into memory 56. This time, during the write time of memory cycle, the scan item is stored in the print-storage area of memory, rather than the scan-storage area. This procedure continues until all of the scan items in a scan have been moved from the scan-storage area of memory into the print-storage area of memory.

There is one other remaining operation of the memory called use-cycle operation. The use cycle is related to the display controls in the actual photocomposing of each scan on photographic film. When the display controls are ready for more scan items to control the display, they generate a use-cycle request signal. When the memory controls receive a use-cycle request signal, they interrupt their other operations, such as assembling full-counts or change-counts, or moving scans, and immediately send a scan-item from the print storage area of memory to display controls. The memory controls generate the use-cycle signal which gates AND gate 72 to pass the scan item from the buffer register to'the display controls. As soon as the scan item has been passed from the print-storage area to the display controls, the memory reverts back to its previous operation which may have been either scan cycle or move scan. The AND gate 72 in FIG. 3 is representative of a plurality of AND gates which would be passing a scan item in parallel to the display controls.

The buffer register 68 is simply a register for storing eight bits of data plus a flag bit. Each stage of the register 68 operates in parallel with the other stages. The data from the memory is loaded into the register in parallel and is gated out of the register in parallel. The details of register 68 are not shown, as such a register is common in the art.

Likewise, the details of memory 56, with its memory controls, are not shown hereinafter as they do not form a part of the invention, and there are many memory and addressing controls and logic which may be used to perform the function of memory 56 and its controls. One exception is the scan address controls which perform some unique functions for the preferred embodiment of the invention as shown in FIG. 3. A block for the scan address controls 74 is shown at the bottom center of FIG. 3.

The scan-address controls function during the scancycle mode of operation of the memory 56 and assign sequential addresses to scan items as they are assembled in the scan storage portion of memory 56. Scanaddress controls are operative either in full-count mode or change-count mode. In either mode, a new scan is assembled in the scan-storage area of the memory. In addition, in change-count mode, the scan-address controls keep track of which scan item is the last scan item in a scan. In other words, the scan address controls monitor the end-of-scan condition and generate a setmove-scan signal when a complete scan has been built up in a scan-storage area of memory. The set-movescan signal is passed by the OR gate 76 to the memory controls to initiate the move-scan operation in the memory. The set-move-scan signal from the scan-address control 74 is generated during a change-count mode of operation. The identical signal during fullcount mode of operation is generated by the end-ofscan decode 78.

To determine whether the data expander is to operate in change-count or full-count mode, mode control 60 is provided. Mode control 60 is initiated by the character start signal from space decode 58. Initially, the mode control will generate a full-count mode signal. When an end-of-scan flag is detected during the full-count mode of operation, the mode control automatically generates a change-count mode signal. The remaining output signal from the mode control is the prime-cycle signal which is present only during the first bit of every full-count scan item. To generate these three signals, full-count mode, change-count mode, and prime cycle, the mode control responds to (reading from top to bottom on block 60 in FIG. 3) character start, a history of two ones, serial data, end-ofcha'racter, full-count-scan-item-but not-end-of-scan,

and set-move-scan (from end-of-scan decode 78). The detail implementation of mode control 60 is shown in FIG. 10 and will be described hereinafter.

To detect the end-of-scan flag during full-count mode operation, end-of-scan decode 78 monitors the serial data during prime cycle. The endof-scan decode is operative only during full-count mode of operation. If, during the prime cycle, (first bit of each full-count item), the serial data contains a one, the end-of-scan decode will indicate an end-of-scan condition over the output marked EOS from decode 78 in FIG. 3. In addition, the end-of-scan decode also indicates over another output line when a full-count item has ended, but there has been no end-of-scan flag. Finally, in the event the end-of-scan decode does detect an end-ofscan flag, it also generates a signal for a set-move-scan, which is passed by OR gate 76, and signals the memory controls to initiate the move-scan operation.

In change-count mode, the change-count decode 80 is active. The function of the change-count decode is to monitor the serial data during a change-count mode. From the data the change-count decode will indicate the amount of change to be applied to a full-count item in the previous scan to make up the present fu1l-count item. The change-count operation on the change-count items is done serial-by-bit. The first determination made by the change-count decode is whether a change in direction (or sign) is called for by the change-count item. If the change in direction is desired, the change count decode applies a signal to the exclusive OR 82. The function of exclusive OR 82 is to change the sign flag bit from the buffer register when the change count decode signals a change in direction. This flag bit indicates the last direction of change for that item. The sign flag bit out of exclusive OR 82 is passed to the memory input gating 62 and stored back in memory 56 during the write time of the memory cycle.

At the same time that the sign flag bit is being updated, the count in a scan item is being incremented or decremented by one by the increment/decrement circuit 70. Whether the circuit 7!) increments or decrements is controlled by the output of exclusive OR 82. With the full count being applied to the increment/decrement circuits via cable 638, the changecount decode 80 applies an advance signal which causes the increment/decrement circuit to add or subtract one from the full count depending upon the flag bit from exclusive OR 82. The updated count is then passed to the memory input gating 62 and loaded back into memory 56 during write time of the memory cycle.

At read time, if there is still a further change required in the count as indicated by the change-count code, the same count item will be again recirculated to the increment/decrement via buffer register 68 and the cable 63B. The increment/decrement circuit 70 again updates the full count. This procedure continues until all of the change-count zeros in the change-count code have been consumed and the full-count is completely updated by the change count. At this time, the changecount decode 80 generates a change-scan-address signal which is applied to the scan-address controls 74.

Scan address controls operate to select the next item for a change-count modification. At the last count item in the scan, scan-address controls will detect that it is an end-of-scan and generate a set-move-scan signal which is passed by OR gate 76 to cause the updated scan to be moved from the scan-storage area of memory to the print-storage area as previously described. The read out from the scan storage is not destructive. Therefore, the scan items will be available in scan storage for updating by change-count codes when the next scan item is built up.

The only remaining function in the data expander is end of character (EOC) decode. The purpose of EOC decode 84 is to detect the end of character code and indicate to the computer that new character information (starting with first and second bytes of a new character) may be sent to the input register 50. A byproduct of EOC decode is a signal telling the scan-address controls when the count item being assembled is the first item in the scan.

CLOCK SIGNAL GENERATION Referring now to FIG. 4, the clock signal generation circuits are shown. These clock signals were not shown in FIG. 3. However, in describing the detailed implementation of some of the blocks in FIG. 3, it is necessary to understand the timing and gating of the signals being used and generated by the blocks.

In FIG. 4, the source of the time pulses is a clock 91 which puts out four clock pulses during each cycle of operation. Clock-pulse outputs B1, B2, and B3 are shown in FIG. 3. B4 is not shown as that particular pulse is not used in the preferred embodiment of the invention. The clock pulses reoccur once each cycle in the order of their numerical identification, i.e., B1, B2, B3, B4, B1, B2, B3, B4, etc. In addition to the B1, B2, and B3 pulses, two gated pulses, OB]. and B3 are also generated. These pulses occur at the same time as BI and B3, but are gated so that they will not occur during either use-cycle or move-scan operations.

To generate the gated pulses OBI and 083, the usecycle request is inverted by inverter 92 while the movescan signal is inverted by inverter 93. These inverted signals are applied to AND gate 94. Therefore, AND gate 94 will have an output only when both the usecycle request and the move-scan signals are absent. The output from AND gate 94 is applied to the inverter 95. Thus, inverter 95 will have an output until one of the signals, use cycle or move scan, is present. The output from inverter enables AND gate 96 to pass the BI time pulse and create the OBI time pulse. Accordingly, the OBI time pulse will disappear when either the use-cycle request or the move scan signals occur.

The output from AND gate 94 is also applied as a DC level to the polarity hold circuit 97. At Bl time, if the AND gate 94 has an output, the polarity hold will be set. The output of the polarity hold then enables AND gate 98 to pass the B3 pulse at B3 time and create the DB3 pulse. If a use-cycle or move-scan signal is present, then the AND gate 94 will not have an up level output at B1 time, and the polarity hold circuit 97 will not be set to an up level. If the polarity hold is not set to an up level, then it will not have an output to enable AND gate 98. Thus, the gated 0B3 time pulse will not be generated when either a use-cycle request or a move-scan signal is present.

INPUT REGISTER The input register 50 of FIG. 3 is shown in detail in FIG. 5. The input register consists of a linear array of OR gates positioned in parallel and identified by the reference numeral 100, a linear array of polarity hold circuits positioned in parallel and responsive to the OR gates and identified by the reference numeral 102, and finally a second linear array of polarity hold circuits responsive to the first array of polarity hold circuits and identified by the reference numeral 104.

The data input bytes of eight bits are applied in parallel to the lines zero through seven at the left-hand side of FIG. 5. Each bit is passed by one of the OR gates 100 to one of the polarity-hold circuits 102. At 0B3 time, the polarity-hold circuit is set to the binary value of the signal applied to it by the OR gates 100. Thus, at 0B3 time, the input data is stored in the polarity-holds 102. The output of each polarity-hold, indicative of its binary state, is passed to the polarity-holds 104. At 081 time, these polarity holds are set to the value they receive from the polarity holds 102. Accordingly, at OBI time, the 8-bit byte stored in polarity holds 102 is shifted to polarity holds 104.

To serialize the parallel data, the output from the polarity holds TM is fedback to the OR circuits 100 where they are applied to next higher bit position of polarity holds 102. During each clock cycle of 0B1, 0B3 timing pulses the parallel data moves upward until it reaches the topmost polarity hold 1041A. Thus, after eight cycles of the clock pulses, the eight parallel bits will have been gated out serially from polarity hold 104A. When the last or eighth bit is in polarity hold IIMA, the computer applies the next eight bit byte to OR gates MN).

The cable I at the bottom of FIG. 5 is the cable which passes the eight-bit byte as parallel bits to AND gate 54 in FIG. 3. This byte of data is the left-edge space count and does move in parallel and need not be serialized. The second byte signal from the computer which controls the gating of AND gate 54 in FIG. 3, will occur during the first clock cycle of 0B3, OBI pulses.

The only remaining output lines from the input register are the one-bit and two-bit positions from polarity holds 1MB and W4C, respectively. These output bits are passed to the full-count size decode 52 in FIG. 3 during the first bytes signal after the 081 pulses has loaded the bits into polarity holds 1643 and 104C. During first byte, these bits contain the full-count size code.

SPACE DECODE In FIG. 6, the space decode is shown in detail. Its function is to decode the first bit, or zero bit, in the first byte of character data. The space decode receives serial data from the input register over line 110. During the time of occurrence of the zero bit, a first byte pulse from the computer will be present. The first byte pulse has a duration equal to one clock cycle running from B1 through B2 pulses. When this first byte pulse is present, AND

gates

112 and 114 are enabled. AND gate 112 will have an output if the first, or zero, bit is a l while AND gate 1 14 will have an output if the zero bit is a 0. AND gate 114 has an output because the zero in the zero-bit position is inverted to a conditioning, or up level, signal by inverter 116. If AND gate 112 has an output, it is indicative that the zero bit was a l, and that a left-edge space count is stored in the second byte. The output from AND gate 1 12 is used to set latch 118. The output of latch 118 is the left-edge space signal which conditions AND gate 54 in FIG. 3. The latch 118 is not reset until a prime-cycle pulse is received from the mode control. The mode control generates a prime cycle in response to a character-start signal. Therefore, if the latch 118 is set, by the zero bit in the first byte, it will remain set until after the character-start signal, i.e., until after the serial data begins to contain scan items.

The character-start signal is generated at the beginning of the first byte to contain scan items. This may be either the second byte if there is no left-edge space, or it may be the third byte if there is a left-edge space.

The character-start signal indicates the beginning of scan items. To generate the character-start signal, when there is left-edge space, the latch 118 enables AND gate 120. AND gate 120 will then pass a third byte signal pulse from the computer at the beginning of the third byte. This third byte pulse is passed by OR gate 122 as the character start signal.

To generate a character-start signal when there is no left-edge space, latch 124 and AND gate 126 are provided. If there is no left-edge space, the first, or zero, bit in the first byte will be a 0, and cause AND gate 114 to have an output. AND gate 114 will then set latch 124. Latch 124 remains set until after a prime-cycle signal is received to reset it. The prime-cycle signal is generated in mode control 60 (FIG. 3) as a result of the mode control receiving a character-start signal. Thus, the latch 124 will remain set until after the characterstart signal is generated. The output from latch 124 is used to enable AND gate 126. AND gate 126 will then pass the second byte pulse from the computer when the second byte is passed into input register 50 (FIG. 3). This second byte pulse passed by AND gate 126 is also passed by OR gate 122 and constitutes the characterstart signal when there is no left-edge space.

FULL-COUNT SIZE DECODE In FIG. 7, the details of the full-count size decode are shown. The full-count size decode is operative to store the l-bit and 2-bit out of the input register during the first byte. Thereafter, at character start, as signaled by prime cycle, the full-count-size decode logically determines the size of full-count items from the two-bit code, and passes the full-count size signal to the memory input gating 62 (FIG. 8).

To store the l-bit and 2-bit, polarity holds 128 and 130 are provided. The polarity hold circuits will be set to the polarity up or down of the one and two-bit re-.

gister positions by the first byte pulse. During first byte, these bits are the two-bit code associated with fullcount size.

To decode the two bits into a full-count size signal, a logic circuit is used consisting of AND

gates

132, 133, 134, and and

inverters

136 and 137. Each AND gate is enabled by different two-bit code. If the two bits are O0,"

inverters

136 and 137 will enable AND gate 132. If the code is 01, AND gate 134 is enabled by inverter 136 and polarity hold 130. If the code is 10, AND gate 133 isenabled by polarity hold 128 and inverter 137. Finally, if the code is l 1 AND gate 135 is enabled by polarity holds 128 and 130. The AND gates will not have an output pulse until the prime-cycle pulse is generated at character start by the mode control. When the prime-cycle pulse occurs, and AND gate which has been enabled by the two-bit code will have an output pulse. Thus, the full-count size is indicated by the output line from the full-count size decode which has a pulse during prime cycle.

MEMORY INPUT GATING In FIG. 8, the memory input gating 62 of FIG. 3 is shown in detail. Cable 140 carries the full-count size information from the full-count size decode 52 (FIG. 3). Cable 63A carries the eight bits from the buffer register 68 (FIG. 3) into the memory input gating. Cable 64 carries the incremented or decremented counts from increment/decrement circuit 70 (FIG. 3). The gating of information from the cables into the memory is controlled by the linear array of AND gates 142. With the exception of the AND gate at the flag-bit position at the top of FIG. 8, the logic for each bit position zero through seven consists of three AND gates whose outputs are collected by a single OR gate. In each case, the topmost AND gate is gated on by a move-scan signal from the memory controls. The center AND gate in the group of three is gated on by a change-count mode signal from the mode control 60 (FIG. 3). The bottom AND gate in the group of three is gated on during full count mode.

As previously described, the memory is cyclically alternated between a write time and a read time. During write time, if an AND gate in the array 142 of FIG. 8 is enabled, it will pass the binary bit it is receiving over one of the cables into the memory. That bit will be then written into a nine bit word in memory storage at an address specified by the memory controls or the scan-address control 74 (FIG. 3). During read time of the memory, the memory cell which is addressed will read all eight bits plus the sign flag bit (nine bits) out into the buffer register 68 (FIG. 3). The contents of the buffer register are then recirculated back to the memory input gating over cable 63A or cable 64 if they are to be incremented or decremented.

Examining first the full-count mode of operation for memory input gating, the conditioning signals for the appropriate AND gates are the full-count mode signal and the not prime-cycle signal. These are applied to AND gate 144. The not prime-cycle signal is, of course, derived from the prime-cycle signal by inverting the latter signal with inverter 146. In effect, during full count-mode, the bottom AND gate of each of the set of three for each bit position is enabled except during the prime cycle. Prime cycle corresponds to the first bit position in the serial flow of bits. This bit-position contains the end-of-scan flag bit, and there is no necessity of applying that flag bit to the memory. Accordingly, the AND gates are inhibited during end-of-scan bit or prime cycle. The serial data flow is applied to the memory input gating at AND gate 148 which is the fullcount mode AND gate in the bottom-bit position (or bit seven).

There is a significant function during prime-cycle full-count mode in the memory input gating. This is the gating into memory of the prime-cycle bit over cable 140. This prime-cycle bit, depending upon which line it comes in on over cable 140, indicates whether the fullcount size is five bits, six bits, seven bits, or eight bits. When the prime-cycle pulse arrives'over one of the lines in cable 140, it is immediately passed to one of the OR gates in the bottom four bit positions. As will be described hereinafter, this pulse which is passed by one of the OR gates to memory and written in the first address will eventually serve as the sign flag bit for the full-count scan item.

To assemble the full-count items during full-count mode, the serial data is applied to AND gate 148. As just described, during the first bit position, the sign flag bit from the full count size decode circuit is a 1 bit and is inserted at one of the bit positions, four, five, six or seven. Assuming that the full-count item is a five-bit item, the sign flag bit would be inserted at bit position four and stored in memory cell having 9-bit positions all containing zeros except the bit four position which would then contain a 1 for the sign flag bit. When the second bit in the full-count item arrives, it is passed by AND gate 148 to the OR gate 150, which is the OR gate for the bit seven position. In the meantime, the flag bit during read time of the memory has been read out to the buffer register 68 (FIG. 3) and recirculated back over cable 63A and applied to AND gate 152. AND gate 152 is enabled in the same manner as AND gate 148 so that the flag bit has been moved up to hit position three OR gate as the second bit in the full-count item enters OR gate 150 at the seven bit position.

The nine bits constituting the sign flag bit and bits zero through seven are then again loaded into the same address at memory during write time and read out again during read time into the bufier register. The next time they are recirculated back to the memory input gating, they will have moved up another position as the third bit of the full-count item enters AND gate 148 and OR gate 150. Thus, as the third bit enters, the sign flag bit is at bit-position two and the second bit is at bitposition six while the third bit is at bit-position seven. The assembly of the full-count item continues in this manner with recirculation back from the buffer register and moving up the bit positions in the memory input gating until the sign flag bit reaches the flag bit OR gate 154. At this time, the OR gates in the memory input gating will contain a sign flag bit l at the flag bit position and the five bits in the five-bit count for the fullcount item will be at bit positions three, four, five, six and seven.

To change the address in scan storage of the memory, after a full-count item has been assembled, the buffer register position zero is monitored by the end-of-scan decode 78 (FIG. 3). The end-of-scan decode will then function to generate a full-count item end, but not end-of-scan signal. This signal is passed to the change-count decode 80 (FIG. 3), which in turn generates a change-scan-address signal. The changescan-address signal is passed to the scan-address controls 74 (FIG. 3) to change the address in the scan storage section of memory in preparation for assembling the next full-count item. The address is not, however, changed until after the contents of the buffer register are recirculated one more time back to the memory input gating and into the old scan storage address. This one more recirculation back to the memory input gating is required to move the flag bit into the flag-bit position and complete assembly of the fullcount item at that address. The timing of the read and write operations in the memory corresponds approximately to the B2 and B4 clock-time pulses: i.e., read occurs at B2, and write occurs at B4. In this way, the complete full-count item is read into the old address of scan storage before the address is changed in preparation for assembling the next full-count item.

The middle AND gate in each group of three AND gates for each bit position is used during the changecount mode. When a change-count mode signal is present, the middle AND gate is enabled to pass an 8- bit byte from cable 64 into the memory. This 8-bit byte will be the incremented or decremented count from increment/decrement circuit 70. Briefly, in change-count mode operation, the full-count to be incremented or decremented is read into bufier register at read time and then passed back to the increment/decrement circuit via cable 638 (FIG. 3). The full-count is incremented or decremented and then passed by cable 64 back to the memory input gating where at write time of the memory it is again stored in the same place in scan storage. This will continue until a full-count item has been updated by a change count. When the updating is complete, the change-count decode will generate a change-scan-address signal which is passed to the scanaddress controls 74. The scan-address controls then change the address being operated on in scan storage and effectively move the change-count mode of operation to the next count item to be updated.

After an entire scan has been stored in scan storage, the scan address controls or the end-of-scan decode will send a set-move-scan signal to the memory controls. The memory controls the then initiate a movescan operation and pass a move-scan conditioning signal to the memory input gating. The move-scan signal enables the top AND gate in each of the group of three AND gates for each bit position. During move scan, the memory controls operate to read out each scan item from the scan storage into the bufier register. The scan items are then recirculated over cable 63A to the memory input gating where they are passed by the topmost AND gates in each bit position back into memory and stored in print storage. The memory controls control the addressing to read out the items from scan storage into the buffer register, and also the addressing to store these items into print storage during write time of the memory. Eventually, when all the scan items in a scan have been moved, the memory controls will generate an end-of-move scan signal, and the move-scan conditioning signal applied to memory input gating disappears.

SCAN ADDRESS CONTROLS Address controls for memory are a welLknown, developed technology, and, by and large, have not been described for purposes of this invention; however, the scan address controls for scan storage perform some functions, such as assembly of the full-count items and detecting end-of-scan during change-count mode which are particularly useful in this invention. Therefore, a rudimentary description of the scan-address controls to perform these functions is given and is illustrated in FIG. 9.

The addresses used by the memory controls for scan storage are generated in the address register 170 in FIG. 9. Initially, register 170 starts, or is reset to zero, as follows: During the first item of each scan, the notfirst-item signal is down. This signal comes from the end-of-character decode 84 (FIG. 3). The purpose of the not-first-item signal is to inhibit AND gate 172 during the first scan item in each scan. In effect, with AND gate 172 inhibited, it has no signals to pass to register 170, and, thus, at B1 clock-pulse time, the register 170 is set to all zeros. All zeros is the first address for the first scan, or count item in scan storage. This address remains the same until the first count item has been assembled and a change-scan address signal is received by AND gate 174. The change-scan address signal is also received by the end of character decode 84 (FIG. 3) and is used to turn on the not-first-item signal. With the not-first-item signal turned on, AND gate 172 is now enabled. The other condition at AND gate 172 is scan cycle, which merely means that if the memory is operating in a move-scan or use-cycle mode, AND gate 172 is inhibited. However, when operating in an assembly of full-count items or updating of change-count items, the scan cycle will be present at AND gate 172.

To change the address in register 170, the contents of the register are fed in parallel over cable 176 to incrementer 178. Incrementer 178 adds one to the value received from register I70 and passes it to register 180. Register 180 is loaded at B3 time if the change-scan-address signal is present. The change-scan-address signal is present at the end of each assembly of a count item or update of a count item. Register 180 will then contain an address which is one higher in position than the address stored in 170. The incremented address is passed to address register 170 by AND gate 172. When a B1 clock pulse is applied to register 170, it is updated with the new address. The memory controls then direct the next count item to this new address. Thus, the count items are stored sequentially in scan storage of memory 56 (FIG. 3).

After a complete scan has been stored in scan storage, a set-move scan will be generated either by the end'of-scan decode 78 (FIG. 3) or the AND gate 182 in the scan address controls. This set-move scan signal is applied to the end-of-character decode 84 (FIG. 3) and the end-of-character decode will cause the notfirst-item signal to drop. When this signal drops, then AND gate I72 is again inhibited, and at the next B1 clock-pulse time, register is reset to zero. In this way, at the end of each compilation of scan, the register 170 is reset so hat as the next scan is built up in scan storage, the memory controls will address the same sequence of addresses as before.

An additional function performed by the scan-ad dress controls is the detection of end-of-scan during change-count mode. The end-of-scan flag bit only exists in the full-count items. During the full-count mode, the end-of-scan condition is detected by the end-ofscan decode 78 (FIG. 3). To detect the end-of-scan in change-count mode, the scan address controls compare the current address being used for scan storage with the address of the last count item in a scan. The address of the last count item of the scan is stored in register 184. Register 184 is set during full count mode operation by the end-of-scan signal from the end-of-scan decode 78 (FIG. 3). When this end-of-scan signal occurs, register 184 will store the address presently being also stored in register 170; i.e., the address of the last count item in a scan. Thereafter, in change-count mode, as the address register 170 stores new addresses, its contents are compared with the contents of register 184 by the compareequal circuit 186. When a compare-equal condition exists, the circuit 186 has an output signaL which enables AND gate 182. AND gate 182 must also be enabled by the change count mode signal. The change count mode condition prevents AND age 182 from generating a setmove-scan signal during full count mode when register 184 is being loaded. At B2 time, AND gate 182 will then generate a set-move scan signal. In this way, the end of scans can be detected in the change-count mode of operation.

MODE CONTROL As previously discussed, the function of the mode control is to generate the full-count mode signal, the change-count mode signal, and the prime-cycle signal. The details of mode control are shown in FIG. 10.

With regard to the prime-cycle signal, this signal represents the first bit in each full count item. It is generated by character start, or during full-count mode, or also during change-count mode. Initially, prime-cycle signal is triggered by the character-start signal from the space decode 58 (FIG. 6). The character start signal is passed by OR gate 190 and applied to polarity hold 192. At 083 time, the polarity hold is set to the level of the output from the OR gate 190. If the character start signal is present, the polarity hold 192 will be set to an up level. This up level is passed to polarity hold 194 so that at gated clock pulse OBI time, polarity hold 194 is set to an up level and produces the prime-cycle signal. The prime-cycle signal is a pulse since at the next gated OBI pulse time, the polarity hold 192 will be down, and, thus, polarity hold 194 will be set to a down level. Polarity hold H2 is set to a down level at 0133 pulse time because the character start is also a pulse signal and will no longer be present on the OR gate 190. In effect, the prime cycle is a pulse which is on during the first bit time of a full-count item, i.e., during the end-of-scan flag bit which is transmitted to the end-of-scan decode.

OR gate 190 is also collecting input pulses from two other sources so as to cause generation of a prime cycle. One instance is the full-count-item-end-but-notend-of-scan pulse, from the end-of-scan decode. This pulse occurs at the end of each assembly of a full-count item in scan storage when that item did not contain an end-of-scan flag. The other input to OR gate 190 is from AND gate 196. AND gate 196 is enabled by a two-l s history signal from the change-count decode 80 (FIG. 3). This signal exists every time the change-count decode detects two sequential ones in the serial data string. If the next bit in the serial data string is also a one, making a sequential series of three ones, AND gate 196 will have an output. Thus, a signal from AND gate 196 means three sequential ones have been received. A review of the data expansion code shows that this is the code for switching from change-count mode to full-count mode. Accordingly, there is a need for generation of a prime cycle and AND gate 196 generates a pulse collected by the OR gate 190 for polarity hold 192 so that a prime cycle pulse will be generated.

The remaining functions in the mode control are the generation of the full-count mode and the change.- count mode signals. There signals are generated by the latch 198. If the latch is set, its l or set output will be up indicating full-count mode. If the latch is reset, its output will be up indicating change-count mode. As previously pointed out, latch 198 is set by AND gate 200 in response to a signal from polarity hold 192 and at the time of a gated clock pulse 031. Thus, each time a prime cycle is being generated, latch 198 is set; so that it indicates a full-count mode.

Latch 198 is reset by one of two conditions so that it will indicate a change-count mode. Initially, the latch is reset by an initial reset pulse which will come from the computer. Normally, however, the latch is reset by the fact that a set-move scan signal has enabled AND gate 202. With AND gate 202 enabled, the next Bl clock pulse will be passed by AND gate 202 and OR gate 201 to reset latch 198 into change-count mode. In effect, this means that at the end of each scan, the mode con trol automatically switches to change-count mode.

The remaining hardware which has not been described in the mode control relates to inhibiting the change-count mode signal from reaching other apparatus in the data expander between the time of initial reset and character start. Initial reset signal is passed by OR gate 204 to reset latch 206. When latch 206 is reset, AND gate 208 is inhibited. the change-count mode signal out of latch 198 cannot pass to the other hardware in the data expander.

When the character-start signal comes up, then latch 206 is set and AND gate 208 is enabled to pass the change-count mode signal. When the end-of-character condition is detected by end-of-character decode 84 (FIG. 3), the end-of-character signal is passed by OR gate 204 and resets latch 206. This again inhibits the passage of the change-count mode signal by AND gate 208. The time period between the initial reset and character start, permits the photocornposing system to perform other functions and prevents the change-count decode 80 (FIG. 3) from being operative between the time of end-of-character and character start, or initial reset and character start. Note that even though the character start signal will set latch 206 and thereby enable AND gate 208, the change-count mode signal will rapidly disappear as the character-start signal also is responsible for setting latch 198 at 0131 clock-pulse time. Thus, the data expander will stait in full-count mode at the start of character data.

END OF SCAN (EOS) DECODE The detail structure of the EOS decode is shown in FIG. 11. The end-of-scan signal is a pulse signal generated by AND gate 210. The AND gate is enabled by the prime-cycle signal from the mode control and by the gated 0B3 clock pulse. If the data bit during prime cycle is a l the AND gate 210 will have an output. The data bit which occurs during prime cycle is the end-of-scan flag bit. Accordingly, an output from AND gate 210 indicates end of scan in full-count mode operation. The end-of-scan signal is used by the scanaddress controls and the end-of-character (EOC) decode. In addition, it is passed to latch 212 inside the end-of-scan decode.

The end-of-scan signal sets latch 212, and the set side of latch 212 then enables AND gate 214. AND gate 214 must also be enabled by buffer register position zero containing a binary one. The binary one at buffer register position zero means that during asembly, the sign flag bit has reached the position zero (see previou discussion on memory input gating).

Therefore, when the latch 212 has been set by an end-of-scan signal and when the buffer register position zero contains the sign flag bit, then the gated 0B3 clock pulse will be passed by AND gate 214 to signal a set-move scan. In effect, this signal indicates that the last full-count item in a scan has been assembled in scan storage, and now, the entire scan may be moved to print storage.

The latch 212 which effectively stores the fact that the count item contained end of scan will be reset as soon as the set-move scan signal causes the mode control to switch to change-count mode. When the changecount mode signal comes on, the full-count mode signal disappears and inverter 216 resets latch 212.

The remaining function performed by the end-ofscan decode is the generation of a full-count-item-end signal when there is no end of scan. This signal indicates that a full-count scan item has been assembled in scan storage, but the item is not the last item in a scan. The signal is generated by AND gate 218. AND gate 218 is enabled by the reset side of latch 212 and by the full-count mode signal from the mode control. Accordingly, when the sign flag bit reaches the buffer register position zero during assembly of the full-count item, a binary one will appear in buffer register position zero and be passed by AND gate 218 to generate the full-count-item-end-but-not-end-of-scan signal.

CHANGE-COUNT DECODE The purpose of the change-count decode, as described earlier, is to decode the change counts received from the computer serially, bit by bit, to indicate how a scan item must be updated, both as to direction and to magnitude. The change-count decode is activated by the change-count mode signal enabling AND gate 220. AND gate 220 is also enabled by the output signal of inverter 222. This signal indicates that the change-count decode in FIG. 12 has no previous change-count history in it. With AND gate 220 enabled, the first binary one on the serial data line that arrives, will be passed by the AND gate, and at 083 pulse time, polarity hold 224 will be set to an up level. Immediately following thereafter at OBI pulse time, polarity hold 226 is set to an up level. The output from polarity hold 226 indicates one binary one has been received during change-count mode. This signal enables AND gate 228 to look for a second binary one and also is passed by OR gate 230 to enable AND gate 232 to look for a binary zero on the data line. AND gate 232 is looking for zeros on the data line since it receives its input of serial data through inverter 234. Also, this output from OR gate 230 is inverted by inverter 222 and inhibits AND gate 220.

When the next serial data bit arrives, if it is a zero, it will be indicative of a magnitude of one increment to be made on the previous count item which is now being updated. This binary zero is passed by AND gate 232,

and at B3 time, causes polarity hold 235 to be set to an up level. Consequently, at 031 pulse time, polarity hold 236 is set to an up level. The fact that polarity hold 236 is set, is indicative that a change-bit or a zero-bit in a change code has been received.

To signal the increment or advance to the increment/decrement circuit 70 in FIG. 3, the zero bit as indicated out of the inverter 234 is passed directly to AND gate 238. AND gate 238 will be enabled since polarity hold 226 was set by the preceding binary one. Therefore, AND gate 238 will pass a pulse signal which will cause the increment/decrement circuit to increase or decrease the count item by a single count. Whether it is an increase or decrease depends upon the signal received from the exclusive OR 82 (FIG. 3). This advancing of the increment circuit occurs immediately upon the receipt of the binary zero. At time 0B1 when the binary zero effectively causes polarity hold 236 to be set, polarity hold 226 is being reset effectively because polarity 224 has no up level output. With polarity hold 236 set to an up level, it will continue to enable AND gate 238 via OR gate 230 in the event the next serial bit received is also a zero. Thus, the zero bit next received will be treated just exactly as the first zero bit received causing an increment or advance action out of AND gate 238 and causing the polarity holds 235 and 236 to remain set at up levels. Eventually, the change-count code is completed because a binary one is received over the serial data input line. When this binary one arrives, it is passed directly to AND gate 240 which has been enabled by the previous zero bit having caused polarity hold 236 to be set. AND gate 240 then has output which is collected by OR gate 242 and used to signal a change-scan address to the scan-address controls. Thereupon, the scan-address controls will cause the memory to address the next count item, and the update by change-count code of that count item can begin.

Returning to the second bit in a change-count code, the code indicates that if the second bit is a binary one, the change-count decode should indicate a change in direction, from the change that occurred in the same count item in the previous scan. The first binary one in the change-count code caused the polarity hold 226 to be set to an up level as previously described. The output from 226 polarity hold enables AND gate 228.

Thus, when the second bit is a binary one, AND gate 228 will have an output, and at 0B3 pulse time, polarity hold 244 will be set to an up level. Then at OBI pulse time, polarity hold 246 is set to an up level. An output from polarity hold 246 is indicative of a history of two binary ones just received from the serial data line. This history of two ones is passed to AND gate 248 which it enables. AND gate 248 will then pass the first zero bit in the change-count code and that signal will be indicative of a change in direction being required during the update of the current-count item. the change in direction signal, as previously described, is applied to exclusive OR 82 in FIG. 3 and, effectively, causes the sign flag bit fed back from buffer register 68 (FIG. 3), to change state. The changed flag bit is then read back into the memory via the input gating and also changes the state of the increment/decrement circuit from increase to decrease or decrease to increase.

The output of polarity hold 246 also is passed as a history of two ones to the mode control 60 (FIG. 3). The mode control 60 uses this signal as previously described to detect the command for reversion from change-count mode back to full-count mode. In addition, the output of polarity hold 246 holds AND gate 238 enabled for the first zero bit in the change-count code. Of course, thereafter, the zero bits will be causing polarity hold 236 to be set so that AND gate 238 will be held open for the succession of zero bits in the changecount code that may be received.

One other possibility in the change-count mode of operation is that the first change-count code bit may be a zero indicating that that count item requires no change. If this occurs, AND gate 250 will have an output. AND gate 250 is enabled by the change-count mode signal and by the no history signal out of inverter 222. If a zero bit occurs as the first change-count code bit, inverter 234 has an output which is passed by AND gate 250. OR gate 242 collects the output from AND gate 250 and generates the change-scan-address signal. The change-scan-address signal is passed to the scanaddress controls which then signal the memory controls to proceed to the next count item for updating.

Finally, OR gate 242 is the change-count decode serves to collect one other signal which may cause a change-scan address signal to be generated. This signal is the full-count item end, but not end of scan, which is received from the end-of-scan decode 78 (FIG. 3) as previously described.

END OF CHARACTER (EOC) DECODE The end-of-character decode 84 in FIG. 3 is shown in detail in HG. 13. The purpose of the end-of-character decode is to detect the end-of-character condition and indicate to the computer that new character information (starting with first and second bytes of a new character) may be sent to the input register 50 (FIG. 3). A by-product of the end-of-character decode is a signal telling the scan-address controls when the count item being assembled is the first count item in the scan.

The first item latch is latch 260, which is set by endof-move scan or initial reset. 'Ihe end-of-move scan signal, which corresponds to a signal at the start of the next scan, is normally used to set the first-item latch 260. With the first-item latch set, AND gate 262 is enabled. AND gate 262 remains enabled, so long as latch

Claims

1. A method of transmitting and registering successive values of a set of variable quantities comprising transmitting initial values of said quantities in binary digits in either of two forms in a full count mode operation in which the full counts of the quantities in the sets are represented in binary digits, including transmitting signals denoting binary digits in groups into each register of a set of registers corresponding to said set of quantities, registering successive values of said quantities by transmitting signals denoting binary digits serially in a change count mode operation in which the binary digits of one form represent the differences between successive values of the quantities and the binary digits of the other form represent control operations, including incrementing the value in each register by successive signals denoting binary digits of one fOrm to change the value by one unit for each binary digit of said one form, and controlling the incrementing in each register in either positive or negative direction by signals denoting the binary digits of the other form, the binary digits of the one form changing the value in each register by a number of units equal to the number of successive binary digits of the one form under control of said digits of the other form, each binary digit of said one form retaining the previous value in the register in absence of a signal denoting a binary digit of the other form.

2. A method as claimed in claim 1, including shifting to full count mode operation following change count mode operation under control of signals of said digits of the other form.

3. A system for registering digitally the values of a set of variable quantities to be represented successively and which may take on new values between representations of said set of quantities, comprising means to place the value of each variable quantity of the set in a register of a first set corresponding to said set of variable quantities where it is represented by digits having two forms as binary bits, means to transfer the values of the quantities registered in said first set of registers to a second set of registers for control of exhibition apparatus while retaining said values of said quantities in said first set of registers, said system having means to control said registers of said first set to register successive value of said quantities in said registers, and including means transmitting signals denoting binary digits serially in a change count mode operation in which the binary digits of one form represent the difference between successive values of the quantities and the binary digits of the other form represent control operations, means incrementing the value in each register by successive signals denoting binary digits of one form to change the value by one unit for each binary digit of said one form and means controlling the incrementing in each register in either positive or negative direction by signals denoting binary digits of the other form, so that said means incrementing the value in each register changes the value by a number of units equal to the number of successive binary digits of the one form under control of said binary digits of the other form, said means transmitting signals also including means actuated by a binary digit of one form to retain a previous value in a register in the absence of a signal denoting a binary digit of the other form.

4. A system for representing an image on a surface which has two distinguishable states, one of which forms said image, said image being coded in the form of digits representing linear arrays of elemental areas of said surface, each array consisting of segments of elemental areas in one of the two distinguishable states, the count of the areas of each segment being in binary digits, said system comprising a set of registers for controlling the representation of the segments of the linear arrays of an image, a source of digitized codes for an image, which are transmitted successively from said source, the counts of the segments of the first linear array transmitted being full counts of the total numbers of areas in the segments in binary digits, the segments of successive arrays transmitted being in change counts of binary digits representing the differences of the full counts from the full counts of segments in preceding arrays transmitted, means to transfer the full counts of the segments of the first array transmitted to the registers of said set, means to change the digits in said registers by the change counts of the segments of each successive array, including means transmitting signals denoting binary digits serially in a change count mode operation in which the binary digits of one form represent the difference between successive values of the quantities and the binary digits of the other form represent control operations, means incrementing the value In each register by successive signals denoting binary digits of one form to change the value by one unit for each binary digit of said one form and means controlling the incrementing in each register in either positive or negative direction by signals denoting binary digits of the other form so that means incrementing the value in each register changes the value by a number of units equal to the number of successive binary digits of the one form under control of said binary digits of the other form, said means transmitting signals also including means actuated by a binary digit of one form to retain a previous value in a register in the absence of a signal denoting a binary digit of the other form.