DE2053341A1 - Process for the compression and decompression of digitally coded data for graphic characters - Google Patents

Description

IBM Germany international office machines GtielUchaft mbH Applicant: Official file number: Applicant's file number:

Boeblingen, October 26, 1970 blu-fr-sku

International Business Machines Corporation, Armorik, N.Y. 10504 New registration Docket BO 968 017

Process for the compression and decompression of digitally coded data for graphic characters. ..

The invention relates to a method for the compression and decompression of digitally coded data for graphic characters, which be formed by delimiting black and white sub-areas within a coordinate network and an arrangement for Implementation of the procedure.

Typographic information is using digital codes can be represented for characters. The coded information can be obtained from a distant place, e.g. from a computer be fed to a light setting device, in which, for example, with the help of a cathode ray tube, the display of characters a movie is controlled. By using a code, entire character fonts can be saved and later used Control of a light setting device or similar can be used.

209820/0796

The character detection should be based on the following prerequisite: The character is created by delimiting black and white partial areas shown within a coordinate network. With column-by-column scanning, the number of identical (black or white) basic coordinate network elements of a sub-area are recorded and stored as full count values. The totality of all Complete counts are then used to control and reproduce the character by means of a light setting device.

However, this has a disadvantageous effect for such a full count value code the high storage space requirements.

It is therefore an object of the invention to provide a method for compressing and decompressing such a full count code and a To specify the arrangement for carrying out the procedure.

According to the invention, this object is achieved in that the number of identical basic elements of the same type of coordinate network, which result in a partial area, is recorded as a full count value and the full count values are then compressed in such a way that, by comparing the full count values, two columns in each case - Or line by line of similar sub-areas adjacent to each other, only the difference of which is registered as the difference count and that with a decreasing change in the number of scanning items from column to column or line to line, the last Abtaetposen is registered as a full count and üa »at

Do <*. T BO «8 0X7

increasing change in the number of sampling posts from column to column or row to row the last sampling post, which corresponds to that in the adjacent column or row, and all subsequent sample items in a column or row as full counts are registered and that when the compressed data is decompressed, the full count values, unless they appear explicitly, by signed cumulative addition of difference counts corresponding partial areas adjacent to each other in columns or rows can be determined to form an original full count value.

An advantageous further embodiment of this method is characterized in that with column-by-column scanning for Registration of the compressed data using a binary code for byte-oriented storage with the following characteristics will:

a) A binary "1" in the first bit of the first byte indicates that it is not retained Columns within the coordinate network in front of the beginning of the character and draws the indication of the number of those that are not binding Columns in dual-encrypted form in the second byte. A binary "O" in the first bit of the first byte indicates that there are no free columns within the coordinate network before the start of the character.

b) The second and third bits of the first byte contain an encrypted assignment for the possible bit length Full counts. It means:

00 5 bits + 1 bit (IO bit) to identify the end

a column-by-column scan

01 6 bits + 1 bit (EA bit) to identify the end

a column-by-column scan

Docfcet BO 968 O ₁₇

I I

10 7 bits + 1 bit (EA bit) to identify the end

a column-by-column scan

11 8 bits + 1 bit (IO bit) to identify the end

a column-by-column scan.

A binary "1", in contrast to a binary "O" the end of a column-by-column scan in the EA bit. fc c) After a binary "1" in the EA bit, the first item for the following column-by-column sampling as a differential count indicated, whereby the size of the difference count is characterized by the number of binary zeros, which is indicated by two binary "l" s are included.

Give two binary "l" s at the beginning of a difference count indicates a change in sign compared to the previous corresponding sample post. A binary "0" indicates that it is the same difference count as the corresponding previous one.

d) Three binary "l" s indicate the transition from differential counting operation to full counting operation.

w The order to carry out this procedure provides for Partial Heise that a decompression of the code information the compressed data byte by byte with input register

Docket BO 968 017 209820/0796

"" 5 -

one series output, one parallel output and one with a decryption circuit for the bit-wise length of the full count values connected output that a cyclically working memory for Recording of the full count values and those decompressed to form total count values Difference counts with a downstream buffer register that for data input into the memory a with a full or. Differential counting mode determining operating mode control connected first gate circuit that a circuit for cumulative Determination of the full count values from the difference count values that a second gate circuit through which the parallel output of the input register for the columns corresponding to the free columns within the coordinate network before the start of the character Conditions can be connected to the memory that address control circuits are provided for addressing the memory locations and that the series output of the input register with the gate circuit is connected, which is adjustable via the decryption circuit for the full count length.

Docket bo 968 017 209820/0796

An embodiment of the invention is shown in the drawings and is described in more detail below. Show it:

Fig.l is a schematic representation of a light setting system;

2 shows the representation of a character within a Coordinate network;

3 shows a schematic representation of the main functional units the data expansion system for registering the complete data for the control of the light setting device;

4 shows a schematic representation of the timer circuit, which supplies control pulses for the data expansion circuit;

5 shows a schematic representation of an input register, which receives the character data from the memory of the computer;

6 shows the block diagram of a decryption circuit for empty columns to the left of the character;

7 shows the block diagram of a full-count value decryption circuit for the number of digits of a sample;

Fig. 8 is a block diagram of a memory input gate circuit; which forward complete data to the storage registers and output registers controls;

Docket BO 968 017 20 982 0/0796

Figure 9 is a schematic diagram of the scan address control circuits and registers for controlling the address of the storage registers;

10 shows the block diagram of the operating mode control circuit, with which the expansion system is set to either full count mode or differential count mode is brought?

Fig. 11 is a block diagram of an end-of-scan decryption circuit;

Fig. 12 is a block diagram of a differential count decoding circuit;

13 shows the block diagram of a character termination circuit.

Let us now go into Fig. 1, where the relationship between the data expansion system and the light setting system is shown schematically. The computer 10 delivers Display data in coded form to the data expansion system 12. The editing of the text and the choice of the The typesetting used takes place in the computer 10. The text that is finally brought to format is compressed in a Code passed on to the data expansion system. The data expansion system 12 then decrypts the Data and provides the control signals to the display controllers 13. The display controllers provide Operating signals that enable the cathode ray tube 14 to read the writing on light-sensitive "Print" film 16.

How the cathode ray tube works in relation to the film is detailed in the copending application Serial No. 682 845, filed November 14, 1967, loading

Docket BO 968

wrote; the title is: "Lichtsetzanlage with back and forth lens "and the inventor is J. L. Overacker. The cathode ray tube 14 shows the result of a vertical Scan on, and the lens 18 focuses this scan result on the film 16. If the result the next adjacent scan is to be printed, this will appear on the screen of the cathode ray tube at the same point, and the lens is indexed horizontally, making the scan line on the film horizontal is moved. Accordingly, a series of vertical scans of the cathode ray tube is applied to the film a symbol is shown, and a slight horizontal adjustment of the lens takes place between two scans 18th

A control unit for the motor of the reciprocating lens which sets the lens 18 is in FIG simultaneously pending, equally cited patent application, the title of which is "Lichtsetzsystem", for which application was made on October 28, 1969 and with which the inventor V.C. Martin is.

In Fig.2, the lowercase letter "e" is an example of a Characters shown, which s is broken down into small cells. For easier understanding of the function of the invention the samples for the example of the letter "e" have been numbered along the letter below, and the vertical ones Bits of a sample have been numbered along the left side of "e". A bit is here as a cell under a Sampling defined. The "e" looks like it is shown in Fig.2 is very rough and is of poor quality for printing. But if you have a lot more bits per sample and working with many more samples per inch, you can get an extremely good print quality of the "e", without noticeable discontinuity on the outer edge.

Docket bo 968 0172 0 9820/0796

With the help of the coordinate network, which is the character "e" as shown in Fig.2, it is possible to specify a data code for the "e" by adding each scan is divided into a series of alternating black and white sample posts. The length of a sample becomes measured over the number of bits (cells) of the sample item. The scan begins at some vertical reference point under the sign. With regard to the example in Figure 2, assume that the vertical reference point for each sample is three bits below the lowest part of the character. The upper scanning end for a character is through the given last black sample post in a sample.

At scan 4, the first scan post is white and 13 bits long. The second sample post is black and 7 bits long. Since the vertical reference point is below the sign, the first sample post will always be white for each sample. The samples then alternately turn black and be white. The following table can be used as a code for the scanning posts of the character "e" as shown in FIG is to be set up. In the vertical direction, bind the alternating white and black sample posts on the table specified. The table shows the number of the scan in the horizontal direction. The scans 1, 2 and 3 and the scan 30 are not found in Table I, since these scans, as can be seen in FIG no parts of the sign can be detected.

Docket BO 968

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Docket BO 968 ? Ö ^ 820/0796

As stated earlier, it is desirable to use the in To condense the code shown in Table I into a code which only reflects the differences between scans. Similarly, a second table can be made from the first by comparing with for each scan the previous scan (usually the scan immediately to the left, however encoding can be from either direction take place here) and by recording the difference per sampling point. Another rule to which one must stick to the compression of the data in Table I is that if the number of sampling posts is at transition from one sample to the next changes, at some of the sample items changed from differential count to full count must become. A full count is equal to the number of bits in a sample item, while a differential count equal to the difference in the number of bits between the sample post in the present sample and the same sample post at the previous scan. When the number of sampling posts is less than the number in a previous scan, the last scan item in a scan must be Full count value can be coded. As the number of scanning posts increases, the scanning post which is the last scanning post must be corresponds to the previous scan, and all remaining scan items are encoded as full counts. Whenever a scanning post changes significantly, this scanning post and all remaining scanning posts must be encoded at the sampling as a full count. With the help of these simple rules, Table II below from Table I.

Docket bo 968 017 ₂ 09820/0796

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Docket BO 968 017 209820/0796

The relationship between Table II and Table I will now be described. Sample 4 is the first sample, which leads through the character and accordingly the sample items must be full count items. Sample 5 is the second scan, which passes through the character, and the number of scan posts is the same as in scan 4. Therefore Sample 5 can be specified by differential counts based on sample 4. The samples are accordingly 6 and 7 by difference counts related to the size of the same sample item in the previous sample specified. In the case of scan 7, for example, it is clear from Table I that the first item in size of 8 in the Scan 6 to 7 decreased at scan 7. Accordingly, the first item of sample 7 is reported as minus 1. Similarly, the second item of scan 7 increased from 16 at scan 6 to 18 at scan 7. (See Table I). Therefore, in Table II, the second item of scan 7 is shown as +2.

If one compares Table I and Table II with Fig.2, so it can be seen that the transition from scan 7 to scan 8 changes the number of scan posts. Therefore must, what the coding of the last three sample posts of sample

8, full count values can be used for coding. Correspondingly, the number of 9 also has the number of scanning Sample posts increased compared to sample 8 and therefore the last three posts of sample 9 must again be encoded as full count items.

In the sample 10, the number of sample posts is the same as in the sample 9, and it becomes with the difference count coded. The first sample post is on the two samples

9 and 10 5 bits long, and the differential count for that sample post is "0" at sample 10. When you

Docket BO 968 017 _{2O982O / om}

Comparing samples 9 and 10 in Table I, one can determine the difference code or difference count code that one for scan 10 in Table II. Accordingly, samples 11 through 24 all become the differential count encoded, since the number of scan posts is the same for all these scans. An interesting case starts with scanning 15, and if one compares samples 14 and 15 in Table I, it can be seen that these samples are identical. Therefore, in the case of scan 15, Table II contains all "zero values" for the scan posts.

The next decrease to full count items occurs when scanning 25. When scanning 25, according to FIG. 2, the number of points of contact between white and black segments of the falls Character from 6 to 4. The last count value at sample 25 is thus coded with the full count value. Samples 26-28 are encoded with differential count value, since they also include four sample posts like sample 25. Eventually the Scan 29, which is the last scan to capture the character, encoded with a full count, starting with the first count, since the change compared to sampling is 28 +6. This change would have had a difference count can be encoded, but this is not done because the change is relatively large.

The code with which the computer sends compressed data to the data expansion system is subject to a group of Rules. The code is binary and in this case comprises 8 bits per byte. When transferring data from the computer to the expansion system one byte is transmitted at a time. As will be seen later, the data expansion system includes one Serializer so that the data expansion is effectively one bit at a time, just like the data from the serializer come in here.

Docket BO 968 017 ₂ 09820/0796

In further treatment of the code group it should be mentioned that the first bit or bit zero in the first byte indicates whether it was before the beginning of the Character at the left edge is free space or not. An "O" means no free space and a "1" means free space. If there is free space on the left edge, the number of samples in the left free space will also be given, namely by the count value that is received with the second byte.

Bits one and two of the first byte represent a double binary Represents the code with which the four possible count values for full count items are indicated. The code is as follows:

Bit 1 Bit 2 VoI1ζ counter value 0 0 5 bits + EA bit 0 1 6 bits + EA bit 1 0 7 bits + EA bit 1 1 8 bits + EA bit '

The EA bit is an end-of-scan flag for a full count sample item. If the EA bit contains a "1", the relevant full count item is the last sample item in a sample. Accordingly, if the counts are so large that seven bits and an EA bit are required to indicate a sample item, bits 1 and 2 will contain "1" and "0", respectively.

Bits three through seven of the first byte are used in this invention not used. You can use them for test bits or others Use data processing functions.

The data expansion system works after the first byte or the second byte on a serial bit basis. Whether this serial processing after the first byte or after the second byte depends on whether bit zero in the first byte indicates data about free space on the left edge or not. If that Bit zero is a "1", the content of the second 8yte is the

Docket BO 968 017 209820/07 96

Number of free samples in the free space on the left edge. If the bit zero in the first byte is an "O", this means that the character data immediately begins with your second byte begin, and therefore serial bit processing begins on the second byte.

Once the character data expansion is started, the following codes are used. When the end of the scan! - Bit is a "1" then the full count item is which contains this bit, the last sample post of a sample. The end of sample bit is the first bit in a full count sample post. So if there are the same bits per full count sample, they will be preceded by an end-of-sample bit that makes it a total of will be eight bits defining a full count sample item. Once the code as stated above defines the size of the full-count sample, this size is retained for the whole character during data expansion.

When an end-of-scan signal occurs, it becomes the first scan post of the next sample is treated as a differential count sample item. The data expansion system is automatically controlled in such a way that that it goes to differential count mode. The data expansion system only goes back to full-count operation when the code "111" is received. If with the data expansion system "1111" is received, it means the end of the character.

The third differential count codes are as follows. A single "0" in a bit position means that the sample post in the present sample is the same as the sample post in the previous sample. If the difference count is not "O * ¹ , the size of the count is determined by a word of different length; the beginning and end of the word are given by a binary" 1 ", and the number of" O "values between the two binary" 1 "values indicate the magnitude of the change. The code" 100Ol "accordingly means a change in the count value by 3, while the code" 101 "means a

Docket BO 968 017

- 17 means change by 1.

As for the sign of the difference count, then mean two ones in the code at the beginning of a differential counter that the direction of change is reversed as at same sampling point in the previous sampling. For example, the term "110001" means a differential count of the Quantity three and change of direction based on the difference count for that sample item in the previous sample. If the sample item in the previous sample was a full count sample item, it is assumed that the difference count will be positive on the next sample or is added, based on the full count item in the previous scan. So if the difference count Sample position pointing to a full count sample position first follows in the previous sample is negative, then the first differential count code for the differential count sample item have an "11" at the beginning of the difference count sample item.

The following Table III lists some of the codes that the computer to the data expansion system for the letter would send "e" of Fig.2. The codes are given sample after sample, except for the first line where the first two bytes of the display data are specified. The following code characters also contain spaces, which are required for the data would not give. The spaces are added here to make it easier for the reader to identify the end of each binary Word to determine.

Docket BO 968 017 209820/079 $

1 Byte sequence Table III 2 First Serial data 3 2 bytes 4th 4th lOOXXXX OOOOOOll 5 5 001101 100111 6th 6th 110001 1000001 7th 7th 1001 100001 8th 8th 101 1001 9 9 101 111 000111 000011 101010 10 10 101 1101 1001 111 000011 000010 100110 11 • O 101 101 O 101 1101 12th • 13th • 14th 14th 15th 15th O 1101 101 O 101 1101 16 • 0 0 0 0 0 0 17th • 18th • 19th 25th 20th • 101 O 101 111 101010 21st • 22nd • 23 28 24 29 1001 1001 O 1001 25th 30th 111 010000 100 100 26th 1111

The first two bytes of data from the computer, which contain character information, are given in Table III above. Bit zero of the first byte contains a "1". Correspondingly, the second byte indicates the number of samples on the left edge of the character before the start of the character samples. In the example of Figure 2 it is three samples and accordingly the second byte contains the binary character for three.

Docket BO 968 017 209820/0796

The first byte will now be discussed again, where the bits at positions "1" and "2" of the byte have "0" values is about, which means that the full count items of the character to be generated will be five bits long plus an end of scan bit. The remaining bits in the first byte are indicated by "X", since these bits are not used in the invention are used and they could be used by the data processing system for other functions.

The next line of Table III gives the binary words for sample 4 of Figure 2. Of course they would binary words in Table III follow one another, and they are only listed here line by line, so that they are easy to understand is which binary words belong to each sample. The binary words for full count items consist of five bits plus an end-of-sample bit as the first bit of each word. The first binary word has an "O" in the place of the first bit, which means that this sample post does not represent the end of the sample. The next five bits indicate the size of the Scanning post, in this case the count value 13. This corresponds to 13 for the first scanning post in the fourth Sample, according to Table II. The second sample item, indicated by the next binary word, contains one "1" in the place of the first bit of the word, indicating that this sample post represents the end of the sample. The number in binary word is seven and this of course corresponds to the seven bits or cells which the second sample post is when sampled 4 according to Table II.

Sample 5 is the first sample encoded with the difference count. In Table II is the first sample post indicated at sample 5 by the first binary word for sample 5. This binary word says change three is required and that the change must be in the direction opposite to that on

Docket BO 968017 209820 / 079G

which the decryption system is currently set. Accordingly, a change in sign must be encoded with the data of the data expansion system are communicated. The sign change is as explained earlier by a second binary "1" is communicated in the binary difference count word. Correspondingly, the first binary word says for sampling 5 a change of minus 3, as required by Table II. The second binary word at sample 5 says that there is no change in sign and the difference count is.

Similarly, the second binary word for sample requires a +5 change, as in Table II for the second sample item indicated by scan 5.

The second sample post of sample 5 does not contain an end-of-sample signal, because the question of the end of scanning in the case of differential counting operation of the components of the data expansion system will be clarified, as will be explained below.

The binary words for samples 6 and 7 represent and are differential count codes as shown in Table III compiled in the same way as just for scanning explained. It should be noted that no change in sign is needed since the same sampling point is at adjacent ones Scans in the same direction changes.

The binary words for sample 8 are significantly different from the binary words for sample 7 because of the number of sample posts changes from two to four. As explained earlier, the data expansion system goes into full count mode for some sample items back when the number of sample posts changes. The binary words for the last three sample items

of scan 8 make full count entries according to Table III represent.

Docket BO 968 017 209820/0796

The second binary word consists of three binary "ones". This is the code signal which indicates the transition to full count operation indicates. This code signal causes the data expansion system goes to full count operation .. The next binary word represents the full count for the second sample item of scan 8. The first bit or end of scan bit of the word is a "0" indicating that the second scan post does not represent the end of the scan, the binary word indicates the count 7, and this corresponds to the size of the second Sample posts according to Table II. The remaining binary words for sample 8 indicate the size of the sample posts Full counts. Of course, the last binary word for sample 8 contains a binary "1" in the first bit position or the end of sample bit position, which means that it is the last sample post of sample 8.

The end of scan signal at the end of the previous scan 8 has the effect of that the data expansion system automatically switches to differential counting operation for scanning 9. As you can see from Fig.2 and from Tables I and II, scan 9 differs from scan 8 in terms of the number of scan posts is concerned. The scan 8 consists of four items and the scan 9 of six items. The last three sampling posts from Samples 9 must therefore be encoded as full count items. The fourth word for scan 9 in Table III consists of three consecutive binary ones "111", which means that a transition to full count operation is necessary. The binary full count words for the last three sample posts of sample 9 are given in Table III below. The last scanning post has a binary one at the first bit position or end of scan bit position, which means end of scan.

The next sample 10, as can be seen in Table II, is entirely encoded in the differential count code. So if the data expansion system automatically at the end of scan 9

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Difference counter operation passes over, so it can with the decryption or begin data expansion for scan 10. For the first sample post of sample 10 there is a 0, which means that this sample post is the same as that of the previous sample. The second binary word for sample 10 in Table III means a change of -1. The third binary word of sample 10 means a change of +1. These Changes correspond to the changes indicated in Table II and they are deciphered in the same way as before for samples 5, 6 and 7.

The next scan, which differs significantly in terms of method, is scan 15. If you look at yourself Looking at scans 14 and 15 in Table I, it can be clearly seen that the scan points are the same for these two scans are. Therefore, the difference counts exist for sampling in Table II from a series of zeros. Similarly, in Table III, the differential count code for sample 15 consists of a series of binary words, each made up of a single bit, and that bit is a zero.

At sampling 25, there is a change back to full counting value operation, indicated by the signal "111" before the last sampling post. The last entry is therefore a full count entry for the count value 10 and also contains the scanning end flag "1" as the first bit. The transition to full count operation is required and therefore an end of scan flag can be used for the last scan post will.

The final significant characteristic of the data expansion code that has not been discussed can be seen in scans 29 and 30 of Table III. Sample 29 is a full count item sample. Accordingly, there is

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Signal for transition to full count operation, as above described, from a series of three ones, and this signal is the first binary word of sample 29. Sample 29 goes then continue in the typical manner using full count items.

The scanning 30 is only included in Table III / because the scanning 30 is the first scanning with which no part of the small character "e" as shown in FIG. 2 is generated. The binary word for sample 30 is a series of four ones. A series of four binary ones is the code which indicates to the data expansion system that the end of the character has been reached.

So far, the description has related to the code with which the data expansion system works. The coding of the scanning posts in full count items and differential count items is critical to the invention and is included also restoring the data to its original full count form. The essential thing about the code is the fact that a large percentage: of the data by differential count coding can be coded and therefore transfer work or in the operational control systems of a computer Memory work is saved. The core of the invention is the storage or transmission of compressed data as well as the use of data expansion circuits for expanding the compressed data to full count values, whereby the data for Can be used for display or control purposes, for example in a light setting device. A preferred embodiment of the data expansion system is shown in FIG.

The connections between the functional blocks in Fig.3 are complete, apart from the control signals and reset signals. The control signals and reset signals are activated with

Docket BO 968 O _{17 2098? N / n7g6}

later illustrations will be received showing the single version the special function blocks shown in Fig.3 are show.

The data flow from the computer reaches the input register 50. The data comes from the computer as bytes with 8 bits. The input register 50 contains a parallel memory bank for parallel storage of the 8 bits on arrival. The register contains also components with which the parallel bits are then converted into a series chain of 8 bits. At the output of the input register 50 are the positions for bit zero, bit one and bit two. The place for the bit zero is the issuing point for serial data. The positions for bits one and bit two contain the information about the full count value or the code if the first byte of character data arrives at the input register. The positions are accordingly from bit two to a decoder for the full count size 52 which will be described below.

In addition, the input register has an output cable, which all eight bits of a byte out of the register in parallel. This cable is in place so that counts for the free space on the left edge in parallel as a full byte from the input register via the AND circuit 54 for storage in the memory 56 can be directed. The AND circuit 54 is shown in Figure 4 as a single AND circuit. In fact, it would the AND circuit 54 consist of a plurality of, namely eight, AND circuits which are connected in parallel, and each one individually AND circuit would forward one bit position in the byte. The two controlling control signals for the AND circuit 54 go to all eight AND circuits, and each AND circuit can then pass one bit of the eight-bit byte.

One of the release signals for the AND circuit 54 is the Docket BO 968 017 2 0 9870/0796

2U53341

Signal for free space at the left edge, which the decryption device 58 generated for free space. The function of the free space decryption circuit 58 is to indicate that there is free space on the left edge in front of the scanning post of a character, and furthermore it is your task The beginning of the character, i.e. the beginning of the sampling point. The decryption facility for free space responds to the serial data entered, to an initial cycle signal from of the mode control unit 60 as well as a signal for the first byte, a signal for the second byte and a signal for the third Byte from the computer. The signals for the first byte, for the second byte and for the third byte are signal pulses that go to the right Time the first byte, the second byte and the third byte of the character information from eight to the beginning of each character accompany. The pulse for the second byte also serves as an enable signal for the AND circuit 54; so that only becomes that second byte of the input character data for storage in memory 56 is allowed through. Of course it's only the second byte which contains the count of the free space at the left edge, in case there is free space at the left edge at the beginning of a character gives. The operation of the free space decoder 58 will now be described with reference to FIG to be discribed.

When the first byte consisting of eight bits is in the input register, the decryption device works for the size of the full count and extracts from bit one and bit two of the eight-bit byte how large the full count items are for the character that is to be lighted . The decryption device for the size of the full count value 52 reacts to the positions for bit one and bit two in the input register, also to the start cycle signal from the operating mode control unit 60 and further to the display for the first byte from the computer. The task is to decipher bit one and bit two, the size of the full count

Docket BO 968 017

209820/0796

2U53341

to determine item and to forward this size information to the input gate 62 (gate circuit) of the memory.

The task of the input gate of the memory is to control whether data from cable 63 or data from cable 64 or serial data from line 65 are passed into memory 56. The memory 56 operates on a cyclical basis, and on each cycle is divided into a write time and a read time.

The remaining input lines of the gate circuit 62 of the memory are the lines which supply the control signals after which the data flow in the gate circuit in the memory 56 is forwarded. The signals transmitted via the cable 66 come from the mode control unit, the signals are for initial cycles, full count operation and differential count operation. In full-count operation, the gate circuit 62 receives serial data via line 65 and stores this data in parallel in the Memory 56 as part of a circulating operation with the aid of buffer register 68. As is each bit in the serial data string comes to the gate circuit 62 of the memory, it is passed on to the memory during the write time. In the reading time of the same cycle, the bit is passed to the buffer register and from the buffer register 68 back via cable 63 and cable 63A to the Gate circuit 62 of the memory. During the next memory cycle, the next bit of the serial data chain will be parallel with the first Bit written into memory. In the next reading time, the two bits are then passed to the buffer register 68 and back to gate circuit 62 as before. This circular * process continues until all bits of a full count item, as prescribed by the decryptor for the size of the full count value 52, at a scan address in the scan memory area of the memory 56 are completed.

Docket BO 968 017 209820/0796

_ 27 -

In the differential count operation, which will be described in detail later is read, the count item (or sample item) is read from the sample storage area of the memory 56 into the buffer register 68 and back to the enlargement and reduction unit 70 where it corresponds to the difference count signal is changed and then passed back into the scan memory via the input gate 62 of the memory.

When completing full count items and also when correcting previous sampling items with differential counts output the control devices of the memory from a scan cycle signal, which the input gate 62 of the memory as well the scan address controls 74 enables. If for a full scan, decryption and completion in the scan memory area of memory 56, a scan transfer duty cycle begins.

Upon scan transfer, the scan posts are read from the scan storage area of memory 56 into buffer register 68. They are then fed back to the input gate of the memory via cables 63 and 63A. The scan transfer signal from the memory controllers goes to the input gate 62 of the memory and enables the input gate of the memory which returns the recirculated scan post to the memory 56. This time, during the write phase of the memory cycle, the sample item is stored in the write storage area of the memory and not in the sample storage area. The whole process continues until all of the sample items of a sample have been transferred from the sample storage area of the memory to the write storage area of the memory.

There is another remaining function of memory which is referred to as use cycle operation. The usage cycle takes place in relation to the display control device

Docket BO 968 017

during the actual light setting of each scan photosensitive film. When the display controllers need more scanning posts to control the display device they generate a usage cycle request signal. When a use cycle request signal is received from the memory controllers received, then they interrupt the other work such as the completion of full counts or Differential counts or the transfer of sample data and immediately send a sample item from the write storage area "of the memory to the display controllers. The controllers of the memory generate the use cycle signal which sets the AND circuit 72 so that the sample post is passed from the buffer register to the display controllers. Once the sampling post from the write storage area is passed to the display controllers, the memory reverts to the previous work, which is either may have been a scan cycle or scan transfer. The AND circuit 72 in Figure 3 is representative for multiple AND circuits which would route a sample post in parallel to the display controllers.

^ The buffer register 66 is simply a register for storage of eight data bits and one identification bit. Each stage of register 68 operates in parallel with the other stages. The data from the memory is input to the register in parallel and is passed out of the register in parallel. The details of register 68 are not shown since such a register is common in the field.

Likewise, no details on the memory 56 and its memory controls since they are not part of the invention and there are many memories as well as many addressing controls and logic which can be used to perform the function of memory 56 as well as its controls. An exception

bo 968 017

the scan addressing controls used in the preferred embodiment of the invention as shown in Figure 3 are certain perform unique functions. In the lower middle of FIG. 3 there is a block for the scanning addressing controls 74.

The scan address controls operate in scan cycle operation of memory 56 and place the scan post at Completion in the scan memory area of the memory 56 to follow-up addresses. The scan addressing controls operate either in full count operation or in differential count operation. In each of the two operating modes, a new scan is carried out completed in the sampling memory area of the memory. aside from that In differential counting mode, the scan addressing controls keep track of which scan post is the last scan post Scanning is. In other words, the scan addressing controls monitor the end of scan and generate a Scan transmit set signal when a full scan completes in a scan memory area of the memory is. The scan transfer set-up signal is passed through the OR circuit 76 to the memory controllers and initiates the scan transfer operation in memory. The scan transfer set signal from scan addressing controller 74 is generated in a differential counting operation. The same signal is output from the end-of-scan decoder in the full-count operation 78 generated.

To decide whether the data expansion system is in Full count value operation or differential count value operation work should, the operating mode control device 60 is present. The mode controller 60 starts operating when the Character start signal from the decoder for free space 58 comes. At the beginning, the mode controller generate a signal for full count operation. When an end-of-scan flag is detected in full count mode is generated, the mode controller automatically generates

Docket BO 968 017 200820/0790

2Ü53341

Signal for differential counting operation. The remaining output signal of the operating mode control device is the start cycle signal, which is only present during the first bit of each full count sample item. To generate this The operating mode control device responds to three signals for full count operation, differential count operation and initial cycle (read from top to bottom at block 60 in FIG. 3) start of character, if there were two ones, on serial data, on end of character, on full count samples but not end of sample as well as on sample transfer setting (from decoder for end of scan 78). The detailed design of the operating mode control device 60 is shown in FIG and will be described below.

For the detection of the end-of-scan indicator in full-count operation End scan decoder 78 monitors the serial data during the initial cycle. The decryption device for the end of scanning only works in full-count mode. If during the initial cycle (first bit of each full count item) the serial Data contains a one, the end-of-scan decoder indicates the end-of-scan for the output, marked with EA on the decryption device 78 in FIG is. In addition, the end-of-scan decoder also shows another output line on when a full count item has ended but no end of scan flag came. Finally, if the end-of-scan decoder detects an end-of-scan flag, it also generates a scan transmission schedule signal, which is passed through OR circuit 76 and indicates to memory controls the scan transfer operation initiate.

In the case of differential counting value operation, the decoding device for differential counting value 80 is in operation. The task of

Docket BO 968 017 209020/0796

It is the coding device for the difference count monitor serial data at differential count. Based on the data, the decoder shows the difference count how much a full count item must be changed in the previous scan in order for the present full count item to be arises. The differential count operation with the differential count items is bit-serial. The decryption facility for difference count first determines whether there is a change in direction (or sign change) for the difference count item is required. When the change of direction is desired, the decoder gives differential count a signal to the antivalence element 82. The antivalence element 82 has the task of the sign identification bit to change from the buffer register when the decryption device for difference count indicates a change in direction. This identification bit indicates the last direction of change for the item in question. The sign flag from the exclusive OR element 82 is passed to the input gate 62 of the memory and stored back into memory 56 during the write time of the memory cycle.

At the time the sign flag is corrected is, the count for a sample item is incremented or decremented by one by the circuit for Zoom in and out 70. Whether circuit 70 increments or decrements depends on the output signal of the antivalence link 82. When the full count on the circuits to enlarge and reduce via cable 63B is given, the decryption device for difference count 80 outputs an increment signal which causes the circuit for enlarging and reducing the "VbIlzzählwert increased by one or decreased by one, depending on the identification bit of the non-equivalence element 82. The corrected The count is then passed to the input gate 60 of the memory and back into memory during the write time in the memory cycle

Docket BO 968 017 509820/0796

entered the memory 56.

If another change to the counter value is required at reading time is indicated by the difference count code, becomes the same count item of the circuit for enlargement and Reduction again via the buffer register 68 in line 63B fed. The increase and decrease circuit 70 corrects the full count again. This process continues until all difference count zeros in the difference count value code are used up and the full count value is completely corrected via the difference count. At this time, the difference count decoder 80 generates a sample addressing change signal, which is input to the scan addressing controls 74.

The scan addressing controls select the next item for a differential count change. At the last count item after the scan, the scan addressing controls determine that the scan is complete and generate a scan transmit set signal, which is passed from the OR circuit 76 and causes the associated sample data be moved from the scan storage area of memory to the write storage area as described earlier. Reading out there is no deletion from the sampling memory. Therefore, the sample pots remain in the sample memory for correction Difference count codes when the next sample post is established are obtained.

The only remaining function in the data expansion system fulfills the end-of-character decryption facility (EOC). The decryption device for the end of characters 84 is to record the code for the end of the character and inform the computer that! That new character information (starting with the first and second byte of a new character) the input

Docket BO 968 017 209820/0798

register 50 can be forwarded. Besides, the decryption device generates for end of character, a signal which notifies the scan addressing controls when it is the count item that will be completed is the first item of the scan.

Reference is now made to pig.4 for the circuits for Clock signal generation are shown. These clock signals were not shown in FIG. For the description of the detailed execution For some of the blocks in Fig. 3, however, it is necessary to understand the timing and direction of the signals which the blocks work and which they produce.

In Figure 4, the time pulse source is a clock 91, which at emits four clock pulses in each working cycle. The clock pulse outputs Bl, B2 and B3 are shown in Fig.3. B4 is not shown as this particular pulse is not used in the preferred embodiment of the invention. the Clock pulses repeat once per cycle in the order of their numerical designation, i.e. in the Sequence B1, B2, B3, B4, B1, B2, B3, B4, etc. In addition to the pulses B1, B2 and B3, there are also two controlled pulses OBL and 0B3 generated. These pulses occur simultaneously with B1 and B3, but they are controlled in such a way that they do not occur if either a use cycle or a scan transfer operation is carried out.

To generate the controlled pulses OB1 and OB3, the Use cycle request signal by inverter 92 reversed, while the scan transmission signal through the inverting stage 93 is reversed. These inverted signals then go to AND circuit 94. At AND circuit 94 there are that is, an output signal only if the usage cycle request and scan transfer signals are both absent. The output signal the AND circuit 94 goes to the inverter 95.

Docket BO 968 017 209820 / 079Θ

The inverter 95 thus has an output signal until one of the Usage cycle signals or scan transmission present. The output signal of the inverter 95 is the AND circuit 96 free, so that the time pulse B1 is allowed to pass and the time pulse OBl is generated. The disappears accordingly Time pulse OBL when either the usage cycle request signal or the signal scan transmission is present.

The output of AND circuit 94 also goes as a DC signal to the polarity hold circuit 97. At the time of B1 when the AND circuit 94 outputs an output signal, will the polarity hold circuit made. The output signal of the The polarity hold circuit then enables the AND circuit 98 so that the pulse B3 is passed on at the time of B3 and the pulse OB3 arises. When there is a use cycle signal or a scan transfer signal, the AND circuit has no high output at the time of B1 and the polarity hold circuit 97 is not set high. If the polarity hold circuit is not set high, then it has no output which the AND circuit 98 releases. The controlled time pulse OB3 is therefore not generated when either a usage cycle request signal or a scan transmit signal is present.

The input register 50 of FIG. 3 is shown in more detail in FIG. The input register consists of a linear series of OR circuits arranged in parallel, which are indicated by the reference number 100 , a linear series of linearly arranged polarity holding circuits which are responsive to the OR circuits and are indicated with the reference number 102, and finally a second linear one A series of polarity hold circuits which are responsive to the first series of polarity hold circuits and are identified by the reference numeral 104.

Docket BO 968 017 209820/0796

The entered data bytes, consisting of 8 bits, go parallel to lines zero to seven on the left in Fig. 5. Each bit becomes one of the OR circuits 100 of the polarity hold circuits 102 are passed. At the time of 0B3, the polarity hold circuit is set to the binary value of the signal that comes to them via the OR circuits 100. So, at the time of 0B3, the input data is stored in the polarity hold circuits 102. The output of each polarity hold circuit which its reproduces binary state is passed to the polarity hold circuits 104. At the time of OB1, these polarity hold circuits set to the value they receive from polarity hold circuits 102. Accordingly, at the time of OBl the eight-bit byte which is in the polarity hold circuits 102 is shifted to the polarity hold circuits 104.

The output signals are used for serial conversion of the parallel data of the polarity hold circuits 104 are fed back to the OR circuits 100 and become that of the polarity hold circuits 102 given for the next higher bit position. During each clock cycle of the control pulses OB1 and 0B3 the parallel data is shifted up until it reaches the highest polarity hold circuit 104A. To eight clock pulse cycles, the eight parallel bits are serially given to the outside from the polarity holding circuit 104A. When the last or eighth bit is in polarity hold circuit 104A, the computer outputs the next eight-bit bytes to the OR circuits 100.

The cable 106 at the bottom in Fig. 5 is the cable with which the byte consisting of eight bits is passed on in the form of parallel bits to the AND circuit 54 in FIG. This data byte provides the counting information about the free space on the left

Docket BO 968 017 20 982Ö / 0796

Edge represent; it is shifted in parallel and does not have to be converted serially. The second byte signal from the computer, which controls the position of the AND circuit 54 in FIG. 3, the pulses OB3 and OBl come during the first clock cycle.

The only remaining output lines of the input register are the places for bit one and bit two of the polarity hold circuits 104B and 104C, respectively. These output bits become the decoder for the size of the full count 52 in Figure 3 let through, during the first Byte signal after the bits are input to the polarity hold circuits 104B and 104C by the pulse OB1. While of the first byte, these bits contain the code for the size of the full count.

In Figure 6 is the free space decoder shown in detail. Your job is to decipher the first bit or bit zero in the first byte of the character data. The free space decoder receives serial data over line 110 from the input register. At the time, in which the bit zero is present, the computer sends an impulse for the first byte. The pulse for the first byte is the same length like a clock cycle from pulse Bl to pulse B2. When this pulse is for the first byte, the AND circuits are 112 and 114 released. The AND circuit 112 has an output signal when the first bit or bit zero is a "1" during AND circuit 114 then has an output signal when bit zero is a "0". The AND circuit 114 has an output signal because the zero in the position of the bit zero is reversed by the inverter 116 into a condition signal or high level signal will. If the AND circuit 112 has an output, it means that bit zero was a "1" and that a count value for free space on the left edge is stored in the second byte. The output of AND circuit 112 becomes the position of the

Docket BO 968 017 209820/0796

of switch 118 is used. The output of the switch 118 is the signal for free space at the left edge, and it prepares the AND circuit 54 in FIG. The desk 118 is not reset until an initial cycle pulse is received from the mode controller. The mode control generates an initial cycle in response to a character start signal, i.e. when the switch 118 by the bit NUIl in the first byte is set, it remains set until the character start signal is over, i.e., until after the serial data sample post begin to contain.

The character start signal is generated at the beginning of the first byte which contains sample items. It can be either be the second byte if there is no free space on the left edge, or it can be the third byte if there is free space on the left edge.

The character start signal means the start of sampling posts. To generate the character start signal when there is free space on left edge is present, the switch 118 enables the AND circuit 120. The AND circuit 120 then outputs a pulse signal for the third byte from the computer continues at the beginning of the third byte. This pulse for the third byte is used as the character start signal forwarded by the OR circuit 122.

The switch 124 and the AND circuit are used to generate a character start signal when there is no free space at the left edge 126 available. If there is no free space on the left edge, the first bit or bit zero in the first byte is one "0" and causes the AND circuit 114 to output Has. AND circuit 114 then sets switch 124. Switch 124 remains set until an initial cycle signal is received is what resets it. The start cycle signal is generated in the mode controller 60 (FIG. 3) when there is a character start signal in the mode control

Docket BO 968 017 200820 / Ο70β

comes in. The switch 124 thus remains set until after the character start signal is generated. The output of the switch 124 is used to enable AND circuit 126. The AND circuit 126 then gives the pulse for the second byte from The computer continues when the second byte is entered into the input register 50 (FIG. 3). This pulse for the second byte, which is passed on by the AND circuit 126 is also passed on by the OR circuit 122 and Character start signal when there is no free space at the left edge.

In Fig.7 are the details of the decryption device for the size of the full count value. The decryption facility for the size of the full count value stores bit one and bit two from the input register during of the first byte. Thereafter, at the beginning of the character, which is signaled by the initial cycle, the decryption device determines the size of the full count value in a logical manner the size of the full count items from the two bit code and forwards the full count value signal to the memory input gate 62 (FIG. 8).

To store bit one and bit two, the polarity switching circuits 128 and 130 are present; the polarity hold circuits are set by the pulse for the first byte moved up or down to the polarity of the register positions for bit one and bit two. During the first Byte, these bits are the two-bit code that relates to the size of the full count.

A logic circuit consisting of AND circuits 132, 133, 134 and 135 and inverters 136 and 137 is used to decode the two bits into a signal for the size of the full count. Each AND circuit is enabled by a different two-bit code . If the two bits

Docket BO 968 017 20 9820/0706

Represent "00", the inverters 136 and 137 give the AND circuit 132 free. When the code is "01", the AND circuit 134 is set by the inverter 136 and the polarity hold circuit 130 released. When the code is "10", the AND circuit 133 is set by the polarity hold circuit 128 and the inverter 137 enabled. Finally, when the code is "11", the AND circuit 135 is closed by the polarity hold circuits 128 and 130 released. The AND operations only have an output pulse when the initial cycle pulse is generated by the operating mode control at the beginning of the character. When the initial cycle pulse occurs, the AND circuit, which was enabled by the two-bit code, an output pulse. So the size of the full count is through the output line of the decryption line for the Size of the full count which has a pulse during the initial cycle.

The gate circuit of the memory input gate 62 is shown in FIG 3 shown in detail, comes over the cable 140 the information on the size of the full count from the decryption device for the size of the full count value 52 (Fig. 3). The eight bits come from the buffer register via cable 64A 69 (Fig. 3) into the memory input gate, via the Cable 64 comes the incrementally increased or incrementally decreased counts from the circuit for magnification and Reduction 70 (Fig. 3). How the information from the cables enters the memory is determined by the linear sequence controlled by AND circuits 142. With the exception of the AND circuit at the position of the identification bit above in Fig. 8 the logic for each of the tit positions zero through seven from three AND circuits whose output signals are collected go to a single OR circuit. In either case, the topmost AND circuit is activated by a scan transmit signal controlled by the storage controls. The middle AND circuit in the group of three there is a signal for dif-

Docket BO 968 017 209820/0796

Reference number operation controlled by the operating mode controller 60 (Fig. 3). The lower AND circuit in the group of three is controlled in full count operation.

As already described earlier, the memory changes cyclically between writing time and reading time. In the write time, if an AND circuit in row 142 of FIG. 8 is enabled, it conducts the binary bit which it receives via one of the cables into the memory. This bit is then written into a nine bit word in memory at an address dictated by the memory controls or scan addressing control (74) (Figure 3). During the read time of the memory reads the memory cell addressed which, ■■ *> is, every eight bits and the sign Kennzeiehnungsbit (nine bits) into the buffer register 68. (Figure 3). The contents of the buffer register are then fed back to the memory input gate via cable 63A or cable 64 when incremental increments or decrements are required.

It is now first on the full count operation of the memory input gate received; the condition signals for the relevant AND circuits are the signal for full count operation and the initial cycle non-existent signal. These signals go to the AND circuit 144. The signal for The absence of an initial cycle is of course derived from the initial cycle signal by using the latter signal the inverter 146 is reversed. In fact, the lower AND circuit of every group of three is in full-count operation enabled at every bit position except during the initial cycle. The initial cycle corresponds to the first bit position in the serial bit flow. This bit position contains the end of scan flag and there is no need to to put this flag in the memory. Likewise, the AND circuits are during the end-of-scan bit or the initial cycle blocked. The serial data flow

Docket BO 968 017 209820/0796

reaches the memory input gate at AND circuit 148, which is the AND circuit for full count operation in the position of the lower bit (or bit seven).

During the initial cycle full count operation, the memory input gate has an important task. This is to route the initial cycle bit over cable 140 into memory. This The initial cycle bit indicates, depending on which line it is coming via cable 140, whether the size of the full count is five bits, six bits, seven bits, or eight bits. When the initial cycle pulse comes over one of the lines in cable 140, will he immediately to one of the OR circuits in the lower four bit positions forwarded. As will be described below, this pulse will be transmitted through one of the OR circuits is given to memory and written at the first address, eventually as the sign flag serve for the full count sample item.

Docket BO 968 017 2 0 9020/0796

The serial data are applied to AND circuit 148 to complete the full count items in full count operation. As just described, in the first bit position the sign flag from the decryption circuit for the size of the full count is a bit "1", and it is inserted at one of the bit positions four, five, six or seven. If we assume that the total count item is a Is a five-bit item, the sign flag is inserted in bit position four and in a memory cell stored, which has nine bit positions, of which all contain zeros except for the bit position four, which then contains one Contains "1" for the sign flag. When the second bit arrives in the full count item, it is passed through AND circuit 148 to OR circuit 150 which is the OR circuit for bit position seven acts. In the meantime, the identification bit has been read out in the read time from the memory to the buffer register 68 (Figure 3) has been fed back via cable 63Λ and applied to AND circuit 152. The AND circuit 152 is enabled in the same way as the AND circuit 148, and that is that Flag bit shifted up to OR circuit of bit position three when the second bit of the full count item is in the OR circuit 150 arrives at bit position seven.

The nine bits, which consist of the sign flag and bits zero to seven, are then again at the same address during the write time in the memory entered and read out again into the buffer register during the reading time. The next time they're led back to the storage input gate, they'll have to move up into one shifted to another position when the third bit of the full count item goes to AND gate 148 and OR gate 150. So when the third bit comes in, that's where it is Sign identifier bit in bit position two and the second bit in bit position six, while the third is Bit is in bit position seven. The completion of the

Docket BO 968 017 209820/0796

The full counter value item goes in this way with return from Buffer register and with higher shifting of the bit positions in the memory input gate waiter until the sign identification bit reaches OR gate 154 for the flag bit. At this time the OR circuits have in the memory input gate a sign flag "1" at the flag bit position, and the five bits of the five-bit count for the full count item are in bit positions three / four, five, six and seven.

To change the address in the itast memory of the memory Completion of a full-count value item becomes the position zero of the buffer register is monitored by end-of-scan decoder 78 (FIG. 3). The decryption facility end of scan will then generate an end of full count item signal, but no end of scan signal. This signal becomes the decryption device for Difference count 80 continued (Fig. 3), which in turn a signal for scan addressing change is generated. The scan addressing footsndarur.g signal is sent to the scan addressing controls 74 fed ^ i Ag, 3) and changes the address in the sample memory area of the memory in preparation for the completion of the next full count value item. The address but is only changed when the content of the buffer register returns to the memory input gate and the old one Sample memory address is circulated. This repeated circulation back to the memory input gate is needed for the shift of the identification bit in the identification bit position and for the complete completion of the full counting value item of this Address. In terms of time, the read operation and the write operation in the memory correspond approximately to the clock pulses B2 and B4, i.e. read takes place at B2 and writing takes place at B4. In this way, the complete full count entry is placed in the old address of the scan memory before the address is changed in preparation for the completion of the next complete counter value item.

Docket BO 968 017 2090 ^ 0/0796

The middle AND circuit of each group of three AND circuits for each bit position is used during differential count operation used. If there is a signal for differential counting operation, the middle AND circuit is enabled, and an eight bit byte from cable 64 is entered into memory. This consisting of eight bits Byte is the incrementally incremented or incrementally decremented count from the increment and decrement circuit 70. In short, in differential counter value operation, the full counter value, which is incrementally increased or incrementally

r reduced must be read into the storage register during read time and then passed back to the enlargement and reduction circuit 70 via cable 63B (Figure 3). The total count is increased or decreased in steps and then goes back via cable 64 to the memory input gate, where it is then stored again at the same location in the sample memory during the write time of the memory. This process continues until a full count item is corrected by a difference count. When the correction is complete, the differential count decoder 80 generates a sample address change signal which is applied to the sample addressing controllers 74. The scanning addressing

fc tion controls then change the address with which in the scan memory is worked and cause differential counting operation effectively occurs with the next count item to be corrected.

When a whole sample is stored in sample memory, send the scan addressing controls or the scan end decoder provide a scan transfer control signal to the memory controls. The memory controllers then initiate a scan transfer operation and give a condition signal for scan transfer to the memory input gate. The sampling transmission signal is the upper AND circuit of every group of three of AND circuits for one

Docket bo 968 017 209820 / n79G

every bit position free. In the case of scan transmission, the memory controls operate that each sample post is read out from the sample memory into the buffer register. The scanning posts are then fed back to the memory input gate via cable 63A, where they are returned to memory via the topmost AND circuits of each bit position and stored in the print memory will. The Speieher controls control the addressing of the Output of the items from the scan memory to the buffer register and likewise the addressing for storing these items in the write memory during the write time of the memory. In the end, when all the scan posts of a scan have been transmitted, the memory controls generate a signal for scan transmission end, and the scan transfer condition signal applied to the memory input gate is cleared.

Addressing controls for memories are a well known developed technical field and have by and large not been described for the purposes of this invention. but the scan addressing controls for scan storage perform some tasks such as completing the full count items and the detection of the end of scanning in differential counting operation, which are particularly useful in the present invention. Therefore, the scan addressing controls become, which fulfill these tasks, described in an elementary manner and a representation can be found in FIG. 9.

The addresses with which the memory controls are used to store samples are generated in address register 170 of FIG. In the beginning, the register begins to work as follows or is reset to zero as follows: During the first post of each scan the signal is for no of the first post below. This signal comes from the decryption device for character end 84 (Fig. 3). The task of the signal for the absence of the first item is that of AND circuit 172 during the first sample post of each

Docket BO 968 017

209820/0796

Lock scanning. Actually, when the AND circuit 172 is disabled, no signals are passed to the register 170, una therefore the register 170 is set to all zeros at the time of the clock pulse B1. This group of all zeros is the first address for the first sample or first count item in sample memory. This address remains the same until the first count item is completed and a sample address change signal from AND gate 174 is received. The sample address change signal also goes to the decryption device for end of character 84 (FIG. 3) and is used to give the signal that the first item is not present. if the signal for the absence of the first item is given, then the AND circuit 172 is free. The other state of the AND circuit 172 is given at scan cycle, which simply means that when the memory is in scan transfer mode or use cycle mode works, the AND circuit 172 is blocked. But if he completes or corrects full count items of differential count items, the sample cycle will be at AND gate 172.

To change the address in register 170, the contents of the register are input to incrementing unit 178 in parallel via cable 176. The incrementing unit 178 increments the value it receives from register 170 by one and then routes it to register 180. Entry into register 180 is made at the time of B3 when the scan address change signal is present. The scan address change signal is present at the end of each completion of a count item or at the end of the correction of a count item. The register 180 then contains an address at which the position is one greater than the address which is stored in the register 170. The increased address is fed to the address register 170 via the AND circuit 172. When a clock pulse B1 comes to the register 170, this is corrected by the new address. The memory controls then direct the next count poet to this new address. That is, the count items are sequentially stored in the sample memory of the memory

Docket BO 968 017 209820/0796

56 saved (Fig, 3)

When a full scan is stored in the scan memory, a scan transfer set signal is generated by either the scan end decoder 78 (FIG. 3) or the AND gate 182 in the scan addressing controls. This Abtastübertragungs actuating signal goes to the decryption means for drawing the end 84 (Fig. 3) and causes the decryption means to mark the end, that the signal for Nichtvorliegc, ^{1 "ows:} e-cjstsn solid" falls when this signal falls is the AND. SU riltung 172 is blocked again, and the register 170 is set to zero again at {the time of the next clock pulse B1. In this way, the register 170 is reset at the end of each sampling translation and the next sampling in the sampling memory is completed; Memory controls the same address sequence as before.

Another task that the scan addressing facilities is the detection of the end of the scan in differential counting mode. The end-of-scan flag is there it only with the full count postm. Bel VoIIzähIw-rtbetrieb becomes the presence of end of scan with the decryption device detected for end of scan 78 (Fig. 3). Compare the Scan addressing controls the current address used for scan storage with the address of the last one Count item of a sample. The address of the last count item of the scan is stored in register 184. The registry 184 is activated by the end-of-scan signal from the end-of-scan decryption device during full-count operation 78 set (Fig. 3). When this end-of-scan signal occurs, register 184 stores the address which is currently is also stored in register 170, i.e. the address of the last count position of a sample. Then in differential counter value mode, when the address register 170 stores new addresses, will

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its contents are compared with the contents of the register 184 by the equality comparison circuit 186. If a If the equivalence is present, the circuit 186 has an output signal which the AND circuit 182 enables. The AND circuit 182 must also be enabled by the signal for differential counter operation. The condition that there must be differential count operation prevents AND circuit 182 from generating a scan transfer set signal in full count operation when register 184 is inputted. Currently produced by B2 then the AND circuit 182 a scan transfer actuation signal. In this way, the end of scans can be detected in the differential count mode.

As discussed earlier, it is the task of the operating mode control, the signal for full count operation, the signal for differential counter operation as well as the signal for the initial cycle to create. The details of the mode control are shown in FIG.

As for the signal for the initial cycle, it represents this signal is the first bit of each full count item. It is generated at the beginning of the character or in full count operation, but also with differential counter value operation. Initially, the signal for the initial cycle is determined by the character start signal from the decryption device for free space 58 (Fig. 6) triggered. The character start signal is via the OR circuit 190 and goes to the polarity hold circuit 192. At the time of OB3, the polarity hold circuit is set to of the output of the OR circuit 190 is set. When the character start signal is present, the polarity hold circuit 192 becomes high-pitched. This high value becomes the polarity hold circuit 194 passed, so that at the time of the passed clock pulse OBl, the polarity holding circuit 194 is set to a high value and generates the signal for the initial cycle. The signal for the initial cycle is a pulse, since the next time, too

Docket BO 968 017 ~ _{Λ A} - _AM .

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which a pulse OBl is passed through, the polarity hold circuit 192 will be at the bottom and therefore the polarity hold circuit 194 will be below. The polarity hold circuit 192 is turned down at the time of a pulse 0B3 because the character start signal is also a pulse signal and is no longer applied to the OR circuit 190. In fact, the Initial cycle pulse shape; it runs during the time of the first bit of a full count item, i.e. during the end of scan flag, which is transmitted to the decryption device for end-of-scan. I.

The OR circuit 190 also collects input pulses from two other sources to cause an initial cycle to occur. In one case it is the impulse from the decryption device for end of scan "end of full count item but not end of scan". This impulse is coming at the end of each completion of a full count item in scan memory if that item does not have an end of scan flag contained. The other input to OR circuit 190 is from AND circuit 196. The AND circuit 196 is enabled when a signal comes from the decryption device for difference count 80 which states that two ones were present (Fig. 3). This signal always comes "when the decryption device for difference count value two Detected consecutive ones in the serial data chain. If the next bit in the serial data chain is also a one and thus there are consecutive three ones in succession, the AND circuit 196 has an output signal. A signal of AND circuit 196 thus means that three consecutive ones were received. If you have the data extension code considered, it is found that this is the code with which transition from differential counting operation to Full count operation is triggered. Accordingly, there must be a beginning cycle are generated, and the AND circuit 196 generates a pulse which is output from the OR circuit 190 for the polarity hold circuit 192 is collected so that a preliminary

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cycle pulse is generated.

The remaining tasks of the operating mode control consist of In the generation of the signals for full count operation and differential count operation. These signals are generated by switch 198. If the switch is set, its output is "one" or its set output is up, which means full-count operation. if the switch is reset, its output is "zero" which means differential count. As has been said earlier, will the switch 198 is set by the AND circuit 200 in response to a signal from the folarity hold circuit 192 and at the time at which a clock pulse OBl is passed through. So every time an initial cycle is generated, the switch becomes 198 set in such a way that it indicates full count operation.

The switch 198 is reset by one of two conditions to indicate differential count operation. At the beginning the switch is reset by an initial reset pulse which comes from the computer. Usually, however the switch is reset in that a scan transmission control signal has enabled the AND circuit 202. If the AND circuit 202 is enabled, the next clock pulse Bl passed through the AND circuit 202 and the OR circuit 201 and resets the switch 198 to differential counting operation. In fact, this means that at the end of each scan the operating mode control automatically switches to differential counting value operation switches.

The remaining components of the operating mode control, which are still not described are there to prevent the signal for differential counting operation from other devices of the Data expansion system reached in the time between the initial reset and the beginning of the character. The initial reset signal goes through the OR circuit 204 to the reset switch 206. When switch 206 is reset, AND circuit 208 is disabled. The signal for differential counting operation,

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which the switch 198 outputs cannot go to the other components the data expansion system.

When the character start signal comes, the switch 206 is set, and the AND circuit 208 is enabled to forward the signal for differential counting operation. When the end-of-character decoder 84 detects the end-of-character condition (Fig. 3), the end-of-character signal is passed from the OR circuit 204, and the switch 206 is reset. Through this again, the passage of any of the signals will be for differential count operation prevented by the UNi * circuit 208. In the In the time between the initial reset and the start of the drawing, the light setting system can fulfill other functions, and it will thereby preventing the difference count decoder 80 (Fig. 3) from being used in the time between character end and start of character or between initial position and start of character is working. It should be noted that although the character start signal sets switch 206 and thus AND circuit 208 releases, the signal for differential counting operation is in any case quickly cleared, since the character start signal also for the Setting the switch 108 to the time of the clock pulse OBl ensures. Thus, the data expansion system starts at the beginning of 2-character data in full count operation.

11 shows the detailed structure of the decryption device for end of scan. The scanning end signal is a pulse signal which the AND circuit 210 generates. The AND circuit is activated by the initial cycle signal from the mode controller and enabled by the passed clock pulse 0B3. If the data bit is a "1" on the initial cycle, the AND circuit 210 has an output signal. The data bit present in the initial cycle is the end of scan flag. Accordingly, the output signal of the AND circuit 210 indicates the end of scanning in the full-count operation. The end of scan signal is used by the scanning addressing controls and the

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encryption device for end of character (EOC) used. It also becomes switch 212 in the decoder for end of scan.

The end of scan signal sets switch 212, and the set side of switch 212 then sets AND gate 214 free. The AND circuit 214 must also be enabled in that there is a binary at position zero of the buffer register One is located. The binary one at position zero of the buffer register means that the sign flag is at has reached position zero after completion (see the description of the memory input gate above).

If, therefore, the switch 212 has been set by a scanning end signal and if the sign flag is present at position zero of the buffer register, then the passed clock pulse OB3 is passed on by the AND circuit 214 and signals scanning transmission setting. In fact, this signal says that the last full count item a scan has been completed in the scan memory and now the entire scan can be transferred to the write memory.

The switch 212 which actually stores the fact that the count item contained an end-of-scan character reset as soon as the scan transfer set signal causes the mode control to switch to differential count operation switches. When the signal for differential counting operation arrives, the signal for full counting operation is cleared, and the inverter 216 resets the switch 212.

The remaining task that the end-of-scan decoder performs is to generate one Signal for the end of a full count item if there is no end of scan. This signal means that a full count sample item has been completed in the sample memory and

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that this post is not the last post Scanning acts. The signal is generated by AND circuit 218. The AND circuit 218 is through the reset side of switch 212 enabled, as well as by the signal for full count operation from the operating mode control. Accordingly, when the sign flag appears at the Completion of the full count entry reaches position zero of the buffer register, a binary one at position Zero of the buffer register, which is passed on by the AND circuit 218 and is used to generate the signal "End of a full count value item, but not end of scan".

The purpose of the differential count decoder described earlier is to to decipher the difference counts, which come serially from the computer, bit by bit, so that it is displayed as a Scanning posts must be corrected, both in terms of direction and size. The decoder for differential count is activated by the signal for Differential count operation, which enables AND circuit 220, is turned on. The AND circuit 220 is also provided by the Output signal of the inverter 222 enabled. This signal states that the differential count decoder of Fig. 12 does not have previous differential count information contains. When AND gate 220 is enabled, the first binary one of the serial data stream that arrives is passed through the AND circuit, and at the time of the pulse 0B3, the polarity hold circuit 224 becomes high posed. Immediately thereafter, at the time of the pulse OB1, the polarity holding circuit 226 is set to a high value. The output of polarity hold circuit 226 indicates that a binary one was received in differential count mode. This signal enables the AND circuit 228, so that a second binary one can be searched, and it is also passed through the OR circuit 230, making the AND circuit

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search for a binary zero in the data series. The AND circuit 232 searches for zeros in the data series since it is the serial data can be entered through the inverter 234. Even this output signal of the OR circuit 230 is reversed with the inverter 222 and blocks the AND circuit 220.

When the next bit of serial data arrives and it's his is a zero, it means that the previous count item which is now being corrected has been changed by one level must become. Such a binary zero is passed through AND circuit fc 232, and at the time of 0B3, polarity hold circuit 235 is caused to be set high. Therefore, at the time of the pulse OB1, the polarity hold circuit becomes 236 set to a high value. When the polarity hold circuit 236 is set, it means that a change bit or zero bit was received in a change code.

To signal the stage or advance to the zoom in and zoom out circuit 70 in Figure 3, it will be used the bit zero, as output by the inverter 234, is passed directly to the AND circuit 238. The AND circuit 238 becomes free because the polarity hold circuit 226 was set by the previous binary one. Therefore, the AND switch ^ device 238 transmit a pulse signal which will cause that the circuit for enlargement and reduction increases or decreases the count value poet u »a single count value. Whether it is enlarged or reduced depends on which signal is received from the antivalena member 82 (FIG. 3). This further switching of the incremental switching takes place immediately afterwards Input of binary minor. To the side of OBl when the binary zero effectively causes the polarity hold circuit 236 to be set is, the polarity hold circuit 226 is effectively reset because the polarity hold circuit 224 a & output none Has high value. When the polarity hold circuit 236 is set to a High quality let, »ο she will continue to use the üND

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Enable device 238 via OR circuit 230 if the next incoming serial bit is also a zero acts. The next incoming bit zero is treated in exactly the same way as the first bit zero that was received, and the output signal advances or switches on of AND circuit 238 and further causes polarity hold circuits 235 and 236 to be set high stay. Eventually the difference count code ζυ will end when a binary one comes in via the input line for the serial data. When that binary one arrives, it will it passed directly to AND gate 240, which was enabled by the earlier bit zero which also caused the Polarity hold circuit 236 is set. The AND circuit 240 then has an output which the OR circuit picks up and thus a scan change address is given to the scan addressing controls displayed. The scan addressing controls will then cause the memory to read the The next count item is addressed and the correction of that count item by the difference count code can begin.

It should now continue to the second bit in a difference count code be entered, for which the code rules state that if it is a binary one, the decryption device must indicate a change of direction for the difference count value, based on the change in the same count value item, which was present in the previous scan. The first binary one in the difference count code has as described above caused the polarity hold circuit 226 to be set high. The output of the polarity hold circuit 226 enables AND gate 228. So when the second bit represents a binary one, the AND circuit becomes 228 have an output, and at the time of the pulse 0B3, the polarity hold circuit 224 is set high will. Then at the time of the pulse OB1, the polarity hold circuit 246 is set high. An output signal

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the polarity hold circuit 246 says that there are just two binary Ones came in over the line for the serial data. That those two ones came is passed to AND gate 248, enabling it. The AND circuit 248 then passes the first bit zero in the difference count code, and this signal indicates that a change in direction is required in order to correct the present count item. This direction change signal goes, as described above, to the non-equivalence element 82 in FIG. 3 and causes it in effect, the sign flag is fed back from buffer register 68 (FIG. 3) to change state. The changed sign identification bit is then read back into the memory via the input gate and changes also the state of the circuit for enlargement and reduction either from enlargement to reduction or from reduction to enlargement.

The output of polarity hold circuit 246 is also routed to the operating mode control 60 as an indication of the presence of two ones (FIG. 3). The mode control 60, as described earlier, uses this signal to the Command for switching back from differential counter value operation to full counter value operation to be determined. In addition, the output of the polarity hold circuit 246 holds the AND circuit 238 free for the first bit zero in the difference count code. Of course, bits zero thereafter will cause the polarity hold circuit 236 to be set so that the AND circuit 238 for the sequence of bits zero in the difference count code, which can enter is kept open.

Another possibility for differential counter value operation is that the first bit of the differential count code is a zero, indicating that this count item need not be changed. If this occurs, AND circuit 250 will have an output signal. The AND circuit 250

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is activated by the signal for differential counting operation and by the signal from the inverter 222, which was not previously present, is enabled. If a bit zero occurs as the first bit in the difference count code, the inverter 234 has an output signal, which is passed on from the AND circuit 250. The OR circuit 242 receives the output of the AND circuit 250 and generates the signal for scan addressing change. This scan address change signal is passed to the scan address controls which then signal the memory controls to proceed to correct the next count item.

Finally, the OR circuit 242 is used in the decryption device for differential count values to receive a further signal which can cause a signal for scanning addressing change to be generated. That signal is that End of full count item but not end of scan signal received from end of scan decoder 78 (FIG. 3) as previously described.

The end-of-character decryption device 84 of FIG. 3 is shown in detail in FIG. The task of the end-of-character decoder is to determine whether the end of the character is present and to inform the computer that new character information (starting with the first and second byte of a new character) can be entered into the input register 50 (FIG. 3). In addition, the end-of-character decoder generates a signal telling the scan addressing controls when the count item is which is completed to be the first count item of the scan.

The switch which indicates the first item is switch 260, which is set by the end of scan transmission signal or the reset start signal. That

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End of scan signal, which corresponds to a signal at the beginning of the next scan, is normally used to set the switch 26O ₁ which indicates the first item. When the switch indicating the first item is set, the AND circuit 262 is free. The AND circuit 262 remains free as long as the switch 260 is set. The switch 260 remains set until the first signal for scan addressing change comes and resets the switch. This signal for scan addressing change comes for the first time at the end of the first scan item or count value item.

If this first scan item or count item contains an end-of-scan flag, the end-of-scan signal is received and is passed by AND circuit 262. The output of the AND circuit 262 is the signal for end of character This signal is fed back to the operating mode control and is also fed to the computer. When the calculator receives the signal for the end of the character, he knows that the data expansion system can now accept the data for the next character. Alternatively, the above can be seen as the detection of an identifier bit for "full count operation, end of scan" during the consider the first sample item of a sample.

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Claims (11)

PA TENT CLAIMS Process for the compression and decompression of digitally coded data for graphic signs, which are formed by delimiting black and white sub-areas within a coordinate network, thereby characterized in that the number of the same type in succession within a column or row of the coordinate network a sub-area resulting coordinate network basic elements is recorded as a full count value and then a compression of the full count | values is carried out in such a way that, by comparing the full count values, in each case two adjacent columns or rows of the same type Sub-areas only the difference of which is registered as a difference count and that with a decreasing change in the number of sample items from column to column or row to line, the last sample item as the full count value is registered and that with increasing changes in the number of sampling posts from column to column or row to row, the last sampling post, which corresponds to that in the adjacent column or row, and all subsequent sample items in a column or row as full count values are registered and that when the compressed data is decompressed, the full count values, if they do not appear explicitly, are signed Accurate, cumulative addition of differential counts of corresponding sub-areas that are adjacent in columns or rows to form an original full count to be determined. 2. The method according to claim 1, characterized in that at strong Change of the difference count of a scanning item of this, as well as all subsequent scanning items for a column or line scan are registered as full counts. 3. The method according to any one of claims 1-2, characterized in that in the case of column-by-column scanning for registering the compressed data, a binary code for byte-oriented storage with the following 209820/0796 Docket BO 968 017 Indicator is used: a) A binary "1" in the first bit of the first byte indicates free Ending columns within the coordinate network before the beginning of the Character and entails the specification of the number of free columns in dual-encrypted form in the second byte. A binary "0" in the first bit of the first byte indicates that there are no free columns are available. ^ b) The second and third bits of the first byte contain an encrypted code rare assignment for the bit length of possible full count values. It means: 00 5 bits + 1 bit (IO bit) for identification the end of a column-by-column scan 01 6 bits + 1 bit (IO bit) for identification the end of a column-by-column scan 10 7 bits + 1 bit (IO bit) for identification the end of a column-by-column scan 11 8 bits + 1 bit (IO bit) for identification the end of a column-by-column scan. In contrast to a binary "0", there is a binary "1" in the EA bit the end of a column-by-column scan. c) After a binary "1" in the EA bit, the first item for the The following column-by-column scanning is given as a difference count, the size of the difference count being given by the number of binary Zeros are indicated by two binary "l" s are included. Two binary ^H l "at the beginning of -sen Differenzzählwertes be a change in sign compared to the previous corresponding to Abtastposten. A binary ¹¹ O" indicates that it is the same difference count value as the corresponding previous ones. 209820/0796 Docket BO 968 017 d) Three binary "I" s indicate the transition from differential counting operation on full count operation. 4. Arrangement for carrying out the method according to claim 3, characterized in that for decompression of the code information an input register (50) receiving the compressed data byte by byte with a series output, a parallel output and one with a decryption circuit (52) for the bit length of the full count values output connected \ that a cyclically working memory (56) for receiving the Vollzählwerte and decompressed to Vollzählwerten Differnzzählwerte with downstream buffer register (68), that for data input into the memory (56) a with a full or Operating mode control (60) connected to the first gate circuit (62) which determines the difference counting value mode, that a circuit (70) for the cumulative determination of the full count values from the difference counts, that a second gate circuit (54) through which the parallel output of the Input register (50) for the remaining free columns within the Coordinate network before the beginning of the sign corresponding conditions I can be connected to the memory (56), that for addressing the memory locations address control circuits (74) are provided and that the series output of the input register (50) is connected to the gate circuit (62), which via the decryption circuit (52) can be set for the full count length. 5. Arrangement according to claim 4, characterized in that with full count value operation the series output of the input register (50) via the gate circuit (62) is connected to the memory (56) in such a way that the storage of the full count value bit by bit and in the course of n-1 (n = length of the full number value) takes place in successive circulation cycles, whereby during each circulation cycle the ready in the memory (56) over- 209820/0796 carried k-bit values (k: 1 ..., n-1) via the buffer register (68) read out and together with the (K + 1). Bit value can be rewritten into the memory via the gate circuit (62). 6. Arrangement according to claim 4, characterized in that if there is a difference count operation a previous full count item from memory via the buffer register (68) and a subsequent difference count the circuit (70) for the cumulative determination of the full count values ■ the difference count values can be supplied and that the determined full count value Your memory (56) can be supplied again via the gate circuit (62). 7. Arrangement according to one of claims 4 to 6, characterized in that that after decryption and completion of the samples the same in the memory (56) as part of a transmission cycle the buffer register (68) and the gate circuit (62) in a write memory area of the memory (56) can be received. 8. Arrangement according to claim 7, characterized in that when retrieved from decompressed scan posts for controlling output units of ρ the memory controller, a signal can be generated by which the desired Sampling post via a gate circuit (72) from the write memory area of the memory (56) can be transferred to the output units and that during this time the completion of count values or the transmission cycle of completed data in the write memory area dee memory (56) is interruptible. 9. The arrangement according to claim 4, characterized in that by the address control circuits (74) connected to the memory (56) for the cyclical completion of the deferred items in the memory (56), subsequent addresses can be generated. 209820/0798 10. Arrangement according to claim 9, characterized in that successive Scan items are stored in the memory (56) at successive addresses. 11. The arrangement according to claim 4, characterized in that in the circuit (70) for the cumulative determination of the full count values from the difference count values a logic counting circuit using polarity hold circuits (2 3 5, 2 4 4, etc.) for the between two binary ones Ones enclosed binary zeros is provided and that the sign of the counting process can be derived via an antivalence element. 209820/0796 Docket BO 968 017 Blank page