JPS63192268A - Manufacture of c-mos semiconductor integrated circuit - Google Patents
Manufacture of c-mos semiconductor integrated circuitInfo
- Publication number
- JPS63192268A JPS63192268A JP62025752A JP2575287A JPS63192268A JP S63192268 A JPS63192268 A JP S63192268A JP 62025752 A JP62025752 A JP 62025752A JP 2575287 A JP2575287 A JP 2575287A JP S63192268 A JPS63192268 A JP S63192268A
- Authority
- JP
- Japan
- Prior art keywords
- channel stopper
- well region
- impurity ions
- region
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 3
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 230000001133 acceleration Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
Description
【発明の詳細な説明】
［概要］
ウェル領域およびチャネルストッパー領域の形成方法に
おいて、チャネルストッパー領域上にウェル領域上より
も厚い膜厚のマスクを形成し、そのマスクを透過させて
不純物イオンを両頭域に同時に注入し、その注入イオン
の加速電圧を時間と共に減少させ、且つ、不純物イオン
のドープ量は初期に少なく、中期に多く、終期に少なく
なるように注入する。そうすれば、ウェル領域とチャネ
ルストッパー領域とが同時に形成されて、製造工程が短
縮される。Detailed Description of the Invention [Summary] In a method for forming a well region and a channel stopper region, a mask having a thickness thicker than that on the well region is formed on the channel stopper region, and the impurity ions are transmitted through the mask. The accelerating voltage of the implanted ions is decreased over time, and the doping amount of impurity ions is small at the beginning, large at the middle, and small at the end. This allows the well region and channel stopper region to be formed at the same time, thereby shortening the manufacturing process.
［産業上の利用分野コ
本発明はＣ−ＭＯＳ半導体集積回路の製造方法に係り、
そのうち、新規なウェル領域およびチャネルストッパー
領域の形成方法に関する。[Industrial Field of Application] The present invention relates to a method for manufacturing a C-MOS semiconductor integrated circuit,
Among them, the present invention relates to a novel method for forming a well region and a channel stopper region.
最近、Ｃ−ＭＯ５）ランジスタ（相補型モストランジス
タ）からなる半導体集積回路（ＩＣ）の需要が増大して
お°す、これは消費電力が少ない利点があるからである
。また、その他に、Ｃ−ＭＯＳＩＣは回路の動作余裕が
大きい等のメリットがあって、ＬＳＩゲートアレーやメ
モリの主流となつている。Recently, the demand for semiconductor integrated circuits (ICs) made of C-MO5) transistors (complementary MOS transistors) has been increasing because they have the advantage of low power consumption. In addition, C-MOSIC has other merits such as a large margin for circuit operation, and has become the mainstream for LSI gate arrays and memories.
このように高度に集積化されつつあるＣ−ＭＯＳＩＣで
あるが、その製造工程は可能な限りに簡易なことが望ま
しい。Although C-MOSICs are becoming highly integrated, it is desirable that their manufacturing process be as simple as possible.
［従来の技術と発明が解決しようとする問題点コ第３図
はＣ−ＭＯＳＩＣを構成するＣ−ＭＯＳトランジスタの
概要図を示しており、１はｎ型半導体基板、２はｐ型ウ
ェル領域、３はｐチャネル、トランジスタ、４はｎチャ
ネルトランジスタ、５はｐ＋型チャネルストッパー領域
である。[Problems to be solved by the prior art and the invention] Figure 3 shows a schematic diagram of a C-MOS transistor constituting a C-MOSIC, in which 1 is an n-type semiconductor substrate, 2 is a p-type well region, 3 is a p-channel transistor, 4 is an n-channel transistor, and 5 is a p+ type channel stopper region.
従来、Ｃ−ＭＯＳトランジスタを形成する場合、初期に
、半導体基板にウェル領域およびチャネルストッパー領
域を形成しており、その工程断面図を第３図（ａ）、
（ｂ）に示している。Conventionally, when forming a C-MOS transistor, a well region and a channel stopper region are initially formed on a semiconductor substrate, and a cross-sectional view of the process is shown in FIG.
Shown in (b).
まず、第３図（ａ）に示すように、５ｉ０２ （酸化
シリコン）膜６をマスクにして、硼素（Ｂ）イオンを加
速電圧１６０〜１８０ＫｅＶ、 ドーズ量ｌＸｌ０／
ｃｄにして注入し、次いで、１２００℃、３〜４時間の
熱処理をおこなって、ｐ型ウェル領域２を画定する。First, as shown in FIG. 3(a), using the 5i02 (silicon oxide) film 6 as a mask, boron (B) ions are heated at an acceleration voltage of 160 to 180 KeV and a dose of lXl0/
CD and then heat-treated at 1200° C. for 3 to 4 hours to define the p-type well region 2.
次いで、°同図（ｂ）に示すように、５ｉ０２膜６のマ
スクを除去し、代わりに、新たな５ｉ０２膜７のマスク
を設けて、加速電圧数十ＫｅＶ 、 ドーズ量は上記
と同程度にして硼素イオンを注入し、熱処理して、ｐ＋
型チャネルストッパー領域５を画定する。なお、マスク
は５ｉ０２膜に限るものでなく、レジスト膜マスクも使
用される。Next, as shown in the same figure (b), the mask of the 5i02 film 6 was removed and a new mask of the 5i02 film 7 was provided in its place, and the acceleration voltage was set to several tens of KeV and the dose was set to the same level as above. After implanting boron ions and heat treatment, p+
A mold channel stopper region 5 is defined. Note that the mask is not limited to the 5i02 film, and a resist film mask may also be used.
このように、従来の形成方法はウェル領域とチャネルス
トッパー領域とは別々のイオン注入をおこない、２回の
マスクを形成し、２回のイオン注入によって作製してい
る。As described above, in the conventional formation method, the well region and the channel stopper region are manufactured by performing separate ion implantations, forming two masks, and performing two ion implantations.
且つ、ウェル領域を形成する場合、上記のように長時間
の熱処理をおこなう理由は、その深さを４μｍ程度まで
深くしてラッチアップ（寄生ｎｐｎｐサイリスタ動作）
を抑制するためで、また、ｐ＋型チャネルストッパー領
域５をウェル領域の周囲に設ける理由もラッチアップを
抑制するためと、表面のリーク電流をなくするためであ
る。このラフチアツブの抑制はＣ−ＭＯＳ トランジス
タ特有の問題点であり、濃度が濃＜、深さが深いほど良
いとされている。In addition, when forming a well region, the reason for performing long-time heat treatment as described above is to increase the depth to about 4 μm to prevent latch-up (parasitic npnp thyristor operation).
In addition, the reason why the p+ type channel stopper region 5 is provided around the well region is to suppress latch-up and to eliminate surface leakage current. Suppression of this rough rise is a problem specific to C-MOS transistors, and it is said that the higher the concentration and the deeper the depth, the better.
ところで、上記のように同じ不純物イオンを２回に別け
て注入することは、それだけ製造工程が増加することと
なり、コストダウンの面から決して好ましいことではな
い。However, implanting the same impurity ions twice as described above increases the number of manufacturing steps, which is not at all preferable from the standpoint of cost reduction.
従って、本発明はこれらウェル領域とチャネルストッパ
ー領域とを同時に形成する製造方法を提案するものであ
る。Therefore, the present invention proposes a manufacturing method for forming these well regions and channel stopper regions at the same time.
［問題点を解決するための手段］
その目的は、チャネルストッパー領域上に不純物イオン
の透過を阻害するマスクを形成し、該ウェル領域と該マ
スクを透過させてチャネルストッパー領域とに同時に異
種導電型不純物イオンを注入して、且つ、該異種導電型
不純物イオンの加速電圧を時間と共に減少させ、更に、
不純物イオンのドープ量が初期に少なく、中期に多く、
更に、終期に少なくなるように調整して注入する工程が
含まれる製造方法によって達成される。[Means for solving the problem] The purpose is to form a mask on the channel stopper region that inhibits the transmission of impurity ions, and to transmit impurity ions into the well region and the channel stopper region at the same time. implanting impurity ions, and reducing the acceleration voltage of the impurity ions of different conductivity type over time;
The doping amount of impurity ions is small in the early stage and large in the middle stage,
Furthermore, this is achieved by a manufacturing method that includes a step of adjusting and injecting so that the amount decreases at the final stage.
［作用］
即ち、本発明は、チャネルストッパー領域上にウェル領
域上よりも厚い膜厚のマスクを形成し、そのマスクを透
過させて、チャネルストッパー領域とウェル領域とに同
時に不純物イオンを注入し、その注入イオンの加速電圧
を時間経過と共に減少させ、且つ、不純物イオンのドー
プ量は初期に少なく、中期に多く、終期に少なくなるよ
うに注入する。そうすれば、１回のマスクとイオン注入
によって、円領域が同時に形成できる。[Operation] That is, in the present invention, a mask is formed on the channel stopper region to be thicker than that on the well region, and impurity ions are implanted into the channel stopper region and the well region at the same time through the mask. The acceleration voltage of the implanted ions is decreased over time, and the implantation is performed so that the amount of impurity ions doped is small at the beginning, large at the middle stage, and small at the final stage. In this way, circular regions can be formed at the same time by one mask and ion implantation.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかるウェル領域とチャネルストッパ
ー領域との形成方法を示している。ｎ型半導体基板１１
上に５ｉ０２膜を形成し、その５ｉ０２膜１６のパター
ンはチャネルストッパー領域形成部分上の５ｉ０２膜１
６”を膜厚５００〜１０００人程度に薄くし形成の部分
の５ｉ０２膜の膜厚はｌ１１ｍ程度に厚く形成する。ま
た、ウェル開城はマスクせずに露出させておく。そうし
て、最初に、硼素イオン注入の加速電圧を数百Ｋｅν（
５００ＫｅＶ〜Ｉ ＭｅＶ ）として、それより時間と
共に減少させ、最後に数十ＫｅＶから百ＫｅＶ程度にま
で低下させる。また、ドーズ量は、最初に１０”−Ｆａ
ｄ程度と少なくし、次に、１０１５／Ｃ１１程度と多く
し、終わりにｌ Ｑ ”−”／ ｃＡ程度と少なくする
。FIG. 1 shows a method of forming a well region and a channel stopper region according to the present invention. n-type semiconductor substrate 11
A 5i02 film 16 is formed on the 5i02 film 16, and the pattern of the 5i02 film 16 is similar to that of the 5i02 film 1 on the channel stopper region forming part.
6" to a film thickness of about 500 to 1000 m, and the 5i02 film in the formed part is thickened to about 11 m. Also, the well opening is left exposed without masking. Then, first , the acceleration voltage for boron ion implantation is set to several hundred Keν (
500 KeV to I MeV), then it is decreased over time, and finally it is lowered from several tens of KeV to about 100 KeV. In addition, the dose amount was initially 10”-Fa.
Decrease it to about d, then increase it to about 1015/C11, and finally decrease it to about lQ "-"/cA.
次いで、熱処理は短時間のランプアニールをおこなう。Next, the heat treatment includes short-time lamp annealing.
そうすると、ウェル領域の深さが４μｍから２．５回ｍ
程度まで（下層１２Ｌ）は濃度が１０′７〜Ｉｔ／ ｃ
ｄとなり、深さが２．５μｍから１μｍ近辺まで（中層
１２Ｍ）は濃度が１０ ／ｃｕｔと高濃度になり、１
μｍ近辺から表面まで（上Ｆ！１２Ｌ）は濃度が１０Ｉ
ワ〜１８
／ｄになったｐ型ウェル９■域１２が形成される。Then, the depth of the well region is 2.5 times m from 4 μm.
(lower layer 12L) has a concentration of 10'7 to It/c
d, and from a depth of 2.5 μm to around 1 μm (middle layer 12M), the concentration is as high as 10 /cut, and 1
From the vicinity of μm to the surface (upper F! 12L), the concentration is 10I
A p-type well 9 region 12 having a diameter of 18/d is formed.
同時に、チャネルストッパー領域１５は深さが２μｍか
ら１μｍ程度まで（下層１５Ｌ）の濃度が１０””ＩＦ
Ｉ／ｃ１１と薄く、１μｍ近辺から表面まで（上Ｊｉ１
５Ｕ）の濃度が１０ ／ｃｄと濃（なる。At the same time, the channel stopper region 15 has a concentration of 10''IF from a depth of about 2 μm to about 1 μm (lower layer 15L).
Thin I/c11, from around 1μm to the surface (upper Ji1
The concentration of 5U) is as high as 10/cd.
この注入イオンの濃度と深さの関係を第２図に示してお
り、縦軸は硼素の濃度、横軸は深さで、曲線Ａはウェル
領域の深さと濃度の曲線９曲線Ｂはチャネルスト−／パ
ー領域の深さと濃度の曲線である。The relationship between the concentration and depth of this implanted ion is shown in Figure 2, where the vertical axis is the boron concentration and the horizontal axis is the depth.Curve A is the depth and concentration curve of the well region.Curve B is the channel strain. This is a curve of depth and concentration in the −/par region.
図のように、ウェル領域とチャネルストッパー領域との
注入状態が相異するのは、チャネルストッパー領域上の
５ｉ０２膜１６°によってイオン注入が妨げられ、ウェ
ル領域には深く、チャネルストッパー領域には浅く注入
されるからである。As shown in the figure, the reason why the implantation conditions in the well region and the channel stopper region are different is that ion implantation is blocked by the 5i02 film 16° on the channel stopper region, and the implantation is deep in the well region and shallow in the channel stopper region. This is because it is injected.
従って、本発明によれば、ウェル領域とチャネルストッ
パー領域とが同時に形成でき、且つ、ウェル領域は深さ
方向の中央部分に濃度の高い層が形成される。そのため
に、次工程でウェル領域にｎ型のソース・ドレインを形
成すると、ソース・ドレイン領域の底面が高濃度なウェ
ル領域に接することになり、ラッチアップが抑制される
効果も得られる。Therefore, according to the present invention, a well region and a channel stopper region can be formed at the same time, and a layer with a high concentration is formed in the central portion of the well region in the depth direction. For this reason, when an n-type source/drain is formed in the well region in the next step, the bottom surface of the source/drain region comes into contact with the highly doped well region, which also has the effect of suppressing latch-up.
上記はウェル領域面を露出させた実施例で説明したが、
ウェル領域上に薄いＳｉＯ□膜を被覆し、更に、チャネ
ルストッパー領域上にそれより厚く、且つ、注入イオン
を透過できる５ｉ０２膜を形成しても良い。The above was explained using an example in which the well region surface was exposed.
A thin SiO□ film may be coated on the well region, and a 5i02 film which is thicker than the thin SiO□ film and is permeable to the implanted ions may be formed on the channel stopper region.
更に、上記例はｐ型のウェル領域・チャネルストッパー
領域の形成方法で説明したが、ｎ型ウェル領域の形成方
法にも適用できるものである。Furthermore, although the above example has been explained as a method for forming a p-type well region/channel stopper region, it can also be applied to a method for forming an n-type well region.
［発明の効果］
以上の説明から明らかなように、本発明にかかる形成方
法によれば、１回のイオン注入法によりウェル領域とチ
ャネルストッパー領域とが同時に形成され、且つ、ラッ
チアップが抑制される効果も得られて、Ｃ−ＭＯＳ Ｉ
Ｃのコストダウンと信軽性向上に著しく役立つもので
ある。[Effects of the Invention] As is clear from the above description, according to the formation method according to the present invention, a well region and a channel stopper region are simultaneously formed by a single ion implantation method, and latch-up is suppressed. C-MOS I
This is extremely useful for reducing C costs and improving reliability.
第１図は本発明にかかるウェル領域とチャネルストッパ
ー領域の形成方法を示す図、
第２図は本発明にかかる注入イオンの濃度と深さとの関
係を示す図、
第３図はＣ−ＭＯＳトランジスタの概要図、第４図（ａ
）、 （ｂ）は従来のウェル領域とチャネルストッパー
領域の形成方法を示す図である。
図において、
１．１１は半導体基板、
２．１２はｐ型ウェル領域、
３はｐチャネルトランジスタ、
４はｎチャネルトランジスタ、
５．１５はチャネルストッパー領域、
６．７．１６は５ｉ０２膜、
１２Ｕはウェル領域の上層、
１２Ｍはウェル領域の中層、
１２１、はウェル領域の下層、
１５Ｕはチャネルストッパー領域の上層、１５Ｌはチャ
ネルストッパー領域の下層、１６’はチャネルストッパ
ー領域上の薄い５ｉ０２膜を示している。
第１図
□チマ
シｔフしイ；ｔ＞ｑΔにＡしｔンデれのｎり（釈ｅ＄Ｔ
ｒｉ）第２図
Ｃ−Ｆ−１０５Ｌう〉）°スタ＾召１宇イＴ第３図
の形へ゛１ｆ壜を不７の
第４図FIG. 1 is a diagram showing a method for forming a well region and a channel stopper region according to the present invention, FIG. 2 is a diagram showing the relationship between implanted ion concentration and depth according to the present invention, and FIG. 3 is a diagram showing a C-MOS transistor. Schematic diagram of Figure 4 (a
) and (b) are diagrams showing a conventional method of forming a well region and a channel stopper region. In the figure, 1.11 is a semiconductor substrate, 2.12 is a p-type well region, 3 is a p-channel transistor, 4 is an n-channel transistor, 5.15 is a channel stopper region, 6.7.16 is a 5i02 film, and 12U is a The upper layer of the well region, 12M is the middle layer of the well region, 121 is the lower layer of the well region, 15U is the upper layer of the channel stopper region, 15L is the lower layer of the channel stopper region, and 16' is the thin 5i02 film on the channel stopper region. There is. Fig. 1 □ It is difficult to move;
ri) Figure 2 C-F-105L〉) ° Place the 1f bottle into the shape shown in Figure 3. Figure 4
Claims (1)
て異種導電型のウェル領域とチャネルストッパー領域と
を形成する製造工程において、チャネルストッパー領域
上に不純物イオンの透過を阻害するマスクを形成し、該
ウェル領域と該マスクを透過させてチャネルストッパー
領域とに同時に異種導電型不純物イオンを注入し、且つ
、該異種導電型不純物イオンの加速電圧を時間と共に減
少させ、更に、不純物イオンのドープ量が初期に少なく
、中期に多く、更に、終期に少なくなるように調整して
注入する工程が含まれてなることを特徴とするＣ−ＭＯ
Ｓ半導体集積回路の製造方法In the manufacturing process of implanting impurity ions of a different conductivity type into a semiconductor substrate of one conductivity type to form a well region and a channel stopper region of different conductivity types, a mask is formed on the channel stopper region to inhibit transmission of impurity ions, Impurity ions of different conductivity type are simultaneously implanted into the well region and the channel stopper region through the mask, and the accelerating voltage of the impurity ions of the different conductivity type is decreased over time, and further, the doping amount of the impurity ions is reduced. A C-MO characterized by comprising a step of adjusting and injecting so that the amount is small in the initial stage, large in the middle stage, and further reduced in the final stage.
S semiconductor integrated circuit manufacturing method
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62025752A JPS63192268A (en) | 1987-02-05 | 1987-02-05 | Manufacture of c-mos semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62025752A JPS63192268A (en) | 1987-02-05 | 1987-02-05 | Manufacture of c-mos semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63192268A true JPS63192268A (en) | 1988-08-09 |
Family
ID=12174564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62025752A Pending JPS63192268A (en) | 1987-02-05 | 1987-02-05 | Manufacture of c-mos semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63192268A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0227760A (en) * | 1988-07-15 | 1990-01-30 | Sony Corp | Manufacture of semiconductor device |
| JPH0296364A (en) * | 1988-09-30 | 1990-04-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5141882A (en) * | 1989-04-05 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor |
| US5545911A (en) * | 1993-12-17 | 1996-08-13 | Nec Corporation | Semiconductor device having mosfets formed in inherent and well regions of a semiconductor substrate |
| US11124061B2 (en) | 2018-06-15 | 2021-09-21 | Honda Motor Co., Ltd. | Tank cap structure and saddle-type vehicle |
-
1987
- 1987-02-05 JP JP62025752A patent/JPS63192268A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0227760A (en) * | 1988-07-15 | 1990-01-30 | Sony Corp | Manufacture of semiconductor device |
| JPH0296364A (en) * | 1988-09-30 | 1990-04-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5141882A (en) * | 1989-04-05 | 1992-08-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor |
| US5545911A (en) * | 1993-12-17 | 1996-08-13 | Nec Corporation | Semiconductor device having mosfets formed in inherent and well regions of a semiconductor substrate |
| US11124061B2 (en) | 2018-06-15 | 2021-09-21 | Honda Motor Co., Ltd. | Tank cap structure and saddle-type vehicle |
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