JPS63190426A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- JPS63190426A JPS63190426A JP62023033A JP2303387A JPS63190426A JP S63190426 A JPS63190426 A JP S63190426A JP 62023033 A JP62023033 A JP 62023033A JP 2303387 A JP2303387 A JP 2303387A JP S63190426 A JPS63190426 A JP S63190426A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- controlled oscillator
- synchronization
- output
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims abstract description 16
- 238000011084 recovery Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は周波数シンセサイザなどに用いる位相同期回路
に関するものである。っ
従来の技術
従来の位相同期口、＠は、第４図に示すような構成であ
った。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase locked circuit used in frequency synthesizers and the like. BACKGROUND OF THE INVENTION A conventional phase synchronization port has a configuration as shown in FIG.
すなわち入力端子１に加えられる入力信号と電圧制御発
振器２の出力を位相比較器３により位相比較し、前記位
相比較器３の出力をループフィルタ４に入力し、前記ル
ープフィルタ４の出力を前記電圧制御発振器２に入力し
てループを構成し、入力信号に位相が同期した出力信号
を前記電圧制御発振器２の出力端子から得ていた。That is, the input signal applied to the input terminal 1 and the output of the voltage controlled oscillator 2 are phase-compared by the phase comparator 3, the output of the phase comparator 3 is input to the loop filter 4, and the output of the loop filter 4 is compared to the voltage controlled oscillator 2. The voltage controlled oscillator 2 is inputted to form a loop, and an output signal whose phase is synchronized with the input signal is obtained from the output terminal of the voltage controlled oscillator 2.
発明が解決しようとする問題点
しかし、このような構成のものでは同期が外れた場合、
同期の復帰が困難であったり、時間がかかるという問題
があった。Problems to be solved by the invention However, with this configuration, if synchronization is lost,
There were problems in that it was difficult to restore synchronization and it took a long time.
本発明はこのような問題を解決するもので、同期の回復
を容易にすることを目的とする。The present invention solves such problems and aims to facilitate recovery of synchronization.
問題点を解決するための手段
上記問題点を解決する本発明の技術的な手段は、同期が
外れたときＯＶから電源電圧まで徐々に変化する電圧を
前記電圧制御発振器の制御電圧として、前記電圧制御発
振器の入力端子に印加するものである。Means for Solving the Problems The technical means of the present invention for solving the above problems is to use a voltage that gradually changes from OV to the power supply voltage when synchronization is lost as the control voltage of the voltage controlled oscillator. This is applied to the input terminal of the controlled oscillator.
作用 この技術的手段による作用は次のようになる。action The effect of this technical means is as follows.
すなわち、同期状態では入力信号と電圧制御発振器の出
力との位相差を位相比較器で検出し、ループフィルタを
介して前記電圧制御発振器にフィードバックされ、入力
信号に位相が同期した出力信号が得られる。That is, in the synchronous state, the phase difference between the input signal and the output of the voltage controlled oscillator is detected by a phase comparator and fed back to the voltage controlled oscillator via the loop filter, thereby obtaining an output signal whose phase is synchronized with the input signal. .
また同期が外れた状態では、前記電圧制御発振器の制御
電圧がＯＶから電源電圧まで徐々に変化するため、必ず
同期状態のときの電圧になるときがあり、その後は短時
間に同期が確立する。Furthermore, in an out-of-synchronization state, the control voltage of the voltage-controlled oscillator gradually changes from OV to the power supply voltage, so there are times when the voltage is always the same as in the synchronized state, and then synchronization is established in a short time.
この結果、同期が外れても容易に復帰することができる
。As a result, even if synchronization is lost, recovery can be easily achieved.
実施例
本発明の一実施例を第１図に示す。３は位相比較器で、
入力端子１に加えられる入力信号と電圧制御発振器２の
出力との位相差を検出する。４ｔｒｉループフイルタで
、前記位相比較器３の出力より直流信号を得る。６は同
期検出器で、本発明による位相同期回路が同期状態であ
るかないかを検出する。７は電圧発生器で、同期検出器
６が同期状態でないことを検出したとき、ｏＶから電源
電圧まで徐々に変化する電圧を発生する。８はスイッチ
で、同期検出回路の出力により同期状態ではａ側に、非
同期状態ではｂ側に切替えられる。Embodiment An embodiment of the present invention is shown in FIG. 3 is a phase comparator,
The phase difference between the input signal applied to input terminal 1 and the output of voltage controlled oscillator 2 is detected. A DC signal is obtained from the output of the phase comparator 3 using a 4-tri loop filter. 6 is a synchronization detector which detects whether the phase synchronization circuit according to the present invention is in a synchronized state or not. A voltage generator 7 generates a voltage that gradually changes from oV to the power supply voltage when the synchronization detector 6 detects that the synchronization detector 6 is not in a synchronized state. 8 is a switch which is switched to the a side in a synchronous state and to the b side in an asynchronous state by the output of the synchronization detection circuit.
第２図は本発明に用いられる電圧発生器７の一例である
。９は入力端子、１ｏは電源電圧、１１はトランジスタ
、１２．１４は抵抗器、１３はコンデンサ、１６は出力
端子である。抵抗器１４の抵抗値Ｒ２は抵抗器１２の抵
抗値Ｒ１よシ十分大きい。FIG. 2 shows an example of the voltage generator 7 used in the present invention. 9 is an input terminal, 1o is a power supply voltage, 11 is a transistor, 12.14 is a resistor, 13 is a capacitor, and 16 is an output terminal. The resistance value R2 of the resistor 14 is sufficiently larger than the resistance value R1 of the resistor 12.
第３図は本発明に用いられる同期検出回路６の一例であ
る。１６は入力端子、１ア、２０，２１゜２３は抵抗器
、１８はダイオード、１９はコンデンサ、２２は電圧比
較器、２４は電源電圧、２６は出力端子である。FIG. 3 shows an example of the synchronization detection circuit 6 used in the present invention. 16 is an input terminal, 1A, 20, 21, 23 is a resistor, 18 is a diode, 19 is a capacitor, 22 is a voltage comparator, 24 is a power supply voltage, and 26 is an output terminal.
つぎに動作を説明する。まず、位相同期回路が同期状態
にあるとき、同期検出器６ｉｌ′ｉ同期状態を検出する
、すなわち同期状態であるので電圧制御発振器２の出力
レベルは高く、第３図の入力端子１６に印加される電圧
も高い。抵抗器１７，２０゜ダイオード１８、コンデン
サ１９で構成される振幅検波回路により高い直流電圧が
得られる。前記直流電圧と、抵抗器２３．２１で決まる
基準電圧を電圧比較器２２で比較し、出力端子２５には
ローレベルを得る。Next, the operation will be explained. First, when the phase-locked circuit is in the synchronous state, the synchronous detector 6il'i detects the synchronous state; in other words, since it is in the synchronous state, the output level of the voltage controlled oscillator 2 is high and is applied to the input terminal 16 in FIG. The voltage applied is also high. A high DC voltage can be obtained by an amplitude detection circuit composed of a resistor 17, a 20° diode 18, and a capacitor 19. A voltage comparator 22 compares the DC voltage with a reference voltage determined by a resistor 23, 21, and a low level is obtained at an output terminal 25.
したがってスイッチ８はａ側のままであり、ループフィ
ルタ４の出力電圧ＶＴｏが電圧制御発振器２に入力され
る。一方第２図の入力端子９はローレベルとなり、トラ
ンジスタ１１はＯＦＦとなり、出力端子１６はＯｖとな
る。Therefore, the switch 8 remains on the a side, and the output voltage VTo of the loop filter 4 is input to the voltage controlled oscillator 2. On the other hand, the input terminal 9 in FIG. 2 is at a low level, the transistor 11 is turned off, and the output terminal 16 is at Ov.
つぎに位相同期回路の同期が外れたとき、同期検出器６
は非同期状態を検出する。すなわち同期が外れているの
で、電圧制御発振器２の出力レベルは低く、第３図の入
力端子１６に印加される電圧も低い。抵抗器１７．２０
、ダイオード１８、コンデンサ１９で構成される振幅検
波回路により低い直流電圧が得られる。前記直流電圧と
、抵抗器２３．２１で決まる基準電圧を電圧比較器２２
で比較し、出力端子２６にはハイレベルを得る。Next, when the phase synchronization circuit loses synchronization, the synchronization detector 6
detects an out-of-sync condition. That is, since the synchronization is out of synchronization, the output level of the voltage controlled oscillator 2 is low, and the voltage applied to the input terminal 16 in FIG. 3 is also low. Resistor 17.20
, a diode 18, and a capacitor 19, a low DC voltage can be obtained by the amplitude detection circuit. The voltage comparator 22 converts the DC voltage and the reference voltage determined by the resistors 23 and 21.
A high level is obtained at the output terminal 26.
したがってスイッチ８はｂ側に切替る。一方第２図の入
力端子９はハイレベルとなシ、トランジスタ１１はＯＮ
となり、出力端子１６に生じる電圧Ｅは電源電圧２４を
Ｖ。、時間をｔとすれば””Ｖｏ （１−、−ｔ／ＣＲ
１）
となる。ここでＣＲ１を大きくとれば電圧ＥはＯＶから
Ｖ。まで徐々に変化する。このように電圧制御発振器２
にはｏＶから電源電圧まで徐々に変化する電圧が制御電
圧として印加される。制御電圧がＯｖから電源電圧まで
変化している場合、制御電圧がＶＴｏになったとき電圧
制御発振器２の出力レベルは高くなり、同期検出器６の
出力はローレベルになり、スイッチ８はａ側に切替る。Therefore, the switch 8 is switched to the b side. On the other hand, the input terminal 9 in Fig. 2 is not at a high level, and the transistor 11 is ON.
Therefore, the voltage E generated at the output terminal 16 is equal to the power supply voltage 24 by V. , if time is t, then ""Vo (1-, -t/CR
1) becomes. Here, if CR1 is set large, the voltage E will go from OV to V. gradually change. In this way, the voltage controlled oscillator 2
A voltage that gradually changes from oV to the power supply voltage is applied as a control voltage. When the control voltage is changing from Ov to the power supply voltage, when the control voltage reaches VTo, the output level of the voltage controlled oscillator 2 becomes high, the output of the synchronous detector 6 becomes low level, and the switch 8 is set to the a side. Switch to.
したがってループフィルタ４の出力である直流電圧が電
圧制御発振器２に入力され、全体としてフィードバック
がかかり、短時間に出力端子５には入力信号の位相に同
期した信号が得られる。Therefore, the DC voltage that is the output of the loop filter 4 is input to the voltage controlled oscillator 2, and feedback is applied to the entire system, so that a signal synchronized with the phase of the input signal is obtained at the output terminal 5 in a short time.
発明の効果
以上のように本発明によれば、同期の回復が容易になり
、実用上きわめて有用である１、Effects of the Invention As described above, according to the present invention, synchronization can be easily restored, which is extremely useful in practice1.
第１図は本発明の一実施例における位相制御回路を示す
ブロック図、第２図は本発明に用いる電圧発生器の一例
を示す回路図、第３図は本発明に用いる同期検出器の一
例を示す回路図、第４図は従来の位相同期回路のブロッ
ク図である。
１・・・・・・入力端子、２・・・ 電圧制御発掘器、
３・・・・・・位相検出器、４・・・・・・ループフィ
ルタ、６・・・・・出力端子、６・・・・・同期検出器
、７・・・・・・電圧発生器、８・・・・・・スイッチ
。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名区
イ
第２図
第３図
区 Ｒ
イ
＼ｒFIG. 1 is a block diagram showing a phase control circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a voltage generator used in the present invention, and FIG. 3 is an example of a synchronous detector used in the present invention. FIG. 4 is a block diagram of a conventional phase locked circuit. 1... Input terminal, 2... Voltage control excavator,
3...Phase detector, 4...Loop filter, 6...Output terminal, 6...Synchronization detector, 7...Voltage generator , 8... switch. Name of agent: Patent attorney Toshio Nakao and 1 other person
A Figure 2 Figure 3 Section R I\r
Claims (1)
もに、その位相比較した出力をループフィルタに入力し
、同期状態では前記ループフィルタの出力を前記電圧制
御発振器の制御電圧として前記電圧制御発振器の入力端
子に印加し、同期外れ状態ではＯＶから電源電圧まで徐
々に変化する電圧を前記電圧制御発振器の制御電圧とし
て前記電圧制御発振器の入力端子に印加し、前記電圧制
御発振器の出力端子から出力信号を得るように構成した
位相同期回路。The input signal and the output of the voltage controlled oscillator are phase-compared, and the phase-compared output is input to a loop filter, and in the synchronized state, the output of the loop filter is used as the control voltage of the voltage controlled oscillator as the input of the voltage controlled oscillator. A voltage that gradually changes from OV to a power supply voltage in an out-of-synchronization state is applied to the input terminal of the voltage controlled oscillator as a control voltage of the voltage controlled oscillator, and an output signal is output from the output terminal of the voltage controlled oscillator. A phase-locked circuit configured to obtain
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62023033A JPS63190426A (en) | 1987-02-02 | 1987-02-02 | Phase locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62023033A JPS63190426A (en) | 1987-02-02 | 1987-02-02 | Phase locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190426A true JPS63190426A (en) | 1988-08-08 |
Family
ID=12099159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62023033A Pending JPS63190426A (en) | 1987-02-02 | 1987-02-02 | Phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190426A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008126223A1 (en) * | 2007-03-29 | 2008-10-23 | Fujitsu Limited | Digital phase synchronizing circuit and digital phase synchronizing circuit control method |
-
1987
- 1987-02-02 JP JP62023033A patent/JPS63190426A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008126223A1 (en) * | 2007-03-29 | 2008-10-23 | Fujitsu Limited | Digital phase synchronizing circuit and digital phase synchronizing circuit control method |
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