JPS58148568A - Gate circuit of synchronizing signal - Google Patents

Abstract

PURPOSE:To follow sufficiently the timewise fluctuation of an input signal, by providing a gate circuit extracting an output signal, and a PLL circuit functions to lock in phase between each output signal received from the gate circuit and each prescribed timing. CONSTITUTION:The timing of leading of the input signal Si is coincident with that of an AND output AO of an AND gate 2. The timing of leading of the output AO is coincident with that of an output signal SO. A PLL circuit comprising a phase comparator 5, an LPF6, a voltage controlled oscillator 7, and monostable multivibrators 8, 9 is phase-locked at the timing of leading of the signal SO, and this timing is almost coincident with the timing of leading of the signal Si. Thus, when the leading of the signal Si is in the open state period of the gate circuit and fluctuated in the range of tau1+tau2 (where; tau1 and tau2 are output pulse widths of the monostable multivibrators 8, 9 respectively), the timing of leading of the signal Si follows the timing of leading immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous signal gate circuit for extracting only a desired timing from an input signal repeatedly supplied and on which noise is superimposed to produce an output signal.

As a conventional means for reducing 0 to 011, there is a method in which a threshold value is provided for one noise N, as shown in FIG. However, according to this method, all the noise N that exceeds the threshold is obtained as an output signal, so it is not suitable for input signals where high-level noise N is easily superimposed. Met.

For this reason, the following measures have been proposed. For example, the second
As shown in the figure and FIG.
Vco ) 22- is supplied to a phase-locked loop (PLL) circuit composed of PLL circuits 22- to obtain an output signal synchronized with the rising edge of input signal P1. In other words, even if noise N is superimposed on the input signal Pi and this results in a change in the output of the phase comparison 6, by selecting the cutoff frequency of the low-pass filter 21 to be sufficiently low, V
The transmission to CO22 is blocked so that the influence of the noise N does not appear on the output signal.

However, according to such means, the input signal P1 becomes small over time, such as when the input signal P1 is a horizontal synchronization signal in a video signal, and this synchronization signal is used to correct the time axis of a video signal reproducing device. When a range fluctuation occurs, the fluctuation frequency is a high frequency rounding, and the VC operates through a low-pass filter 4 with a low cut-off frequency.
The output change of O22 cannot be obtained io, that is, the input signal P
The output signals have sufficient followability for fluctuations in l.
When applied to the above-mentioned apparatus, there is a drawback that satisfactory time axis correction cannot be performed.

The present invention has been made in order to rectify such conventional drawbacks.The present invention has been made to eliminate the influence of noise added to the input signal, and to provide an output that has sufficient followability in accordance with the temporal fluctuations of the input signal. An object of the present invention is to provide a synchronous signal gate circuit for obtaining a signal.

The present invention will be explained below based on the drawings.

FIGS. 4 and 5 show an embodiment of the present invention.

, in the figure, reference numeral 1 is a terminal that supplies the input signal St, and this terminal 1 is one input terminal Kw! of the AND gate 2.
It is threaded. The AND output signal of the AND gate 2 is supplied to one input terminal of an OR gate 3, and an output signal 8 is obtained from a terminal 4 connected to the output terminal thereof. Further, the output signal S is fed back and supplied to the input end of the phase comparator 5, and the output of this phase comparator 5 is supplied to the low-pass filter 6, so that only the DC and low frequency components are passed. Further, the output of the low-pass filter 6 is supplied to the VCO 7, and the ρVCO 7 provides an output vO with an oscillation frequency proportional to the input voltage.

Then, the output Vo of the VCO 7 triggers the first monostable multivibrator 8 to output a pulse Q1 with a pulse width τ1.
to occur. Further, the first monostable multivibrator 8 is connected to the second monostable multivibrator 9 to generate an output pulse Q2 with a pulse width τ2, and this pulse Q
2 is supplied to the other input terminal of the phase comparator 5 mentioned above.

On the other hand, the concave force (■) of the VCO 7 is supplied to the clear terminal CLR of the D-type flip 70 tube 10 and acts as a clear signal, and the clock terminal CKK of this 7-lip flop 10 is connected to the output pulse Q2 of the second monostable I multivibrator 9. Supplied. Further, a high level signal H is always supplied to the input end of the D-type flip-flop 100, and the output DO at the output end Q thereof is supplied to the other input end of the OR gate 3. The D-type flip-flop is configured as a 7 flip-flop with 10ti negative edge triggers.

Furthermore, the VCO7o output Vo is the AND gate 2
is supplied to the other input end of the .

Thus, and gate 2. The OR gate 3 and the D-type 7 lip-flop 10 constitute a gate circuit, which includes a phase comparator 6S, an O-pass filter 6, a VCO 7° first and second
The monostable multivibrators 8 and 9 constitute a PLL circuit, and the first and second monostable multivibrators 8 and 9 constitute a delay circuit.

Next, the operation of the circuit according to this embodiment will be explained with reference to FIG. Note that the waveforms of each signal shown in FIG. 5 are the same when the circuit reaches a steady state.

The input signal ε1 is repeatedly supplied to the AND gate 2, but in this case, the rising timing M1 of the input signal S1 is the rising timing M2 of the AND output cover of the AND gate 2.
is consistent with Moreover, the timing h of the rise of the AND output kalpa matches the timing flow of the rise of the output hinoki,
VCO 7 of the PLL circuit operates in response to this output cycle.
The output Vo is located a time width τ1 before the rising timing Ms of the output signal □. This time width τ1 is similar to the pulse width τ1 of the output pulse Q1 of the first monostable multivibrator, and the output of the second monostable multivibrator 9 is triggered at 1 at the falling edge timing of this pulse Q1. Pulse 1;h
The timing of the falling edge of Fi 2 coincides with the rising timing of M5 of the output pulse of the D-type flip-flop 10. In other words, since the timing flow of the rising edge of the output pulse Q2 coincides with the timing of the falling edge of the output pulse Q1, the timing of the rising edge of the output pulse Q2 There is a timing flow for the rise of the output pulse).

In this way, the PLL circuit composed of the phase comparator 5 and the like is phase-synchronized at the rising timing Ms of the output signal S, and this timing h is always equal to the rising timing M+K of the input signal s1. We are doing so. In other words, if the timing M1 of the rise of the input signal S1 is within the range of τ1 before and τ2 after the timing of the rise of the output pulse Q2 of the second monostable multivibrator 9, For example, the timing h of the rising edge of the output signal S is set so as to coincide with the timing M1 of the rising edge of the input signal St.
Become. Therefore, the timing M1 of the rising edge of the input signal 81 has a time width τ1+, which is the open state period of the gate circuit.
When the output signal 81 fluctuates within the range of , the rising timing island of the output signal 81 immediately follows the rising timing M1 of the input signal 81.

Note that if the timing M1 of the rise of the input signal S1 causes a large fluctuation on the time axis and deviates from the range of time width τ10τ2, the timing island of the rise of the output signal will temporarily change to the output Vo of the VCO 7 or The timing Ma of the rise of the output pulse of the D-type slip 70 and the knob 10,
It is substituted by Ms and is located before and after the time width τ1+τ2. However, due to the action of PL'L recovery, VCO7
The oscillation frequency of the second monostable multivibrator 9 changes, and the rising timing M6 of the second monostable multivibrator 9 gradually coincides with the rising timing M1 of the input signal Sl. The speed of this matching can be increased by increasing the cutoff frequency of the low-pass filter 6.

Also, the noise r superimposed on the input signal StK has a time width τ1+τ
If it is outside the range of 2, even if it is continuously mixed in, it will not affect the output signal.

As explained above, according to the present invention, a gate circuit receives a synchronization signal as an input signal, remains open within a certain time width including a predetermined timing of the synchronization signal, and sequentially outputs output signals; Since it has a delay circuit that determines the fixed time width and a PLL circuit that synchronizes the phase of each output signal received from the gate circuit with each predetermined timing, the input signal does not fluctuate within the fixed time width. It is also possible to obtain an output signal that is constantly followed without sacrificing response speed, and to eliminate the influence of noise superimposed before and after the fluctuation range. therefore,
The present invention is applicable to a circuit in which the input signal is a separated horizontal synchronizing signal included in a video signal with a poor S/N ratio, and the resulting output signal is used for time base correction of a video signal reproducing device. It is extremely effective to apply

[Brief explanation of drawings]

Figures 1 to 3 are diagrams explaining conventional examples. Figure 1 is a timing chart when noise exceeding a threshold appears as an output, and Figure 2 is a block diagram when configured with a PLL circuit. 3 is a timing chart explaining the operation of the circuit shown in FIG. 2, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a timing chart explaining the operation of the circuit shown in FIG. 4. It is. 2...and gate, 3...or gate, 5...
Phase comparator, 6...low pass filter, 7...vc
o, s...first monostable multivibrator, 9
...Second monostable i multivibrator, 1o...D
Shape flip 70 tube. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] A gate circuit that receives a synchronization signal as an input signal, remains open within a certain time width including a predetermined timing of the synchronization signal, and sequentially outputs output signals, and a delay that determines the certain time width. What is claimed is: 1. A synchronizing signal gate circuit, comprising: a seven-way locked loop circuit for achieving phase synchronization between each output signal received from the gate circuit and each of the predetermined timings.