JPS61280123A - Pll circuit - Google Patents

Abstract

PURPOSE:To obtain a PLL circuit phase-locked to each frequency component inputted in this way by using the result of phase comparison of each frequency component to generate one control voltage, using the said control voltage to generate a master clock and applying frequency division to the master clock in response to each output signal frequency to obtain an output clock. CONSTITUTION:A phase comparator circuit uses two input signals Si, Ri to generate a voltage proportional to the phase difference DELTAtheta1 between the signals Si and Ri, a control voltage generating circuit 8 inputs DELTAtheta1-DELTAtheta3 to generate a control voltage Vc in a function form. The control voltage Vc is inputted to the voltage controlled oscillator 9 of the next stage, which generates a clock having a frequency deviation proportional to the input voltage Vc and the center frequency is set to one of three frequency common multiples. The clock is subjected to a frequency division by frequency dividers 10-12 to generate reference signals R1-R3. The output of the frequency dividers 10-12 is outputted from respective clock output terminals 16-18 via a delay or shaping circuits 13-15.

Description

Detailed Description of the Invention (Technical field to which the invention pertains) The present invention generates, for a composite signal having a plurality of frequency components, a plurality of clock signals that are synchronized with the signals of each frequency component and are in a synchronous relationship with each other. The present invention relates to a PLL circuit.

(Prior Art) In conventional circuits of this type, it has been common to configure a PLL circuit for each of a plurality of input frequency components. Therefore, the synchronization relationship between the plurality of clock signals obtained was not guaranteed.

For example, for an NTSC television signal, the vertical synchronization signal, horizontal synchronization signal, and color subcarrier signal have an integer ratio relationship to each other. For each, a vertical scanning signal, a horizontal scanning signal,
A PLL circuit is provided for color subcarrier recovery.

FIG. 1 is a schematic diagram of a circuit for explaining the conventional method, in which 100 is an input of an NTSC signal, 110, 120,
130 is a vertical synchronization signal, horizontal synchronization signal, and color subcarrier signal extraction circuit; 111, 121, and 131 are PLL circuits for each signal; and 112, 122, and 132 are vertical scanning signal, horizontal scanning signal, and signal generation circuits for synchronous detection. , 11
3, 123, and 133 are output terminals for each signal.

As is clear from the figure, each output signal operates in synchronization with the corresponding component of the input signal, but the synchronization conditions between the output signals are not guaranteed.

Normally, since there is a synchronous relationship between each component of the input signal, a synchronous relationship also occurs between the components of the output signal, but if the input signal is switched or one of the input signal components is affected by disturbances such as noise. If it changes, the integer ratio relationship or phase synchronization relationship of instantaneous frequencies between the respective components of the output signal cannot be maintained.

Therefore, in devices in fields such as image processing, when a regular integer ratio relationship or a phase synchronization relationship is required between output signal components, it is difficult to use conventional methods.

(Object of the Invention) The present invention provides a PLL circuit that synchronizes in phase with each input frequency component while maintaining an integer ratio relationship and a phase synchronization relationship of one frequency with respect to a plurality of output signals, regardless of the state of the input signal. It provides:

(Structure of the Invention) For this purpose, the present invention generates one control voltage based on the phase comparison result of each frequency component, generates one master clock using this control voltage, and adjusts the master clock to each output signal frequency. The output clock is obtained by dividing the frequency according to a frequency division ratio determined accordingly.

These methods are different from the prior art.

(Example) FIG. 2 is a diagram showing the configuration of the first example of the present invention,
1 is an input terminal, 2, 3.4 is an extraction circuit for each frequency component,
5, 6.7 are phase comparison circuits, 8 is a control voltage generation circuit, 9
is a voltage controlled oscillator, 10, 11, 12 are frequency dividers, 13
, 14.15 is a delay or shaping circuit, 16.17.18
is a clock output terminal.

This embodiment shows a circuit in which an NTSC television signal is input as an input signal, and vertical scanning, horizontal scanning, and color subcarrier clocks are obtained as output signals.

The NTSC signal inputted from the input terminal 1 is guided to extraction circuits 2, 3.4 for each frequency component.

The extraction circuit 2 separates the amplitude of the NTSC signal to extract a synchronization signal, and also extracts a vertical synchronization pulse by performing integration processing.

The extraction circuit 3 separates the amplitude of the NTSC signal to extract a synchronization signal, and also extracts a horizontal synchronization pulse by differential processing.

The extraction circuit 4 extracts the section after the horizontal synchronizing pulse from the NTSC signal, and extracts the color subcarrier using a bandpass filter.

Three extracted signals S1. S, , S, are led to phase comparator circuits 5, 6.7, respectively.

A reference signal R□IR1tR3 generated from frequency dividing circuits 10, 11, and 12, which will be described later, is input to each phase comparator.

In the phase comparator circuit, S
Phase difference between l and R, 60. Generates a voltage proportional to.

For example, the difference t between the rising time of Sl and the rising time of R,
A voltage Aθ proportional to (Sl)−t(Ri) is generated.

In the control voltage generation circuit 8, Δθ8. Δθ2. Δθ is input, and a control voltage Vc is generated according to a certain functional form.

The functional form of the control voltage generation circuit 8 is 1 freeze sum α1jθ1+
α2Δθ2+α, Δθ2 (α1.α2.α3 are constant coefficients)
Or, the maximum value Max(α1Δθ8.a, Aθ2.α1
Δθ3) etc.

The control voltage Vc is input to the voltage controlled oscillator 9 at the next stage.

The voltage controlled oscillator 9 generates a clock having a frequency deviation proportional to the input voltage Vc. The center frequency is set to one of the common multiples of the three frequencies.

This clock is frequency-divided by frequency dividers 10, 11, and 12 to generate a reference signal R□tLtL. Frequency divider 10, 11, 12
The outputs are outputted from respective clock output terminals 16, 17, and 18 after passing through delay or shaping circuits 13, 14, and 15.

FIG. 3 is a diagram showing the configuration of a second embodiment of the present invention.

The difference from FIG. 2 is that the output of frequency divider 10 resets other frequency dividers 11 and 12.

That is, the other frequency components are phase-synchronized with the clock having the lowest frequency component. If the phase conditions for each of the three frequency components of the input signal are determined,
This method is necessary.

FIG. 4 is an explanatory diagram showing one method of generating a control voltage according to the present invention, and is intended to explain that a desired operation can be realized by using the above-described configuration.

As an input signal, the frequency ratio is f□:f, :f, = 1:2
Consider a signal with three frequency components: :4.

If the time difference between the input signal and the reference clock is At, the phase difference between each component can be expressed as lθ□, ΔθltJθ3 in the figure.

1Δθ, 1〉π/2, then 10.

11iθ, 1≦π/2, 11θ21>π/2, Ad,
, otherwise Aθ, and set it as Vc, V in the same figure
The characteristics of c are obtained.

Now, assuming that At is π/f, the voltage controlled oscillator is driven by the control voltage Vc in the section (2), that is, the phase difference -θ1 of the f4 configuration, and the time difference Δt changes in the direction of the boundary between (2) and (2).

When entering (2), the voltage controlled oscillator is similarly driven by the phase difference Δθ2 of the f2 configuration, and At reaches the boundary between (2) and (2).

In (2), 4t stops at O as a stable point due to the phase difference tθ3 of the f3 configuration.

As a result, the clock is sequentially adjusted in the phase direction in which the phase difference becomes 0 from the lowest frequency component, and finally the phase difference of the highest frequency component becomes 0 and becomes stable.

The method for creating Vc in Figure 4 is generally 1Δθ11〉π piece, then Vc=Jθ1 outside the above, 1Δθ
21〉π piece, then Vc=Δθ2 Outside the above, IAθn-4
If 1>π dimension - then vc=Δθ. −□Other than the above
This can be obtained by setting Vc=Δθ7.

Note that the functional form of Vc is, if Jt>O, then Vc>O1Δ
If t<O, then Vc<O; if Δ1=0, then Vc=O.

Any other functional form may be used as long as it holds.

For example, vc=α, θ1+α2θ2+...order α
. θ. , Vc = Maxabs (a 1θ0.α2
θ2. ......, α7θn), (Maxabs is a function that selects the one with the maximum absolute value, α1..., α
1 is a coefficient. ) etc. are fine.

(Effects of the Invention) As explained above, according to the present invention, for a signal having a plurality of frequency components, phase synchronization is achieved with each frequency component, and the frequency ratio between each component is determined in advance. Since it is possible to generate a clock having an integer ratio, it is effective to use it as a clock generation device for a device that processes a signal formatted by signals of a plurality of frequency components, such as in one image communication.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a circuit for explaining the conventional method, FIG. 2 is a diagram showing the configuration of a first embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a second embodiment of the present invention. FIG. 4 is an explanatory diagram showing one method of generating a control voltage according to the present invention. 1...Input terminal. 2, 3.4... Frequency component extraction circuit. 5.6.7... Phase comparison circuit, 8... Control voltage generation circuit, 9... Voltage controlled oscillator, 10, 11, 12... Frequency divider, 13.14, 15... Delay or molded circuit, 16
．． 17, 18... Clock output terminals. Patent applicant Nippon Telegraph and Telephone Corporation Figure 4

Claims (4)

[Claims] (1) Multiple frequency components k_1f_■, k_2f_■,
..., k_nf_0(k_1, k_2, ..., k_
n is an integer), and the i-th signal (i=1
, 2, ..., n), its component k_
if_0, a function to detect the phase difference Δθ_i between the extracted signal and the i-th reference signal R_i, and Δθ_i (i=1, 2, ..., n) are input and one A circuit that generates a control voltage Vc, a voltage controlled oscillator that is driven by Vc, oscillates with one of the common multiples of each frequency component k_if_0 as the center frequency, and whose frequency deviates in proportion to Vc, and an output of the voltage controlled oscillator. and a frequency dividing circuit that divides each frequency and generates the reference signal R_i (i=1, 2, . . . , n), and generates a plurality of signals phase-synchronized with each frequency component of the composite signal. A PLL circuit featuring: (2) In the circuit that generates the control voltage Vc, a coefficient α_i is determined for the phase difference Δθ_i of each component, and Vc=α_1
Δθ_1+α_2Δθ_2+・・・・・・+α_nΔθ
The PLL circuit according to claim 1, wherein the PLL circuit generates a control voltage as _n. (3) In the circuit that generates the control voltage Vc, α_iΔ
The control voltage according to claim (1) is characterized in that the maximum absolute value of θ_i (i=1, 2, . . . , n) is defined as α_mΔθ_m, and the control voltage is generated with Vc=α_mΔθ_m. PLL circuit. (4) In the circuit that generates the control voltage Vc, k_1>
When k_2>k_3...>k_n, |Δ
If θ_1 | > k_1/k_2, Vc = Δθ_1 Outside the above, | Δθ_2 | > k_2/k_3, Vc = Δθ_2
Outside the above, if |Δθ_3|>k_3/k_4, Vc=Δ
θ_3: Outside the above |Δθ_n_-_1|>k_n_-_1/k_
If n, Vc = Δθ_n_-_1 Outside of the above, Vc = Δθ_
The PLL circuit according to claim 1, wherein the PLL circuit generates a control voltage as n.